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Commit d7e78d92 authored by Andrey Filippov's avatar Andrey Filippov
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debugging error handling

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.project
View file @ d7e78d92
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160208095139740.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160208171112129.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160208095139740.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160208171112129.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160208095350202.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160208171331975.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160208095139740.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160208171112129.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160208095350202.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160208171331975.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160208095350202.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160208171331975.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160208095350202.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160208171331975.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160208095350202.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160208171331975.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160208095350202.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160208171331975.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160208095139740.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160208171112129.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_dma.v
View file @ d7e78d92
...@@ -345,13 +345,13 @@ module ahci_dma ( ...@@ -345,13 +345,13 @@ module ahci_dma (
if (cmd_start) dev_wr_mclk <= dev_wr; if (cmd_start) dev_wr_mclk <= dev_wr;
if (mrst) cmd_busy <= 0; if (mrst || cmd_abort) cmd_busy <= 0;
else if (cmd_start) cmd_busy <= 1; else if (cmd_start) cmd_busy <= 1;
else if (cmd_done) cmd_busy <= 0; else if (cmd_done) cmd_busy <= 0;
if (mrst) ct_busy <= 0; if (mrst || cmd_abort) ct_busy <= 0;
else if (cmd_start) ct_busy <= 1; else if (cmd_start) ct_busy <= 1;
else if (ct_done_mclk) ct_busy <= 0; else if (ct_done_mclk) ct_busy <= 0;
if (mrst) afi_arcache <= 4'h3; if (mrst) afi_arcache <= 4'h3;
else if (set_axi_rd_cache_mode) afi_arcache <= axi_rd_cache_mode; else if (set_axi_rd_cache_mode) afi_arcache <= axi_rd_cache_mode;
...@@ -379,11 +379,6 @@ module ahci_dma ( ...@@ -379,11 +379,6 @@ module ahci_dma (
always @ (posedge hclk) begin always @ (posedge hclk) begin
hrst_r <= hrst; hrst_r <= hrst;
// axi_dirty_r <= (|afi_wacount) || (|afi_rcount); // afi_wacount of afi_rcount are non-zero (assuming afi_wcount should be zero as addresses are posted first
// if (abort_or_reset && axi_dirty_r) abort_busy_hclk <= 1'b1;
addr_data_rq_r <= addr_data_rq_w; addr_data_rq_r <= addr_data_rq_w;
...@@ -400,21 +395,21 @@ module ahci_dma ( ...@@ -400,21 +395,21 @@ module ahci_dma (
// overall sequencing makes sure that there will be no new requests until older served // overall sequencing makes sure that there will be no new requests until older served
// additionally they are mutuially exclusive - only one may be pending at a time // additionally they are mutuially exclusive - only one may be pending at a time
if (hrst) raddr_ct_pend <= 0; if (hrst || cmd_abort_hclk) raddr_ct_pend <= 0;
else if (raddr_ct_rq) raddr_ct_pend <= 1; else if (raddr_ct_rq) raddr_ct_pend <= 1;
else if (axi_set_raddr_ready) raddr_ct_pend <= 0; else if (axi_set_raddr_ready) raddr_ct_pend <= 0;
if (hrst) raddr_prd_pend <= 0; if (hrst || cmd_abort_hclk) raddr_prd_pend <= 0;
else if (raddr_prd_rq) raddr_prd_pend <= 1; else if (raddr_prd_rq) raddr_prd_pend <= 1;
else if (axi_set_raddr_ready) raddr_prd_pend <= 0; else if (axi_set_raddr_ready) raddr_prd_pend <= 0;
if (hrst) raddr_data_pend <= 0; if (hrst || cmd_abort_hclk) raddr_data_pend <= 0;
else if (raddr_data_rq) raddr_data_pend <= 1; else if (raddr_data_rq) raddr_data_pend <= 1;
else if (axi_set_raddr_ready) raddr_data_pend <= 0; else if (axi_set_raddr_ready) raddr_data_pend <= 0;
if (hrst) waddr_data_pend <= 0; if (hrst || cmd_abort_hclk) waddr_data_pend <= 0;
else if (waddr_data_rq) waddr_data_pend <= 1; else if (waddr_data_rq) waddr_data_pend <= 1;
else if (axi_set_waddr_ready) waddr_data_pend <= 0; else if (axi_set_waddr_ready) waddr_data_pend <= 0;
if (hrst) {is_ct_addr, is_prd_addr, is_data_addr} <= 0; if (hrst) {is_ct_addr, is_prd_addr, is_data_addr} <= 0;
else if (raddr_ct_rq || raddr_prd_rq || wcount_set) {is_ct_addr, is_prd_addr, is_data_addr} <= {raddr_ct_rq, raddr_prd_rq, wcount_set}; else if (raddr_ct_rq || raddr_prd_rq || wcount_set) {is_ct_addr, is_prd_addr, is_data_addr} <= {raddr_ct_rq, raddr_prd_rq, wcount_set};
...@@ -572,8 +567,8 @@ module ahci_dma ( ...@@ -572,8 +567,8 @@ module ahci_dma (
.WCNT_BITS (21), .WCNT_BITS (21),
.ADDRESS_BITS (3) .ADDRESS_BITS (3)
) ahci_dma_rd_fifo_i ( ) ahci_dma_rd_fifo_i (
.mrst (mrst), // input .mrst (mrst || abort_busy_mclk), // input
.hrst (hrst), // input .hrst (hrst || cmd_abort_hclk), // input
.mclk (mclk), // input .mclk (mclk), // input
.hclk (hclk), // input .hclk (hclk), // input
.wcnt (wcount[21:1]), // input[20:0] .wcnt (wcount[21:1]), // input[20:0]
...@@ -596,29 +591,27 @@ module ahci_dma ( ...@@ -596,29 +591,27 @@ module ahci_dma (
.WCNT_BITS (21), .WCNT_BITS (21),
.ADDRESS_BITS (3) .ADDRESS_BITS (3)
) ahci_dma_wr_fifo_i ( ) ahci_dma_wr_fifo_i (
.mrst (mrst), // input .mrst (mrst || abort_busy_mclk), // input
.hrst (hrst), // input .hrst (hrst ||cmd_abort_hclk), // input
.mclk (mclk), // input .mclk (mclk), // input
.hclk (hclk), // input .hclk (hclk), // input
.wcnt (wcount[21:1]), // input[20:0] .wcnt (wcount[21:1]), // input[20:0]
.woffs (data_addr[2:1]), // input[1:0] .woffs (data_addr[2:1]), // input[1:0]
.init (cmd_start_hclk), // input .init (cmd_start_hclk), // input
.start (prd_wr), // input .start (prd_wr), // input
.dout (afi_wdata), // output[63:0] reg .dout (afi_wdata), // output[63:0] reg
// .dout_av (), // input // .dout_av (), // input
.dout_av_many (afi_wcount_many),// input .dout_av_many (afi_wcount_many), // input
.last_prd (last_prd), // input .last_prd (last_prd), // input
.dout_we (afi_wvalid_data),// output .dout_we (afi_wvalid_data), // output
.dout_wstb (afi_wstb4), // output[3:0] reg .dout_wstb (afi_wstb4), // output[3:0] reg
.done (done_dev_rd), // output reg .done (done_dev_rd), // output reg
.busy (), // output .busy (), // output
.fifo_nempty_mclk (fifo_nempty_mclk), // output reg .fifo_nempty_mclk (fifo_nempty_mclk), // output reg
.din (sys_in), // input[31:0] .din (sys_in), // input[31:0]
.din_rdy (sys_nfull), // output .din_rdy (sys_nfull), // output
.din_avail (sys_we) // input .din_avail (sys_we) // input
); );
// mclk -> hclk cross-clock synchronization // mclk -> hclk cross-clock synchronization
pulse_cross_clock #( pulse_cross_clock #(
.EXTRA_DLY(0) .EXTRA_DLY(0)
......
ahci/ahci_fis_receive.v
View file @ d7e78d92
...@@ -34,6 +34,7 @@ module ahci_fis_receive#( ...@@ -34,6 +34,7 @@ module ahci_fis_receive#(
)( )(
input hba_rst, // @posedge mclk - sync reset input hba_rst, // @posedge mclk - sync reset
input mclk, // for command/status input mclk, // for command/status
input pcmd_st_cleared, // ~= hba_rst?
// Control Interface // Control Interface
output reg fis_first_vld, // fis_first contains valid FIS header, reset by get_* output reg fis_first_vld, // fis_first contains valid FIS header, reset by get_*
// Debug features // Debug features
...@@ -241,8 +242,8 @@ localparam DATA_TYPE_ERR = 3; ...@@ -241,8 +242,8 @@ localparam DATA_TYPE_ERR = 3;
assign fis_first_invalid = fis_first_invalid_r; assign fis_first_invalid = fis_first_invalid_r;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (hba_rst || dma_in_stop) dma_in <= 0; if (hba_rst || dma_in_stop || pcmd_st_cleared) dma_in <= 0;
else if (dma_in_start) dma_in <= 1; else if (dma_in_start) dma_in <= 1;
if (hba_rst) was_data_in <= 0; if (hba_rst) was_data_in <= 0;
else was_data_in <= {was_data_in[0], hba_data_in_ready}; else was_data_in <= {was_data_in[0], hba_data_in_ready};
...@@ -254,7 +255,7 @@ localparam DATA_TYPE_ERR = 3; ...@@ -254,7 +255,7 @@ localparam DATA_TYPE_ERR = 3;
else if ((dma_in_valid && data_in_dwords_r[11]) || else if ((dma_in_valid && data_in_dwords_r[11]) ||
(wreg_we_r && dwords_over)) too_long_err <= 1; (wreg_we_r && dwords_over)) too_long_err <= 1;
if (hba_rst || dma_in_start) fis_extra_r <= 0; if (hba_rst || dma_in_start || pcmd_st_cleared) fis_extra_r <= 0;
else if (data_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && dma_prds_done) fis_extra_r <= 1; else if (data_in_ready && (hba_data_in_type == DATA_TYPE_DMA) && dma_prds_done) fis_extra_r <= 1;
...@@ -294,13 +295,12 @@ localparam DATA_TYPE_ERR = 3; ...@@ -294,13 +295,12 @@ localparam DATA_TYPE_ERR = 3;
end end
if (hba_rst) fis_rec_run <= 0; if (hba_rst || pcmd_st_cleared) fis_rec_run <= 0;
else if (get_fis) fis_rec_run <= 1; else if (get_fis) fis_rec_run <= 1;
else if (is_fis_end && data_in_ready) fis_rec_run <= 0; else if (is_fis_end && data_in_ready) fis_rec_run <= 0;
if (hba_rst ||get_fis) dwords_over <= 0; if (hba_rst ||get_fis || pcmd_st_cleared) dwords_over <= 0;
else if (wreg_we_r && !(|fis_dcount)) dwords_over <= 1; else if (wreg_we_r && !(|fis_dcount)) dwords_over <= 1;
/// else if (wreg_we_r && (!(|fis_dcount) || is_fis_end)) dwords_over <= 1;
if (hba_rst) wreg_we_r <= 0; if (hba_rst) wreg_we_r <= 0;
else wreg_we_r <= fis_rec_run && data_in_ready && !is_fis_end && !dwords_over && (|fis_dcount || !wreg_we_r) && else wreg_we_r <= fis_rec_run && data_in_ready && !is_fis_end && !dwords_over && (|fis_dcount || !wreg_we_r) &&
...@@ -308,7 +308,7 @@ localparam DATA_TYPE_ERR = 3; ...@@ -308,7 +308,7 @@ localparam DATA_TYPE_ERR = 3;
fis_end_r <= {fis_end_r[0], fis_end_w}; fis_end_r <= {fis_end_r[0], fis_end_w};
if (hba_rst) get_fis_busy_r[0] <= 0; if (hba_rst || pcmd_st_cleared) get_fis_busy_r[0] <= 0;
else if (get_fis) get_fis_busy_r[0] <= 1; else if (get_fis) get_fis_busy_r[0] <= 1;
else if (too_long_err || fis_end_w) get_fis_busy_r[0] <= 0; else if (too_long_err || fis_end_w) get_fis_busy_r[0] <= 0;
...@@ -316,10 +316,8 @@ localparam DATA_TYPE_ERR = 3; ...@@ -316,10 +316,8 @@ localparam DATA_TYPE_ERR = 3;
get_fis_done <= get_fis_busy_r[0] && (too_long_err || fis_end_w); get_fis_done <= get_fis_busy_r[0] && (too_long_err || fis_end_w);
/// if (hba_rst || get_fis) fis_first_vld <= 0; if (hba_rst || (|get_fis_busy_r) || pcmd_st_cleared) fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
/// if (hba_rst || fis_end_w) fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis else if (is_FIS_HEAD) fis_first_vld <= 1;
if (hba_rst || (|get_fis_busy_r))fis_first_vld <= 0; // is_FIS_HEAD stays on longer than just get_fis
else if (is_FIS_HEAD) fis_first_vld <= 1;
if (hba_rst || get_fis) fis_ok <= 0; if (hba_rst || get_fis) fis_ok <= 0;
else if (fis_end_w) fis_ok <= hba_data_in_type == DATA_TYPE_OK; else if (fis_end_w) fis_ok <= hba_data_in_type == DATA_TYPE_OK;
...@@ -356,6 +354,7 @@ localparam DATA_TYPE_ERR = 3; ...@@ -356,6 +354,7 @@ localparam DATA_TYPE_ERR = 3;
else if (update_prdbc_r) reg_addr <= CLB_OFFS32 + 1; // location of PRDBC else if (update_prdbc_r) reg_addr <= CLB_OFFS32 + 1; // location of PRDBC
if (reg_d2h || reg_sdb[0] || reg_ds[0]) fis_i <= hba_data_in[14]; if (reg_d2h || reg_sdb[0] || reg_ds[0]) fis_i <= hba_data_in[14];
if (reg_sdb) sdb_n <= hba_data_in[15]; if (reg_sdb) sdb_n <= hba_data_in[15];
if (reg_ds[0]) {dma_a,dma_d} <= {hba_data_in[15],hba_data_in[13]}; if (reg_ds[0]) {dma_a,dma_d} <= {hba_data_in[15],hba_data_in[13]};
...@@ -381,7 +380,6 @@ localparam DATA_TYPE_ERR = 3; ...@@ -381,7 +380,6 @@ localparam DATA_TYPE_ERR = 3;
xfer_cntr_zero_r <= xfer_cntr_r[31:2] == 0; xfer_cntr_zero_r <= xfer_cntr_r[31:2] == 0;
update_err_sts_r <= update_pio || update_err_sts || clear_bsy_drq || set_bsy || set_sts_7f || set_sts_80; update_err_sts_r <= update_pio || update_err_sts || clear_bsy_drq || set_bsy || set_sts_7f || set_sts_80;
// update_pio_r <= update_pio;
update_prdbc_r <= update_prdbc; // same latency as update_err_sts update_prdbc_r <= update_prdbc; // same latency as update_err_sts
update_sig_r <= update_sig && pUpdateSig_r; // do not update if not requested update_sig_r <= update_sig && pUpdateSig_r; // do not update if not requested
...@@ -395,10 +393,9 @@ localparam DATA_TYPE_ERR = 3; ...@@ -395,10 +393,9 @@ localparam DATA_TYPE_ERR = 3;
else if (store_sig[3]) sig_available <= 1; else if (store_sig[3]) sig_available <= 1;
// Maybe it is not needed if the fsm will send this pulse? // Maybe it is not needed if the fsm will send this pulse?
// data_in_words_apply <= dma_in_stop && (hba_data_in_type == DATA_TYPE_OK);
if (hba_rst || (|get_fis_busy_r)) fis_first_invalid_r <= 0; if (hba_rst || (|get_fis_busy_r) ||pcmd_st_cleared) fis_first_invalid_r <= 0;
else fis_first_invalid_r <= is_FIS_NOT_HEAD; else fis_first_invalid_r <= is_FIS_NOT_HEAD;
if (!fis_first_invalid_r) fis_first_flushing_r <= 0; if (!fis_first_invalid_r) fis_first_flushing_r <= 0;
else if (fis_first_flush) fis_first_flushing_r <= 1; else if (fis_first_flush) fis_first_flushing_r <= 1;
......
ahci/ahci_fis_transmit.v
View file @ d7e78d92
...@@ -30,6 +30,7 @@ module ahci_fis_transmit #( ...@@ -30,6 +30,7 @@ module ahci_fis_transmit #(
)( )(
input hba_rst, // @posedge mclk - when port is reset (even COMINIT)? input hba_rst, // @posedge mclk - when port is reset (even COMINIT)?
input mclk, // for command/status input mclk, // for command/status
input pcmd_st_cleared, // ~= hba_rst?
// Command pulses to execute states // Command pulses to execute states
input fetch_cmd, // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS) input fetch_cmd, // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS)
// wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd // wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd
...@@ -232,45 +233,35 @@ module ahci_fis_transmit #( ...@@ -232,45 +233,35 @@ module ahci_fis_transmit #(
always @ (posedge mclk) begin always @ (posedge mclk) begin
// Mutliplex between DMA and FIS output to the output routed to transmit FIFO // Mutliplex between DMA and FIS output to the output routed to transmit FIFO
// Count bypassing DMA dwords to generate FIS_last condition? // Count bypassing DMA dwords to generate FIS_last condition?
if (hba_rst) todev_full_r <= 0; if (hba_rst || pcmd_st_cleared) todev_full_r <= 0;
else if (write_or_w) todev_full_r <= 1; // do not fill the buffer if FIFO is not ready else if (write_or_w) todev_full_r <= 1; // do not fill the buffer if FIFO is not ready
else if (todev_ready) todev_full_r <= 0; else if (todev_ready) todev_full_r <= 0;
if (write_or_w) todev_data <= dma_en_r? dma_out: fis_data_out; if (write_or_w) todev_data <= dma_en_r? dma_out: fis_data_out;
if (hba_rst) todev_type <= 3; // invalid? - no, now first and last word in command FIS (impossible?) if (hba_rst) todev_type <= 3; // invalid? - no, now first and last word in command FIS (impossible?)
else if (write_or_w) todev_type <= dma_en_r? {dx_dma_last_w , 1'b0} : fis_data_type; else if (write_or_w) todev_type <= dma_en_r? {dx_dma_last_w , 1'b0} : fis_data_type;
// else if (was_dma_ndav[1]) todev_type <= {1'b1, 1'b0}; // type = last in FIS
// if (hba_rst) was_dma_ndav <= 0;
// else was_dma_ndav <= {was_dma_ndav[1:0], ~dma_dav & todev_full_r & watch_prd_end_w} ;
// if (hba_rst || dma_dav || !todev_full_r || !watch_prd_end_w) was_dma_ndav <= 0;
// else was_dma_ndav <= (was_dma_ndav << 1) | 1;
// if (hba_rst || dx_xmit || done_w) watch_prd_end <= 0;
// else if (masked_last_h2d_data) watch_prd_end <= 1;
// Read 3 DWORDs from the command header // Read 3 DWORDs from the command header
if (hba_rst) fetch_chead_r <= 0; // running 1 if (hba_rst) fetch_chead_r <= 0; // running 1
else fetch_chead_r <= {fetch_chead_r[2:0], fetch_cmd}; else fetch_chead_r <= {fetch_chead_r[2:0], fetch_cmd};
if (hba_rst) fetch_chead_stb_r <= 0; if (hba_rst) fetch_chead_stb_r <= 0;
else fetch_chead_stb_r <= {fetch_chead_stb_r[2:0], pre_reg_stb && chead_bsy}; else fetch_chead_stb_r <= {fetch_chead_stb_r[2:0], pre_reg_stb && chead_bsy};
if (hba_rst) chead_bsy <= 0; if (hba_rst) chead_bsy <= 0;
else if (fetch_cmd) chead_bsy <= 1; else if (fetch_cmd) chead_bsy <= 1;
else if (chead_done_w) chead_bsy <= 0; else if (chead_done_w) chead_bsy <= 0;
if (hba_rst) chead_bsy_re <= 0; if (hba_rst) chead_bsy_re <= 0;
else if (fetch_cmd) chead_bsy_re <= 1; else if (fetch_cmd) chead_bsy_re <= 1;
else if (fetch_chead_r[1]) chead_bsy_re <= 0; // read 3 dwords else if (fetch_chead_r[1]) chead_bsy_re <= 0; // read 3 dwords
if (hba_rst) reg_re_r <= 0; // [0] -> reg_re output if (hba_rst) reg_re_r <= 0; // [0] -> reg_re output
else reg_re_r <= {reg_re[1:0], reg_re_w}; else reg_re_r <= {reg_re[1:0], reg_re_w};
if (fetch_cmd) reg_addr <= CLB_OFFS32; // there will be more conditions if (fetch_cmd) reg_addr <= CLB_OFFS32; // there will be more conditions
else if (reg_re_r[0]) reg_addr <= reg_addr + 1; else if (reg_re_r[0]) reg_addr <= reg_addr + 1;
// save command header data to registers // save command header data to registers
if (fetch_chead_stb_r[0]) begin if (fetch_chead_stb_r[0]) begin
...@@ -291,24 +282,21 @@ module ahci_fis_transmit #( ...@@ -291,24 +282,21 @@ module ahci_fis_transmit #(
else if (chead_done_w) pCmdToIssue_r <= 1; else if (chead_done_w) pCmdToIssue_r <= 1;
else if (clearCmdToIssue) pCmdToIssue_r <= 0; else if (clearCmdToIssue) pCmdToIssue_r <= 0;
if (hba_rst) fetch_cmd_busy_r <= 0; if (hba_rst || pcmd_st_cleared) fetch_cmd_busy_r <= 0;
else if (fetch_cmd) fetch_cmd_busy_r <= 1; else if (fetch_cmd) fetch_cmd_busy_r <= 1;
else if (dma_start) fetch_cmd_busy_r <= 0; else if (dma_start) fetch_cmd_busy_r <= 0;
//CFIS/ATAPI common //CFIS/ATAPI common
// if (hba_rst || cfis_xmit) anc_fis_r <= 0;
// else if (atapi_xmit) anc_fis_r <= 1;
// fetch and send command/atapi FIS // fetch and send command/atapi FIS
if (hba_rst || acfis_xmit_start_w) acfis_xmit_pend_r <= 0; if (hba_rst || acfis_xmit_start_w || pcmd_st_cleared) acfis_xmit_pend_r <= 0;
else if (cfis_xmit || atapi_xmit) acfis_xmit_pend_r <= 1; else if (cfis_xmit || atapi_xmit) acfis_xmit_pend_r <= 1;
acfis_xmit_start_r <= !hba_rst && acfis_xmit_start_w; acfis_xmit_start_r <= !hba_rst && acfis_xmit_start_w;
if (hba_rst) acfis_xmit_busy_r <= 0; if (hba_rst || pcmd_st_cleared) acfis_xmit_busy_r <= 0;
else if (acfis_xmit_start_r) acfis_xmit_busy_r <= 1; else if (acfis_xmit_start_r) acfis_xmit_busy_r <= 1;
else if (acfis_xmit_end) acfis_xmit_busy_r <= 0; else if (acfis_xmit_end) acfis_xmit_busy_r <= 0;
if (cfis_xmit) cfis_acmd_left_r <= ch_cmd_len_r[ 4: 0]; // Will assume that there is room for ... if (cfis_xmit) cfis_acmd_left_r <= ch_cmd_len_r[ 4: 0]; // Will assume that there is room for ...
else if (atapi_xmit) cfis_acmd_left_r <= (|xfer_cntr[31:4]) ? 5'h4 : {3'b0,xfer_cntr[3:2]}; else if (atapi_xmit) cfis_acmd_left_r <= (|xfer_cntr[31:4]) ? 5'h4 : {3'b0,xfer_cntr[3:2]};
...@@ -332,20 +320,18 @@ module ahci_fis_transmit #( ...@@ -332,20 +320,18 @@ module ahci_fis_transmit #(
//TODO: update xfer length, prdtl (only after R_OK) - yes, do it outside //TODO: update xfer length, prdtl (only after R_OK) - yes, do it outside
// if (dx_xmit) xfer_cntr_is_set <= !xfer_cntr_zero; // if it was zero - rely on PRDs
if (dx_xmit) dx_dwords_left[11:0] <= (xfer_cntr_zero || (|xfer_cntr[31:13])) ? 12'h800 : {1'b0,xfer_cntr[12:2]}; if (dx_xmit) dx_dwords_left[11:0] <= (xfer_cntr_zero || (|xfer_cntr[31:13])) ? 12'h800 : {1'b0,xfer_cntr[12:2]};
else if (dma_re_w) dx_dwords_left[11:0] <= dx_dwords_left[11:0] - 1; else if (dma_re_w) dx_dwords_left[11:0] <= dx_dwords_left[11:0] - 1;
if (dx_xmit) dwords_sent <= 0; if (dx_xmit) dwords_sent <= 0;
else if (dma_re_w) dwords_sent <= dwords_sent + 1; else if (dma_re_w) dwords_sent <= dwords_sent + 1;
// send FIS header // send FIS header
if (hba_rst || write_or_w) dx_fis_pend_r <= 0; if (hba_rst || write_or_w ||pcmd_st_cleared) dx_fis_pend_r <= 0;
else if (dx_xmit) dx_fis_pend_r <= 1; else if (dx_xmit) dx_fis_pend_r <= 1;
if (hba_rst || dx_dma_last_w || (|dx_err_r)) dma_en_r <= 0; if (hba_rst || dx_dma_last_w || (|dx_err_r) || pcmd_st_cleared) dma_en_r <= 0;
else if (dx_fis_pend_r && write_or_w) dma_en_r <= 1; else if (dx_fis_pend_r && write_or_w) dma_en_r <= 1;
// Abort on transmit errors // Abort on transmit errors
if (hba_rst || any_cmd_start) dx_err_r[0] <= 0; if (hba_rst || any_cmd_start) dx_err_r[0] <= 0;
...@@ -357,9 +343,7 @@ module ahci_fis_transmit #( ...@@ -357,9 +343,7 @@ module ahci_fis_transmit #(
if (hba_rst || any_cmd_start) dx_err_r[2] <= 0; if (hba_rst || any_cmd_start) dx_err_r[2] <= 0;
else if (xrdy_collision) dx_err_r[2] <= 1; else if (xrdy_collision) dx_err_r[2] <= 1;
if (hba_rst) dx_busy_r <= 0; // sending CFIS, AFIS or data FIS (until error or R_OK) if (hba_rst || pcmd_st_cleared) dx_busy_r <= 0; // sending CFIS, AFIS or data FIS (until error or R_OK)
// else if (dx_xmit) dx_busy_r <= 1;
// else if (dx_dma_last_w || (|dx_err_r)) dx_busy_r <= 0;
else if (dx_xmit || acfis_xmit_start_r) dx_busy_r <= 1; else if (dx_xmit || acfis_xmit_start_r) dx_busy_r <= 1;
else if (xmit_ok || (|dx_err_r)) dx_busy_r <= 0; else if (xmit_ok || (|dx_err_r)) dx_busy_r <= 0;
...@@ -369,14 +353,12 @@ module ahci_fis_transmit #( ...@@ -369,14 +353,12 @@ module ahci_fis_transmit #(
if (hba_rst) done <= 0; if (hba_rst) done <= 0;
else done <= done_w; else done <= done_w;
if (hba_rst) busy <= 0; if (hba_rst || pcmd_st_cleared) busy <= 0;
else if (any_cmd_start) busy <= 1; else if (any_cmd_start) busy <= 1;
else if (done_w) busy <= 0; else if (done_w) busy <= 0;
if (hba_rst) xmit_ok_r <= 0; if (hba_rst) xmit_ok_r <= 0;
else xmit_ok_r <= dx_busy_r && !(|dx_err_r) && xmit_ok; else xmit_ok_r <= dx_busy_r && !(|dx_err_r) && xmit_ok;
dma_cmd_abort <= done_w && (|dx_err_r); dma_cmd_abort <= done_w && (|dx_err_r);
......
ahci/ahci_sata_layers.v
View file @ d7e78d92
...@@ -138,6 +138,9 @@ module ahci_sata_layers #( ...@@ -138,6 +138,9 @@ module ahci_sata_layers #(
wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle wire ll_incom_start; // link -> // if started an incoming transaction assuming this and next 2 are single-cycle
wire ll_incom_done; // link -> // if incoming transition was completed wire ll_incom_done; // link -> // if incoming transition was completed
wire ll_incom_invalidate; // link -> // if incoming transition had errors wire ll_incom_invalidate; // link -> // if incoming transition had errors
reg ll_incom_invalidate_r; // error delayed by 1 clock - if eof was incorrect (because of earlier data error)
// let last data dword to pass through
// wire incom_ack_good = send_R_OK; // -> link // transport layer responds on a completion of a FIS // wire incom_ack_good = send_R_OK; // -> link // transport layer responds on a completion of a FIS
// wire incom_ack_bad = send_R_ERR; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle // wire incom_ack_bad = send_R_ERR; // -> link // oob sequence is reinitiated and link now is not established or rxelecidle
...@@ -176,6 +179,7 @@ module ahci_sata_layers #( ...@@ -176,6 +179,7 @@ module ahci_sata_layers #(
wire rxelsfull; wire rxelsfull;
wire rxelsempty; wire rxelsempty;
wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer
...@@ -262,7 +266,7 @@ module ahci_sata_layers #( ...@@ -262,7 +266,7 @@ module ahci_sata_layers #(
.link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle .link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction .sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception? .sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session .incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current receiving session
.link_established (link_established), .link_established (link_established),
// inputs from phy // inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established .phy_ready (phy_ready), // input wire // phy is ready - link is established
...@@ -277,14 +281,15 @@ module ahci_sata_layers #( ...@@ -277,14 +281,15 @@ module ahci_sata_layers #(
); );
always @ (posedge clk) begin always @ (posedge clk) begin
ll_incom_invalidate_r <= ll_incom_invalidate;
// FIS receive D2H // FIS receive D2H
// add head if ll_d2h_valid and (d2h_type_in == D2H_TYPE_OK) || (d2h_type_in == D2H_TYPE_ERR)? Or signal some internal error // add head if ll_d2h_valid and (d2h_type_in == D2H_TYPE_OK) || (d2h_type_in == D2H_TYPE_ERR)? Or signal some internal error
if (rst || ll_incom_start) d2h_type_in <= D2H_TYPE_FIS_HEAD; // FIS head if (rst || ll_incom_start) d2h_type_in <= D2H_TYPE_FIS_HEAD; // FIS head
else if (ll_d2h_valid) d2h_type_in <= D2H_TYPE_DMA; // FIS BODY else if (ll_d2h_valid) d2h_type_in <= D2H_TYPE_DMA; // FIS BODY
else if (ll_incom_done || ll_incom_invalidate) d2h_type_in <= ll_incom_invalidate ? D2H_TYPE_ERR: D2H_TYPE_OK; else if (ll_incom_done || ll_incom_invalidate_r) d2h_type_in <= ll_incom_invalidate_r ? D2H_TYPE_ERR: D2H_TYPE_OK;
if (rst) fis_over_r <= 0; if (rst) fis_over_r <= 0;
else fis_over_r <= (ll_incom_done || ll_incom_invalidate) && (d2h_type_in == D2H_TYPE_DMA); // make sure it is only once else fis_over_r <= (ll_incom_done || ll_incom_invalidate_r) && (d2h_type_in == D2H_TYPE_DMA); // make sure it is only once
// Second - generate internal error? // Second - generate internal error?
// FIS transmit H2D // FIS transmit H2D
...@@ -342,7 +347,7 @@ module ahci_sata_layers #( ...@@ -342,7 +347,7 @@ module ahci_sata_layers #(
.WIDTH(9) .WIDTH(9)
) fifo_h2d_control_i ( ) fifo_h2d_control_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst || pcmd_st_cleared), // input
.wr (h2d_fifo_wr), // input .wr (h2d_fifo_wr), // input
.rd (h2d_fifo_rd), // input .rd (h2d_fifo_rd), // input
.nempty (h2d_nempty), // output .nempty (h2d_nempty), // output
...@@ -376,7 +381,7 @@ module ahci_sata_layers #( ...@@ -376,7 +381,7 @@ module ahci_sata_layers #(
.WIDTH(9) .WIDTH(9)
) fifo_d2h_control_i ( ) fifo_d2h_control_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst || pcmd_st_cleared), // input
.wr (d2h_fifo_wr), // input .wr (d2h_fifo_wr), // input
.rd (d2h_fifo_rd), // input .rd (d2h_fifo_rd), // input
.nempty (d2h_nempty), // output .nempty (d2h_nempty), // output
......
ahci/ahci_top.v
View file @ d7e78d92
...@@ -246,7 +246,7 @@ module ahci_top#( ...@@ -246,7 +246,7 @@ module ahci_top#(
wire dma_cmd_start; // input wire dma_cmd_start; // input
wire dma_prd_start; // input wire dma_prd_start; // input
wire dma_cmd_abort_xmit; // input wire dma_cmd_abort_xmit; // input
wire dma_cmd_abort_fsm; // abort from FSM (also from ahci_fis_transmit) wire dma_cmd_abort_fsm; // abort from FSM (also from ahci_fis_transmit)
// Use some of the custom registers in the address space? // Use some of the custom registers in the address space?
wire [17:0] fsm_pgm_ad; // @aclk, address/data to program the AHCI FSM wire [17:0] fsm_pgm_ad; // @aclk, address/data to program the AHCI FSM
...@@ -896,7 +896,7 @@ module ahci_top#( ...@@ -896,7 +896,7 @@ module ahci_top#(
) ahci_fis_receive_i ( ) ahci_fis_receive_i (
.hba_rst (mrst), // input .hba_rst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
.pcmd_st_cleared (pcmd_st_cleared), // input
.fis_first_vld (frcv_first_vld), // output reg .fis_first_vld (frcv_first_vld), // output reg
.fis_first_invalid (frcv_first_invalid), // output .fis_first_invalid (frcv_first_invalid), // output
.fis_first_flush (frcv_first_flush), // input .fis_first_flush (frcv_first_flush), // input
......
py393sata/x393sata.py
View file @ d7e78d92
...@@ -730,6 +730,20 @@ sata.reg_status() ...@@ -730,6 +730,20 @@ sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4) _=mem.mem_dump (0x80000ff0, 4,4)
sata.reset_ie()
sata.dd_read_dma(0x100, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reset_ie()
sata.dd_read_dma(0x81, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
mem.write_mem(0x80000118,0x10) mem.write_mem(0x80000118,0x10)
......
tb_ahci_01.sav
View file @ d7e78d92
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Feb 8 16:49:44 2016 [*] Tue Feb 9 00:10:45 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160207225755387.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160208143933526.fst"
[dumpfile_mtime] "Mon Feb 8 05:59:18 2016" [dumpfile_mtime] "Mon Feb 8 21:40:58 2016"
[dumpfile_size] 10376737 [dumpfile_size] 10386281
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0 [timestart] 0
[size] 1823 1180 [size] 1823 1180
[pos] 1917 0 [pos] 1917 0
*-23.562601 38842258 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-23.562601 17391070 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
[treeopen] tb_ahci.dut. [treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i. [treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top. [treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
...@@ -1155,16 +1156,16 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn ...@@ -1155,16 +1156,16 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200 @1401200
-ahci_fsm -ahci_fsm
@800200 @c00200
-ahci_fis_receive -ahci_fis_receive
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
@c08029 @c08028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0] (1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
@1409201 @1401200
-group_end -group_end
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr[9:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr[9:0]
...@@ -1251,7 +1252,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0] ...@@ -1251,7 +1252,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0] (3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
@1001200 @1001200
-group_end -group_end
@1000200 @1401200
-ahci_fis_receive -ahci_fis_receive
@c00200 @c00200
-ahci_fis_transmit -ahci_fis_transmit
...@@ -1413,9 +1414,17 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_addr[31:1] ...@@ -1413,9 +1414,17 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_addr[31:1]
-group_end -group_end
@1401200 @1401200
-ahci_fis_transmit -ahci_fis_transmit
@c00200 @800200
-ahci_sata_layers -ahci_sata_layers
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_start
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_invalidate
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_wr
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type_in[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready
@22 @22
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_fill[9:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_fill[9:0]
...@@ -1462,6 +1471,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full ...@@ -1462,6 +1471,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full
- -
@1401200 @1401200
-fifo_h2d_control -fifo_h2d_control
@1000200
-ahci_sata_layers -ahci_sata_layers
@c00200 @c00200
-simul_axi_hp_wr -simul_axi_hp_wr
...@@ -2663,7 +2673,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full ...@@ -2663,7 +2673,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
- -
@1401200 @1401200
-ahci_dma -ahci_dma
@c00200 @800200
-link -link
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
...@@ -2756,7 +2766,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_send_data ...@@ -2756,7 +2766,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clr_send_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clr_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
@c00200 tb_ahci.dut.sata_top.ahci_sata_layers_i.link.incom_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc_good
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_goodend
@800200
-states -states
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
...@@ -2783,7 +2796,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold ...@@ -2783,7 +2796,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1401200 @1000200
-states -states
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset
...@@ -3039,7 +3052,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair ...@@ -3039,7 +3052,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@1401200 @1000200
-link -link
@c00200 @c00200
-phy -phy
......
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