Removed x393 as submodule, copied needed files only (to resolve future recursion)

.gitmodules

-[submodule "x393"]
-	path = x393
-	url = https://github.com/Elphel/x393.git

copy_from_x393.sh

+#!/bin/bash
+REPO_ROOT=".."
+CWD="$(pwd)"
+
+cd $REPO_ROOT
+cp -v --parents \
+x393/simulation_modules/simul_axi_master_wraddr.v \
+x393/simulation_modules/simul_axi_master_rdaddr.v \
+x393/simulation_modules/simul_axi_master_wdata.v \
+x393/simulation_modules/simul_axi_slow_ready.v \
+x393/simulation_modules/simul_axi_hp_rd.v \
+x393/simulation_modules/simul_axi_hp_wr.v \
+x393/simulation_modules/simul_axi_read.v \
+x393/util_modules/fifo_same_clock_fill.v \
+x393/util_modules/dly_16.v \
+x393/util_modules/axi_hp_clk.v \
+x393/simulation_modules/simul_fifo.v \
+x393/simulation_modules/simul_axi_fifo_out.v \
+x393/util_modules/dly01_16.v \
+x393/wrap/pll_base.v \
+x393/wrap/ram18p_var_w_var_r.v \
+x393/util_modules/fifo_sameclock_control.v \
+x393/util_modules/pulse_cross_clock.v \
+x393/axi/axibram_read.v \
+x393/wrap/ram_var_w_var_r.v \
+x393/wrap/ramt_var_wb_var_r.v \
+x393/util_modules/fifo_cross_clocks.v \
+x393/axi/axibram_write.v \
+x393/util_modules/fifo_same_clock.v \
+x393/util_modules/resync_data.v \
+x393/wrap/ramt_var_w_var_r.v \
+x393/glbl.v \
+$CWD
+cd $CWD

x393 @ 1e167c27

-Subproject commit 1e167c275aa336683875434b4ae406d803b3db3d

x393/glbl.v

+`timescale  1 ps / 1 ps
+module glbl ();
+    parameter ROC_WIDTH = 10000;// 100000;
+    parameter TOC_WIDTH = 0;
+
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire GSR;
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire GTS;
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire PRLD;
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire PLL_LOCKG;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	   GSR_int = 1'b1;
+	   PRLD_int = 1'b1;
+	   #(ROC_WIDTH)
+	   GSR_int = 1'b0;
+	   PRLD_int = 1'b0;
+    end
+
+    initial begin
+	   GTS_int = 1'b1;
+	   #(TOC_WIDTH)
+	   GTS_int = 1'b0;
+    end
+endmodule

x393/simulation_modules/simul_axi_fifo_out.v

+/**************************************
+* Module: simul_axi_fifo
+* Date:2014-03-23  
+* Author: Andrey Filippov     
+*
+* Description: 
+***************************************/
+`timescale 1ns/1ps
+
+module simul_axi_fifo
+#(
+  parameter integer WIDTH=  64,         // total number of output bits
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+  parameter integer FIFO_DEPTH=LATENCY+DEPTH+1
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+  input              clk,
+  input              reset,
+  input  [WIDTH-1:0] data_in,
+  input              load,
+  output             input_ready,
+  output [WIDTH-1:0] data_out,
+  output             valid,
+  input              ready);
+  
+  reg  [WIDTH-1:0]   fifo [0:FIFO_DEPTH-1];
+  integer            in_address;
+  integer            out_address;
+  integer            in_count;
+  integer            out_count;
+  reg    [LATENCY:0] latency_delay_r;
+  
+  wire [LATENCY+1:0] latency_delay={latency_delay_r,load};             
+  wire               out_inc=latency_delay[LATENCY];
+  
+  assign data_out=    fifo[out_address];
+  assign valid=       out_count!=0;
+  assign input_ready= in_count<DEPTH;
+//  assign out_inc={
+
+  always @ (posedge clk or posedge reset) begin
+    if (reset) latency_delay_r <= 0;
+    else       latency_delay_r <= latency_delay[LATENCY:0];
+
+    if    (reset)  in_address <= 0;
+    else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
+
+    if    (reset)            out_address <= 0;
+    else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
+    
+    if    (reset)                       in_count <= 0;
+    else if (!(valid && ready) && load) in_count <= in_count+1;
+    else if (valid && ready && !load)   in_count <= in_count-1;
+
+    if    (reset)                          out_count <= 0;
+    else if (!(valid && ready) && out_inc) out_count <= out_count+1;
+    else if (valid && ready && !out_inc)   out_count <= out_count-1;
+  end
+  always @ (posedge clk) begin
+    if (load) fifo[in_address] <= data_in;
+  end
+  
+endmodule
\ No newline at end of file

x393/simulation_modules/simul_axi_master_rdaddr.v

+/*******************************************************************************
+ * Module: simul_axi_master_rdaddr
+ * Date:2014-03-23  
+ * Author: Andrey Filippov     
+ * Description: Simulation model for AXI read address channel
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_axi_master_rdaddr.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_rdaddr.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+
+`timescale 1ns/1ps
+
+module simul_axi_master_rdaddr
+#(
+  parameter integer ID_WIDTH=12,
+  parameter integer ADDRESS_WIDTH=32,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+  
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      arid_in,
+    input  [ADDRESS_WIDTH-1:0] araddr_in,
+    input  [3:0]               arlen_in,
+    input  [1:0]               arsize_in,
+    input  [1:0]               arburst_in,
+    input  [3:0]               arcache_in,
+    input  [2:0]               arprot_in,
+
+    output [ID_WIDTH-1:0]      arid,
+    output [ADDRESS_WIDTH-1:0] araddr,
+    output [3:0]               arlen,
+    output [1:0]               arsize,
+    output [1:0]               arburst,
+    output [3:0]               arcache,
+    output [2:0]               arprot,
+    output                     arvalid,
+    input                      arready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+    wire [ID_WIDTH-1:0]      arid_out;
+    wire [ADDRESS_WIDTH-1:0] araddr_out;
+    wire [3:0]               arlen_out;
+    wire [1:0]               arsize_out;
+    wire [1:0]               arburst_out;
+    wire [3:0]               arcache_out;
+    wire [2:0]               arprot_out;
+    wire                     arvalid_out;
+    
+    assign #(DATA_DELAY) arid=    arid_out;
+    assign #(DATA_DELAY) araddr=  araddr_out;
+    assign #(DATA_DELAY) arlen=   arlen_out;
+    assign #(DATA_DELAY) arsize=  arsize_out;
+    assign #(DATA_DELAY) arburst= arburst_out;
+    assign #(DATA_DELAY) arcache= arcache_out;
+    assign #(DATA_DELAY) arprot=  arprot_out;
+    assign #(VALID_DELAY) arvalid=arvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+ADDRESS_WIDTH+15),     // total number of output bits
+      .LATENCY(LATENCY),                     // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                          // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({arid_in,araddr_in,arlen_in,arsize_in,arburst_in,arcache_in,arprot_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({arid_out,araddr_out,arlen_out,arsize_out,arburst_out,arcache_out,arprot_out}),    // output [WIDTH-1:0] data_out,
+    .valid(arvalid_out),       // output             valid,
+    .ready(arready));      //  input              ready);
+
+endmodule

x393/simulation_modules/simul_axi_master_wdata.v

+/*******************************************************************************
+ * Module: simul_axi_master_wdata
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI write data channel
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_master_wdata.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_wdata.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_master_wdata#(
+  parameter integer ID_WIDTH=12,
+  parameter integer DATA_WIDTH=32,
+  parameter integer WSTB_WIDTH= 4,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      wid_in,
+    input  [DATA_WIDTH-1:0]    wdata_in,
+    input  [WSTB_WIDTH-1:0]    wstrb_in,
+    input                      wlast_in,
+    output [ID_WIDTH-1:0]      wid,
+    output [DATA_WIDTH-1:0]    wdata,
+    output [WSTB_WIDTH-1:0]    wstrb,
+    output                     wlast,
+    output                     wvalid,
+    input                      wready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+
+    wire  [ID_WIDTH-1:0]      wid_out;
+    wire  [DATA_WIDTH-1:0]    wdata_out;
+    wire  [WSTB_WIDTH-1:0]    wstrb_out;
+    wire                      wlast_out;
+    wire                      wvalid_out;
+    
+    assign #(DATA_DELAY)  wid=    wid_out;
+    assign #(DATA_DELAY)  wdata=  wdata_out;
+    assign #(DATA_DELAY)  wstrb=  wstrb_out;
+    assign #(DATA_DELAY)  wlast=  wlast_out;
+    assign #(VALID_DELAY) wvalid= wvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+DATA_WIDTH+WSTB_WIDTH+1),  // total number of output bits
+      .LATENCY(LATENCY),                         // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                              // maximal number of commands in FIFO
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({wid_in, wdata_in, wstrb_in, wlast_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({wid_out, wdata_out, wstrb_out, wlast_out}),    // output [WIDTH-1:0] data_out,
+    .valid(wvalid_out),       // output             valid,
+    .ready(wready));          //  input              ready);
+
+endmodule
+

x393/simulation_modules/simul_axi_master_wraddr.v

+/*******************************************************************************
+ * Module: simul_axi_master_wraddr
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI write address channel
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_master_wraddr.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_wraddr.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_master_wraddr
+#(
+  parameter integer ID_WIDTH=12,
+  parameter integer ADDRESS_WIDTH=32,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      awid_in,
+    input  [ADDRESS_WIDTH-1:0] awaddr_in,
+    input  [3:0]               awlen_in,
+    input  [1:0]               awsize_in,
+    input  [1:0]               awburst_in,
+    input  [3:0]               awcache_in,
+    input  [2:0]               awprot_in,
+
+    output [ID_WIDTH-1:0]      awid,
+    output [ADDRESS_WIDTH-1:0] awaddr,
+    output [3:0]               awlen,
+    output [1:0]               awsize,
+    output [1:0]               awburst,
+    output [3:0]               awcache,
+    output [2:0]               awprot,
+    output                     awvalid,
+    input                      awready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+    wire [ID_WIDTH-1:0]      awid_out;
+    wire [ADDRESS_WIDTH-1:0] awaddr_out;
+    wire [3:0]               awlen_out;
+    wire [1:0]               awsize_out;
+    wire [1:0]               awburst_out;
+    wire [3:0]               awcache_out;
+    wire [2:0]               awprot_out;
+    wire                     awvalid_out;
+    
+    assign #(DATA_DELAY) awid=    awid_out;
+    assign #(DATA_DELAY) awaddr=  awaddr_out;
+    assign #(DATA_DELAY) awlen=   awlen_out;
+    assign #(DATA_DELAY) awsize=  awsize_out;
+    assign #(DATA_DELAY) awburst= awburst_out;
+    assign #(DATA_DELAY) awcache= awcache_out;
+    assign #(DATA_DELAY) awprot=  awprot_out;
+    assign #(VALID_DELAY) awvalid= awvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+ADDRESS_WIDTH+15),     // total number of output bits
+      .LATENCY(LATENCY),                     // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                          // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({awid_in,awaddr_in,awlen_in,awsize_in,awburst_in,awcache_in,awprot_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({awid_out,awaddr_out,awlen_out,awsize_out,awburst_out,awcache_out,awprot_out}),    // output [WIDTH-1:0] data_out,
+    .valid(awvalid_out),       // output             valid,
+    .ready(awready));      //  input              ready);
+
+endmodule
+

x393/simulation_modules/simul_axi_read.v

+/*******************************************************************************
+ * Module: simul_axi_read
+ * Date:2014-04-06  
+ * Author: Andrey Filippov
+ * Description: simulation of read data through maxi channel
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_axi_read.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_read.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_read #(
+    parameter ADDRESS_WIDTH=10
+    )(
+  input                     clk,
+  input                     reset,
+  input                     last,      // last data word in burst
+  input                     data_stb,  // data strobe (RVALID & RREADY) genearted externally
+  input  [ADDRESS_WIDTH-1:0] raddr,     // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd 
+  input              [ 3:0] rlen,      // burst length  as written by axi master, valid at rcmd
+  input                     rcmd,      // read command (address+length) strobe
+  output [ADDRESS_WIDTH-1:0] addr_out,  // output address
+  output                    burst,     // burst in progress
+  output reg                err_out);  // data last does not match predicted or FIFO over/under run
+
+  wire   [ADDRESS_WIDTH-1:0] raddr_fifo; // raddr after fifo
+  wire               [ 3:0] rlen_fifo;  // rlen after fifo
+  wire                      fifo_valid; // fifo out valid
+  reg                       burst_r=0;
+  reg                [ 3:0] left_plus_1;
+  wire                      start_burst=fifo_valid && data_stb && !burst_r;
+  wire                      generated_last= burst?(left_plus_1==1): ( fifo_valid && (rlen_fifo==0)) ;
+  wire                      fifo_in_rdy;
+  wire                      error_w= (data_stb && (last != generated_last)) || (rcmd && !fifo_in_rdy) || (start_burst && !fifo_valid);
+  reg    [ADDRESS_WIDTH-1:0] adr_out_r;
+
+  assign  burst=burst_r || start_burst;
+  assign  addr_out=start_burst?raddr_fifo:adr_out_r;
+  always @ (posedge reset or posedge clk) begin
+      if (reset)                 burst_r <= 0;
+      else if (start_burst)      burst_r <= rlen_fifo!=0;
+//      else if (last && data_stb) burst_r <= 0;
+      else if (generated_last && data_stb) burst_r <= 0;
+      if (reset)                 left_plus_1 <= 0;
+      else if (start_burst)      left_plus_1 <= rlen_fifo;
+      else if (data_stb)         left_plus_1 <= left_plus_1-1;
+      if (reset)                 err_out <= 0;
+      else                       err_out <= error_w;
+//      if (reset)                 was_last <= 0;
+//      else if (data_stb)         was_last <= last;
+
+  end
+  always @ (posedge clk) begin
+      if   (start_burst) adr_out_r <= raddr_fifo+1; // simulating only address incremental mode
+      else if (data_stb) adr_out_r <= adr_out_r + 1;
+  
+  end
+simul_fifo
+#(
+  .WIDTH(ADDRESS_WIDTH+4),
+  .DEPTH(64)
+)simmul_fifo_i(
+     .clk(clk),
+     .reset(reset),
+//     .data_in({rlen[3:0],raddr[11:2]}), // did not detect raddr[11:2] for  input  [ 9:0] raddr 
+     .data_in({rlen[3:0],raddr}),
+     .load(rcmd),
+     .input_ready(fifo_in_rdy),
+     .data_out({rlen_fifo, raddr_fifo}),
+     .valid(fifo_valid),
+     .ready(start_burst));
+endmodule
+

x393/simulation_modules/simul_axi_slow_ready.v

+/*******************************************************************************
+ * Module: simul_axi_slow_ready
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI: slow ready generation
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_slow_ready.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_slow_ready.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_slow_ready(
+    input         clk,
+    input         reset,
+    input  [3:0]  delay,
+    input         valid,
+    output        ready
+    );
+    reg   [14:0]  rdy_reg;
+    assign ready=(delay==0)?1'b1: ((((rdy_reg[14:0] >> (delay-1)) & 1) != 0)?1'b1:1'b0);
+    always @ (posedge clk or posedge reset) begin
+        if (reset)                rdy_reg <=0;
+        else if (!valid || ready) rdy_reg <=0;
+        else rdy_reg <={rdy_reg[13:0],valid};
+    end
+    
+
+endmodule
+

x393/simulation_modules/simul_fifo.v

+/*******************************************************************************
+ * Module: simul_fifo
+ * Date:2014-04-06  
+ * Author: Andrey Filippov     
+ * Description: simple fifo for simulation
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_fifo.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_fifo.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module simul_fifo
+#(
+  parameter integer WIDTH=  32,         // total number of output bits
+  parameter integer DEPTH=  64,         // maximal number of words in FIFO
+//  parameter OUT_DELAY = 3.5,
+  parameter integer FIFO_DEPTH=DEPTH+1
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+  input              clk,
+  input              reset,
+  input  [WIDTH-1:0] data_in,
+  input              load,
+  output             input_ready,
+  output [WIDTH-1:0] data_out,
+  output             valid,
+  input              ready);
+  
+  reg  [WIDTH-1:0]   fifo [0:FIFO_DEPTH-1];
+  integer            in_address;
+  integer            out_address;
+  integer            count;
+  
+  assign data_out=    fifo[out_address];
+  assign valid=       count!=0;
+  assign input_ready= count<DEPTH;
+
+  always @ (posedge clk or posedge reset) begin
+    if    (reset)  in_address <= 0;
+    else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
+
+    if    (reset)            out_address <= 0;
+    else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
+
+    
+    if    (reset)                       count <= 0;
+    else if (!(valid && ready) && load) count <= count+1;
+    else if (valid && ready && !load)   count <= count-1;
+  end
+
+  always @ (posedge clk) begin
+    if (load) fifo[in_address] <= data_in;
+  end
+endmodule
\ No newline at end of file

x393/util_modules/axi_hp_clk.v

+/*******************************************************************************
+ * Module: axi_hp_clk
+ * Date:2015-04-27  
+ * Author: Andrey Filippov     
+ * Description: Generate global clock for axi_hp
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * axi_hp_clk.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  axi_hp_clk.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  axi_hp_clk#(
+    parameter CLKIN_PERIOD =        20, //ns >1.25, 600<Fvco<1200
+    parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
+    parameter CLKFBOUT_DIV_AXIHP =  6   // To get 150MHz for the reference clock
+    )(
+    input   rst,
+    input   clk_in,
+    output  clk_axihp,
+    output  locked_axihp
+);
+    wire  clkfb_axihp, clk_axihp_pre; 
+    BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));
+    pll_base #(
+        .CLKIN_PERIOD(CLKIN_PERIOD), // 20
+        .BANDWIDTH("OPTIMIZED"),
+        .CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
+        .CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock
+        .REF_JITTER1(0.010),
+        .STARTUP_WAIT("FALSE")
+    ) pll_base_i (
+        .clkin(clk_in), // input
+        .clkfbin(clkfb_axihp), // input
+//        .rst(rst), // input
+        .rst(rst), // input
+        .pwrdwn(1'b0), // input
+        .clkout0(clk_axihp_pre), // output
+        .clkout1(), // output
+        .clkout2(), // output
+        .clkout3(), // output
+        .clkout4(), // output
+        .clkout5(), // output
+        .clkfbout(clkfb_axihp), // output
+        .locked(locked_axihp) // output
+    );
+
+
+endmodule
+

x393/util_modules/dly01_16.v

+/*******************************************************************************
+ * Module: dly01_16
+ * Date:2014-05-30  
+ * Author: Andrey Filippov
+ * Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitive)
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * dly01_16.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  dly01_16.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  dly01_16(
+    input       clk,
+    input       rst,
+    input [3:0] dly,
+    input       din,
+    output      dout
+);
+    reg [15:0] sr=0;
+`ifdef SHREG_SEQUENTIAL_RESET
+    always @ (posedge clk) begin
+        sr <= {sr[14:0], din & ~rst}; 
+    end
+`else 
+//    always @ (posedge rst or posedge clk) begin
+    always @ (posedge clk) begin
+       if (rst) sr <=0;
+       else     sr <= {sr[14:0],din}; 
+    end
+`endif
+`ifdef SIMULATION
+    assign dout = (|sr) ? ((&sr) ? 1'b1 : sr[dly]) :  1'b0 ;
+`else
+    assign dout =sr[dly];
+`endif        
+endmodule
+

x393/util_modules/dly_16.v

+/*******************************************************************************
+ * Module: dly_16
+ * Date:2014-05-30  
+ * Author: Andrey Filippov
+ * Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitives)
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * dly_16.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  dly_16.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  dly_16 #(
+    parameter WIDTH=1
+    )(
+    input               clk,
+    input               rst,
+    input         [3:0] dly,
+    input   [WIDTH-1:0] din,
+    output  [WIDTH-1:0] dout
+);
+  generate
+    genvar i;
+    for (i=0; i < WIDTH; i=i+1) begin: bit_block
+        dly01_16 dly01_16_i (
+            .clk(clk), // input
+            .rst(rst), // input
+            .dly(dly), // input[3:0] 
+            .din(din[i]), // input
+            .dout(dout[i]) // output reg 
+        );
+    end
+  endgenerate
+endmodule
+

x393/util_modules/fifo_cross_clocks.v

+/*******************************************************************************
+ * Module: fifo_cross_clocks
+ * Date:2014-05-20  
+ * Author: Andrey Filippov
+ * Description: Configurable FIFO with separate read and write clocks
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * fifo_cross_clocks.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_cross_clocks.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module fifo_cross_clocks
+#(
+  parameter integer DATA_WIDTH=16,
+  parameter integer DATA_DEPTH=4 // >=3
+) (
+    input                   rst,      // async reset, active high (global)
+    input                   rrst,     // @ posedge rclk - sync reset
+    input                   wrst,     // @ posedge wclk - sync reset
+    input                   rclk,     // read clock - positive edge
+    input                   wclk,     // write clock - positive edge
+    input                   we,       // write enable
+    input                   re,       // read enable
+    input  [DATA_WIDTH-1:0] data_in,  // input data
+    output [DATA_WIDTH-1:0] data_out, // output data
+    output                  nempty,   // FIFO has some data (sync to rclk)
+    output                  half_empty // FIFO half full (wclk) -(not more than 5/8 full)
+  );
+    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+    reg  [DATA_WIDTH-1:0]   ram [0:DATA_2DEPTH];
+    reg  [DATA_DEPTH-1:0] raddr;
+    reg  [DATA_DEPTH-1:0] waddr;
+    reg  [DATA_DEPTH-1:0] waddr_gray; //SuppressThisWarning ISExst VivadoSynthesis : MSB(waddr_gray) == MSB(waddr)
+    reg  [DATA_DEPTH-1:0] waddr_gray_rclk;
+    wire [DATA_DEPTH-1:0] waddr_plus1 = waddr +1;   
+    wire [DATA_DEPTH-1:0] waddr_plus1_gray = waddr_plus1 ^ {1'b0,waddr_plus1[DATA_DEPTH-1:1]};
+       
+    wire [DATA_DEPTH-1:0] raddr_gray = raddr ^ {1'b0,raddr[DATA_DEPTH-1:1]};
+    wire [DATA_DEPTH-1:0] raddr_plus1 = raddr +1;   
+    wire [2:0] raddr_plus1_gray_top3 = raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-3] ^ {1'b0,raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-2]};
+    reg  [2:0] raddr_gray_top3; //SuppressThisWarning ISExst VivadoSynthesis : MSB(raddr_gray_top3) == MSB(raddr)
+    reg  [2:0] raddr_gray_top3_wclk;
+       wire [2:0] raddr_top3_wclk = {
+        raddr_gray_top3_wclk[2],
+        raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1],
+        raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1]^raddr_gray_top3_wclk[0]};
+   wire [2:0] waddr_top3=waddr[DATA_DEPTH-1:DATA_DEPTH-3];
+   wire [2:0] addr_diff=waddr_top3[2:0]-raddr_top3_wclk[2:0];
+    // half-empty does not need to be precise, it uses 3 MSBs of the write address
+    // converting to Gray code (easy) and then back (can not be done parallel easily).
+    // Comparing to 1/8'th of the depth with one-bit Gray code error results in uncertainty
+    // of +/-1/8, so half_empty means "no more than 5/8 full"
+    assign half_empty=~addr_diff[2];
+    // False positive in nempty can only happen if
+    // a) it is transitioning from empty to non-empty due to we pulse
+    // b) it is transitioning to overrun - too bad already
+    // false negative - OK, just wait for the next rclk 
+//    assign nempty=waddr_gray_rclk != raddr_gray;
+//    assign nempty=waddr_gray_rclk[3:0] != raddr_gray[3:0];
+    assign nempty= (waddr_gray_rclk[3:0] ^ raddr_gray[3:0]) != 4'b0;
+    assign data_out=ram[raddr];
+    always @ (posedge  wclk or posedge rst) begin
+        if (rst)       waddr <= 0;
+        else if (wrst) waddr <= 0;
+        else if (we)   waddr <= waddr_plus1;
+        
+        if (rst)       waddr_gray <= 0;
+        else if (wrst) waddr_gray <= 0;
+        else if (we)   waddr_gray [3:0] <= waddr_plus1_gray[3:0];
+        
+    end
+    
+    always @ (posedge  rclk or posedge rst) begin
+// making rrst set FIFO to empty regardless of current  waddr (write should be stopped)        
+        if (rst)       raddr <= waddr; // 0;
+        else if (rrst) raddr <= waddr; // 0;
+        else if (re)   raddr <= raddr_plus1;
+
+        if (rst)       raddr_gray_top3 <= waddr[DATA_DEPTH-1 -: 3] ^ {1'b0,waddr[DATA_DEPTH-1 -: 2]}; // 0;
+        else if (rrst) raddr_gray_top3 <= waddr[DATA_DEPTH-1 -: 3] ^ {1'b0,waddr[DATA_DEPTH-1 -: 2]}; // 0;
+        else if (re)   raddr_gray_top3 <= raddr_plus1_gray_top3;
+    end
+    
+    always @ (posedge  rclk) begin
+        waddr_gray_rclk[3:0] <= waddr_gray[3:0];
+        
+    end
+
+    always @ (posedge  wclk) begin
+          raddr_gray_top3_wclk[2:0] <= raddr_gray_top3[2:0];
+          if (we) ram[waddr] <= data_in;
+    end
+    
+endmodule
+

x393/util_modules/fifo_same_clock.v

+/*******************************************************************************
+ * Module: fifo_same_clock
+ * Date:2014-05-20  
+ * Author: Andrey Filippov
+ * Description: Configurable synchronous FIFO using the same clock for read and write
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * fifo_same_clock.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_same_clock.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+`include "system_defines.vh" 
+//`define DEBUG_FIFO 1 
+module fifo_same_clock
+#(
+  parameter integer DATA_WIDTH=16,
+  parameter integer DATA_DEPTH=4
+)
+    (
+  input                   rst,      // reset, active high
+  input                   clk,      // clock - positive edge
+  input                   sync_rst, // synchronously reset fifo;
+  input                   we,       // write enable
+  input                   re,       // read enable
+  input  [DATA_WIDTH-1:0] data_in,  // input data
+  output [DATA_WIDTH-1:0] data_out, // output data
+  output                  nempty,   // FIFO has some data
+  output reg              half_full // FIFO half full
+`ifdef DEBUG_FIFO
+    ,output reg                 under,    // debug outputs - under - attempt to read from empty
+    output reg                  over,      // overwritten
+    output reg [DATA_DEPTH-1:0] wcount,
+    output reg [DATA_DEPTH-1:0] rcount,
+    output     [DATA_DEPTH-1:0] num_in_fifo
+    
+`endif
+  );
+    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
+//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
+//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
+// Do not understand - why?
+    reg  [DATA_DEPTH-1:0] fill=0; // RAM fill
+    reg  [DATA_WIDTH-1:0] inreg;
+    reg  [DATA_WIDTH-1:0] outreg;
+    reg  [DATA_DEPTH-1:0] ra;
+    reg  [DATA_DEPTH-1:0] wa;
+//    wire [DATA_DEPTH-1:0] next_fill;
+    reg  wem;
+    wire rem;
+    reg  out_full=0; //output register full
+    reg  [DATA_WIDTH-1:0]   ram [0:DATA_2DEPTH];
+    
+    reg  ram_nempty;
+    
+//    assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
+    assign rem= ram_nempty && (re || !out_full); 
+    assign data_out=outreg;
+    assign nempty=out_full;
+    
+`ifdef DEBUG_FIFO
+    assign num_in_fifo=fill[DATA_DEPTH-1:0];
+`endif
+    
+    always @ (posedge  clk or posedge  rst) begin
+      if      (rst)          fill <= 0;
+      else if (sync_rst)     fill <= 0;
+//      else               fill <= next_fill;
+      else if ( wem && ~rem) fill <= fill + 1;
+      else if (~wem &&  rem) fill <= fill - 1;
+      
+      if (rst)           wem <= 0;
+      else if (sync_rst) wem <= 0;
+      else               wem <= we;
+      
+      if   (rst)         ram_nempty <= 0;
+      else if (sync_rst) ram_nempty <= 0;
+//      else               ram_nempty <= (next_fill != 0);
+//      else               ram_nempty <= wem || (|fill[DATA_DEPTH-1:1]) || (fill[0] && !rem);
+      else               ram_nempty <= (|fill[DATA_DEPTH-1:1]) || (fill[0] && wem) || ((fill[0] || wem) && !rem) ;
+     
+      if (rst)           wa <= 0;
+      else if (sync_rst) wa <= 0;
+      else if (wem)      wa <= wa+1;
+      
+      if (rst)              ra <=  0;
+      else if (sync_rst)    ra <= 0;
+      else if (rem)         ra <= ra+1;
+      else if (!ram_nempty) ra <= wa; // Just recover from bit errors
+
+      if (rst)             out_full <= 0;
+      else if (sync_rst)   out_full <= 0;
+      else if (rem && ~re) out_full <= 1;
+      else if (re && ~rem) out_full <= 0;
+
+`ifdef DEBUG_FIFO
+      if (rst)            wcount <= 0;
+      else if (sync_rst)  wcount <= 0;
+      else if (we)        wcount <= wcount + 1;
+
+      if (rst)           rcount <= 0;
+      else if (sync_rst) rcount <= 0;
+      else if (re)       rcount <= rcount + 1;
+`endif      
+    end
+
+// no reset elements
+    always @ (posedge  clk) begin
+      half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
+      if (wem) ram[wa] <= inreg;
+      if (we)  inreg  <= data_in;
+      if (rem) outreg <= ram[ra];
+`ifdef DEBUG_FIFO
+      under <= ~we & re & ~nempty; // underrun error
+      over <=  we & ~re & (fill == (1<< (DATA_DEPTH-1)));    // overrun error
+`endif      
+    end
+endmodule

x393/util_modules/fifo_same_clock_fill.v

+/*******************************************************************************
+ * Module: fifo_same_clock_fill
+ * Date:2014-05-20  
+ * Author: Andrey Filippov
+ * Description: Configurable synchronous FIFO using the same clock for read and write.
+ * Provides fill level - number of words currently in FIFO
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * fifo_same_clock_fill.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_same_clock_fill.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+`include "system_defines.vh" 
+module fifo_same_clock_fill
+#(
+  parameter integer DATA_WIDTH=16,
+  parameter integer DATA_DEPTH=4
+)
+    (
+  input                   rst,      // reset, active high
+  input                   clk,      // clock - positive edge
+  input                   sync_rst, // synchronously reset fifo;
+  input                   we,       // write enable
+  input                   re,       // read enable
+  input  [DATA_WIDTH-1:0] data_in,  // input data
+  output [DATA_WIDTH-1:0] data_out, // output data
+  output                  nempty,   // FIFO has some data
+  output reg              half_full, // FIFO half full
+  output reg                 under,    // debug outputs - under - attempt to read from empty
+  output reg                  over,      // overwritten
+  output reg [DATA_DEPTH-1:0] wcount,
+  output reg [DATA_DEPTH-1:0] rcount,
+  output     [DATA_DEPTH:  0] num_in_fifo
+);
+    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
+//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
+//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
+// Do not understand - why?
+    reg  [DATA_DEPTH:  0] fill=0; // RAM fill
+    reg  [DATA_DEPTH:  0] fifo_fill=0; // FIFO (RAM+reg) fill
+    reg  [DATA_WIDTH-1:0] inreg;
+    reg  [DATA_WIDTH-1:0] outreg;
+    reg  [DATA_DEPTH-1:0] ra;
+    reg  [DATA_DEPTH-1:0] wa;
+    wire [DATA_DEPTH:0] next_fill;
+    reg  wem;
+    wire rem;
+    reg  out_full=0; //output register full
+    reg  [DATA_WIDTH-1:0]   ram [0:DATA_2DEPTH];
+    
+    reg  ram_nempty;
+    
+    assign next_fill = fill[DATA_DEPTH:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
+    assign rem= ram_nempty && (re || !out_full); 
+    assign data_out=outreg;
+    assign nempty=out_full;
+//    assign num_in_fifo=fill[DATA_DEPTH:0];
+    assign num_in_fifo=fifo_fill[DATA_DEPTH:0];
+    always @ (posedge  clk or posedge  rst) begin
+      if      (rst)      fill <= 0;
+      else if (sync_rst) fill <= 0;
+      else               fill <= next_fill;
+      
+      if      (rst)        fifo_fill <= 0;
+      else if (sync_rst)   fifo_fill <= 0;
+      else if ( we && !re) fifo_fill <= fifo_fill+1;
+      else if (!we &&  re) fifo_fill <= fifo_fill-1;
+
+      if (rst)           wem <= 0;
+      else if (sync_rst) wem <= 0;
+      else               wem <= we;
+      
+      if   (rst)         ram_nempty <= 0;
+      else if (sync_rst) ram_nempty <= 0;
+      else               ram_nempty <= (next_fill != 0);
+     
+      if (rst)           wa <= 0;
+      else if (sync_rst) wa <= 0;
+      else if (wem)      wa <= wa+1;
+      
+      if (rst)              ra <=  0;
+      else if (sync_rst)    ra <= 0;
+      else if (rem)         ra <= ra+1;
+      else if (!ram_nempty) ra <= wa; // Just recover from bit errors
+
+      if (rst)             out_full <= 0;
+      else if (sync_rst)   out_full <= 0;
+      else if (rem && ~re) out_full <= 1;
+      else if (re && ~rem) out_full <= 0;
+      if (rst)            wcount <= 0;
+      else if (sync_rst)  wcount <= 0;
+      else if (we)        wcount <= wcount + 1;
+
+      if (rst)           rcount <= 0;
+      else if (sync_rst) rcount <= 0;
+      else if (re)       rcount <= rcount + 1;
+    end
+
+// no reset elements
+    always @ (posedge  clk) begin
+      half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
+      if (wem) ram[wa] <= inreg;
+      if (we)  inreg  <= data_in;
+      if (rem) outreg <= ram[ra];
+//      under <= ~we & re & ~nempty; // underrun error
+//      over <=  we & ~re & (fill == (1<< (DATA_DEPTH-1)));    // overrun error
+      under <= re & ~nempty; // underrun error
+      over <=  wem & ~rem & fill[DATA_DEPTH] & ~fill[DATA_DEPTH-1];    // overrun error
+    end
+endmodule

x393/util_modules/fifo_sameclock_control.v

+/*******************************************************************************
+ * Module: fifo_sameclock_control
+ * Date:2016-01-20  
+ * Author: andrey     
+ * Description: BRAM-based fifo control, uses BARM output registers
+ *
+ * Copyright (c) 2016 Elphel, Inc .
+ * fifo_sameclock_control.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_sameclock_control.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  fifo_sameclock_control#(
+    parameter WIDTH = 9
+)(
+    input                  clk,
+    input                  rst,  // clock-sync reset
+    input                  wr,  // write to FIFO (also applied directly to memory)
+    input                  rd,  // read from FIFO, internally masked by nempty
+    output                 nempty,    // at read side 
+    output       [WIDTH:0] fill_in,   // valid at write side, latency 1 for read 
+    output reg [WIDTH-1:0] mem_wa,
+    output reg [WIDTH-1:0] mem_ra,
+    output                 mem_re,
+    output                 mem_regen,
+    output reg             over,
+    output reg             under
+    
+);
+    reg       [WIDTH:0] fill_ram;
+    
+    reg                 ramo_full;
+    reg                 rreg_full;
+    
+    assign mem_re = (|fill_ram) && (!ramo_full || !rreg_full || rd);
+    assign mem_regen =   ramo_full && (!rreg_full || rd);
+    assign nempty =    rreg_full;
+    assign fill_in =   fill_ram;
+    
+    always @ (posedge clk) begin
+        if     (rst) mem_wa <= 0;
+        else if (wr) mem_wa <= mem_wa + 1;
+
+        if      (rst)    mem_ra <= 0;
+        else if (mem_re) mem_ra <= mem_ra + 1;
+
+        if      (rst)                fill_ram <= 0;
+        else if (wr ^ mem_re)        fill_ram <= mem_re ? (fill_ram - 1) : (fill_ram + 1);
+
+        if      (rst)                ramo_full <= 0;
+        else if (mem_re ^ mem_regen) ramo_full <= mem_re;
+
+        if      (rst)                           rreg_full <= 0;
+        else if (mem_regen ^ (rd && rreg_full)) rreg_full <= mem_regen;
+        
+        if (rst)                     under <= 0;
+        else                         under <= rd && ! rreg_full;
+        
+        if (rst)                     over <= 0;
+        else                         over <= wr && fill_ram[WIDTH] && !fill_ram[WIDTH-1];
+        
+    end
+
+endmodule
+

x393/util_modules/pulse_cross_clock.v

+/*******************************************************************************
+ * Module: pulse_cross_clock
+ * Date:2015-04-27  
+ * Author: Andrey Filippov     
+ * Description: Propagate a single pulse through clock domain boundary
+ * For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
+ * and 1:5 for EXTRA_DLY=1 
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * pulse_cross_clock.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  pulse_cross_clock.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  pulse_cross_clock#(
+    parameter EXTRA_DLY=0 // for 
+)(
+    input  rst,
+    input  src_clk,
+    input  dst_clk,
+    input  in_pulse, // single-cycle positive pulse
+    output out_pulse,
+    output busy
+);
+    localparam EXTRA_DLY_SAFE=EXTRA_DLY ? 1 : 0;
+`ifndef IGNORE_ATTR
+    (* KEEP = "TRUE" *)
+`endif    
+    reg       in_reg = 0; // can not be  ASYNC_REG as it can not be put together with out_reg
+//WARNING: [Constraints 18-1079] Register sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/in_reg_reg
+// and sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/out_reg_reg[0] are
+//from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints
+// or mismatched control signals on the registers.
+    
+`ifndef IGNORE_ATTR
+    (* ASYNC_REG = "TRUE" *)
+`endif    
+    reg [2:0] out_reg = 0;
+`ifndef IGNORE_ATTR
+    (* ASYNC_REG = "TRUE" *)
+`endif    
+    reg       busy_r = 0;
+    assign out_pulse=out_reg[2];
+    assign busy=busy_r; // in_reg;
+    always @(posedge src_clk or posedge rst) begin
+        if   (rst) in_reg <= 0;
+        else       in_reg <= in_pulse || (in_reg && !out_reg[EXTRA_DLY_SAFE]);
+        if   (rst) busy_r <= 0;
+        else       busy_r <= in_pulse || in_reg || (busy_r && (|out_reg[EXTRA_DLY_SAFE:0]));
+    end
+//    always @(posedge dst_clk or posedge rst) begin
+    always @(posedge dst_clk) begin
+        out_reg <= {out_reg[0] & ~out_reg[1],out_reg[0],in_reg};
+    end
+endmodule
+

x393/util_modules/resync_data.v

+/*******************************************************************************
+ * Module: resync_data
+ * Date:2015-12-22  
+ * Author: Andrey Filippov
+ * Description: Resynchronize data between clock domains. No over/underruns
+ * are checker, start with half FIFO full. Async reset sets
+ * specifies output values regardless of the clocks 
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * resync_data.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  resync_data.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module resync_data
+#(
+  parameter integer DATA_WIDTH=16,
+  parameter integer DATA_DEPTH=4, // >= 2
+  parameter         INITIAL_VALUE = 0
+  
+) (
+    input                       arst,     // async reset, active high (global)
+    input                       srst,     // same as arst, but relies on the clocks 
+    input                       wclk,     // write clock - positive edge
+    input                       rclk,     // read clock - positive edge
+    input                       we,       // write enable
+    input                       re,       // read enable
+    input      [DATA_WIDTH-1:0] data_in,  // input data
+    output reg [DATA_WIDTH-1:0] data_out, // output data
+    output reg                  valid     // data valid @ rclk
+  );
+    localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
+    reg  [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
+    reg  [DATA_DEPTH-1:0] raddr;
+    reg  [DATA_DEPTH-1:0] waddr;
+    
+    reg             [1:0] rrst = 3;
+
+    always @ (posedge  rclk or posedge arst) begin
+        if      (arst)                         valid <= 0;
+        else if (srst)                         valid <= 0;
+        else if (&waddr[DATA_DEPTH-2:0] && we) valid <= 1; // just once set and stays until reset
+    end
+    
+    
+    always @ (posedge  wclk or posedge arst) begin
+        if      (arst) waddr <= 0;
+        else if (srst) waddr <= 0;
+        else if (we)   waddr <= waddr + 1;
+    end
+    
+    always @ (posedge  rclk or posedge arst) begin
+        if      (arst) rrst <= 3;
+        else if (srst) rrst <= 3; // resync to rclk
+        else           rrst <= rrst << 1;
+    
+        if      (arst)          raddr <= 0;
+        else if (rrst[0])       raddr <= 0;
+        else if (re || rrst[1]) raddr <= raddr + 1;
+        
+        if (arst)               data_out <= INITIAL_VALUE;
+        else if (rrst[0])       data_out <= INITIAL_VALUE;
+        else if (re || rrst[1]) data_out <= ram[raddr];
+    end
+    
+    always @ (posedge  wclk) begin
+          if (we) ram[waddr] <= data_in;
+    end
+    
+endmodule
+

x393/wrap/pll_base.v

+/*******************************************************************************
+ * Module: pll_base
+ * Date:2014-05-01  
+ * Author: Andrey Filippov
+ * Description: PLLE2_BASE wrapper
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * pll_base.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  pll_base.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  pll_base#(
+    parameter CLKIN_PERIOD =          0.000,  // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
+    parameter BANDWIDTH =       "OPTIMIZED",  // "OPTIMIZED", "HIGH","LOW"
+    parameter CLKFBOUT_MULT =         1,      // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
+    parameter CLKFBOUT_PHASE =        0.000,  // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
+    parameter CLKOUT0_PHASE =         0.000,  // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
+    parameter CLKOUT1_PHASE =         0.000,  // Initial/static fine phase shift, 1/(56*Fvco) actual step 
+    parameter CLKOUT2_PHASE =         0.000,
+    parameter CLKOUT3_PHASE =         0.000,
+    parameter CLKOUT4_PHASE =         0.000,
+    parameter CLKOUT5_PHASE =         0.000,
+    parameter CLKOUT0_DUTY_CYCLE=     0.5,    // CLOCK 0 output duty factor, 3 significant digits      
+    parameter CLKOUT1_DUTY_CYCLE=     0.5,      
+    parameter CLKOUT2_DUTY_CYCLE=     0.5,      
+    parameter CLKOUT3_DUTY_CYCLE=     0.5,      
+    parameter CLKOUT4_DUTY_CYCLE=     0.5,      
+    parameter CLKOUT5_DUTY_CYCLE=     0.5,      
+    parameter CLKOUT0_DIVIDE =        1,        // CLK0 outout divide, integer 1..128 
+    parameter CLKOUT1_DIVIDE =        1,        // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
+    parameter CLKOUT2_DIVIDE =        1,
+    parameter CLKOUT3_DIVIDE =        1,
+    parameter CLKOUT4_DIVIDE =        1,
+    parameter CLKOUT5_DIVIDE =        1,
+    parameter DIVCLK_DIVIDE =         1,            // Integer 1..106. Divides all outputs with respect to CLKIN
+    parameter REF_JITTER1   =         0.010,        // Expected jitter on CLKIN1 (0.000..0.999)
+    parameter STARTUP_WAIT  =         "FALSE"       // Delays "DONE" signal until MMCM is locked
+)
+(
+    input clkin,   // General clock input
+    input clkfbin,  // Feedback clock input
+    input rst,      // asynchronous reset input
+    input pwrdwn,   // power down input    
+    output clkout0,  // output 0, HPC BUFR/BUFIO capable
+    output clkout1,  // output 1, HPC BUFR/BUFIO capable
+    output clkout2,  // output 2, HPC BUFR/BUFIO capable
+    output clkout3,  // output 3, HPC BUFR/BUFIO capable
+    output clkout4,  // output 4, HPC BUFR/BUFIO not capable
+    output clkout5,  // output 5, HPC BUFR/BUFIO not capable
+    output clkfbout, // dedicate feedback output    
+    output locked   // PLL locked output
+);
+    PLLE2_BASE #(
+        .BANDWIDTH           (BANDWIDTH),
+        .CLKFBOUT_MULT       (CLKFBOUT_MULT),
+        .CLKFBOUT_PHASE      (CLKFBOUT_PHASE),
+        .CLKIN1_PERIOD       (CLKIN_PERIOD),
+        .CLKOUT0_DIVIDE      (CLKOUT0_DIVIDE),
+        .CLKOUT0_DUTY_CYCLE  (CLKOUT0_DUTY_CYCLE),
+        .CLKOUT0_PHASE       (CLKOUT0_PHASE),
+        .CLKOUT1_DIVIDE      (CLKOUT1_DIVIDE),
+        .CLKOUT1_DUTY_CYCLE  (CLKOUT1_DUTY_CYCLE),
+        .CLKOUT1_PHASE       (CLKOUT1_PHASE),
+        .CLKOUT2_DIVIDE      (CLKOUT2_DIVIDE),
+        .CLKOUT2_DUTY_CYCLE  (CLKOUT2_DUTY_CYCLE),
+        .CLKOUT2_PHASE       (CLKOUT2_PHASE),
+        .CLKOUT3_DIVIDE      (CLKOUT3_DIVIDE),
+        .CLKOUT3_DUTY_CYCLE  (CLKOUT3_DUTY_CYCLE),
+        .CLKOUT3_PHASE       (CLKOUT3_PHASE),
+        .CLKOUT4_DIVIDE      (CLKOUT4_DIVIDE),
+        .CLKOUT4_DUTY_CYCLE  (CLKOUT4_DUTY_CYCLE),
+        .CLKOUT4_PHASE       (CLKOUT4_PHASE),
+        .CLKOUT5_DIVIDE      (CLKOUT5_DIVIDE),
+        .CLKOUT5_DUTY_CYCLE  (CLKOUT5_DUTY_CYCLE),
+        .CLKOUT5_PHASE       (CLKOUT5_PHASE),
+        .DIVCLK_DIVIDE       (DIVCLK_DIVIDE),
+        .REF_JITTER1         (REF_JITTER1),
+        .STARTUP_WAIT        (STARTUP_WAIT)
+    ) PLLE2_BASE_i (
+        .CLKFBOUT            (clkfbout), // output 
+        .CLKOUT0             (clkout0), // output 
+        .CLKOUT1             (clkout1), // output 
+        .CLKOUT2             (clkout2), // output 
+        .CLKOUT3             (clkout3), // output 
+        .CLKOUT4             (clkout4), // output 
+        .CLKOUT5             (clkout5), // output 
+        .LOCKED              (locked), // output 
+        .CLKFBIN             (clkfbin), // input 
+        .CLKIN1              (clkin), // input 
+        .PWRDWN              (pwrdwn), // input 
+        .RST                 (rst) // input 
+    );
+endmodule