Added compact input primitives logging and FPGA-based profiling of the host/device communication (29d789db) · Commits · Elphel / x393_sata

.project

+17 −17

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		@@ -52,87 +52,87 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160307105701067.log</location>
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		</link>
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		</link>
		<link>
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		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160307105701067.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160308235749196.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160307105701067.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160308235749196.log</location>
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		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160308235749196.log</location>
		</link>
		<link>
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		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160307105701067.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160308235749196.log</location>
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		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160308235632422.log</location>
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		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160307105701067.log</location>
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		</link>
		</linkedResources>
		</projectDescription>

ahci/ahci_fsm.v

+8 −2

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		@@ -271,6 +271,7 @@ module ahci_fsm
		wire fsm_next;
		// reg fsm_next_r;
		reg fsm_actions; // processing actions
		reg dis_actions; // disable actions during async jump
		reg fsm_act_busy;
		reg [1:0] fsm_transitions; // processing transitions
		reg fsm_preload; // read first sequence data (2 cycles for regen)
		@@ -288,7 +289,7 @@ module ahci_fsm
		wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
		wire fsm_last_act_w = pgm_data[17];

		wire fsm_pre_act_w = fsm_actions && fsm_next; // use it as CS for generated actions (registered)
		wire fsm_pre_act_w = !dis_actions && fsm_actions && fsm_next; // use it as CS for generated actions (registered)

		reg [1:0] async_pend_r; // waiting to process cominit_got
		reg async_from_st; // change to multi-bit if there will be more sources for async transitions
		@@ -381,6 +382,11 @@ module ahci_fsm
		else if (fsm_jump[2]) fsm_actions <= 1;
		else if (fsm_last_act_w && fsm_next) fsm_actions <= 0;

		if (hba_rst) dis_actions <= 0;
		else if (\|async_pend_r) dis_actions <= 1;
		else if (fsm_jump[2]) dis_actions <= 0;


		if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;

		if (hba_rst \|\| pre_jump_w) fsm_transitions <= 0;

ahci/ahci_sata_layers.v

+26 −2

Original line number	Diff line number	Diff line
		@@ -308,8 +308,32 @@ assign debug_phy = debug_phy0;
		// .cominit_got (cominit_got), // output wire
		// .comwake_got (serr_DW), // output wire


		`ifdef DATASCOPE_INCOMING_RAW
		assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx
		`else
		// Mix transmitted alignes pair, but only to the closest group of 6 primitives
		reg dbg_was_link5; // alignes pair sent
		wire dbg_was_link5_xclk; // alignes pair sent

		always @ (posedge datascope_clk) begin
		if (dbg_was_link5_xclk) dbg_was_link5 <= 1;
		else if (datascope_we) dbg_was_link5 <= 0;
		end

		pulse_cross_clock #(
		.EXTRA_DLY(0)
		) dbg_was_link5_i (
		.rst (rst), // input
		.src_clk (clk), // input
		.dst_clk (datascope_clk), // input
		.in_pulse (debug_link[5]), // input// is actually a two-cycle
		.out_pulse (dbg_was_link5_xclk), // output
		.busy() // output
		);

		assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx

		`endif
		link #(
		.DATA_BYTE_WIDTH(4)
		) link (

ahci/ahci_top.v

+240 −279

File changed.

Preview size limit exceeded, changes collapsed.

device/sata_device.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -983,7 +983,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
		DEV_TITLE = "Transmission is paused";
		$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
		linkSendPrim("HOLD");
		xpause = xpause - 1;
		// xpause = xpause - 1;
		end else begin
		scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
		linkSendData(transmit_data[cnt] ^ scrambler_value);

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