Removed x393 as submodule, copied needed files only (to resolve future recursion)

.gitmodules

-[submodule "x393"]
-	path = x393
-	url = https://github.com/Elphel/x393.git

copy_from_x393.sh

+#!/bin/bash
+REPO_ROOT=".."
+CWD="$(pwd)"
+
+cd $REPO_ROOT
+cp -v --parents \
+x393/simulation_modules/simul_axi_master_wraddr.v \
+x393/simulation_modules/simul_axi_master_rdaddr.v \
+x393/simulation_modules/simul_axi_master_wdata.v \
+x393/simulation_modules/simul_axi_slow_ready.v \
+x393/simulation_modules/simul_axi_hp_rd.v \
+x393/simulation_modules/simul_axi_hp_wr.v \
+x393/simulation_modules/simul_axi_read.v \
+x393/util_modules/fifo_same_clock_fill.v \
+x393/util_modules/dly_16.v \
+x393/util_modules/axi_hp_clk.v \
+x393/simulation_modules/simul_fifo.v \
+x393/simulation_modules/simul_axi_fifo_out.v \
+x393/util_modules/dly01_16.v \
+x393/wrap/pll_base.v \
+x393/wrap/ram18p_var_w_var_r.v \
+x393/util_modules/fifo_sameclock_control.v \
+x393/util_modules/pulse_cross_clock.v \
+x393/axi/axibram_read.v \
+x393/wrap/ram_var_w_var_r.v \
+x393/wrap/ramt_var_wb_var_r.v \
+x393/util_modules/fifo_cross_clocks.v \
+x393/axi/axibram_write.v \
+x393/util_modules/fifo_same_clock.v \
+x393/util_modules/resync_data.v \
+x393/wrap/ramt_var_w_var_r.v \
+x393/glbl.v \
+$CWD
+cd $CWD

x393 @ 1e167c27

-Subproject commit 1e167c275aa336683875434b4ae406d803b3db3d

x393/glbl.v

+`timescale  1 ps / 1 ps
+module glbl ();
+    parameter ROC_WIDTH = 10000;// 100000;
+    parameter TOC_WIDTH = 0;
+
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire GSR;
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire GTS;
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire PRLD;
+    //SuppressWarnings VEditor - this value is used in other modules through global reference
+    wire PLL_LOCKG;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	   GSR_int = 1'b1;
+	   PRLD_int = 1'b1;
+	   #(ROC_WIDTH)
+	   GSR_int = 1'b0;
+	   PRLD_int = 1'b0;
+    end
+
+    initial begin
+	   GTS_int = 1'b1;
+	   #(TOC_WIDTH)
+	   GTS_int = 1'b0;
+    end
+endmodule

x393/simulation_modules/simul_axi_fifo_out.v

+/**************************************
+* Module: simul_axi_fifo
+* Date:2014-03-23  
+* Author: Andrey Filippov     
+*
+* Description: 
+***************************************/
+`timescale 1ns/1ps
+
+module simul_axi_fifo
+#(
+  parameter integer WIDTH=  64,         // total number of output bits
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+  parameter integer FIFO_DEPTH=LATENCY+DEPTH+1
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+  input              clk,
+  input              reset,
+  input  [WIDTH-1:0] data_in,
+  input              load,
+  output             input_ready,
+  output [WIDTH-1:0] data_out,
+  output             valid,
+  input              ready);
+  
+  reg  [WIDTH-1:0]   fifo [0:FIFO_DEPTH-1];
+  integer            in_address;
+  integer            out_address;
+  integer            in_count;
+  integer            out_count;
+  reg    [LATENCY:0] latency_delay_r;
+  
+  wire [LATENCY+1:0] latency_delay={latency_delay_r,load};             
+  wire               out_inc=latency_delay[LATENCY];
+  
+  assign data_out=    fifo[out_address];
+  assign valid=       out_count!=0;
+  assign input_ready= in_count<DEPTH;
+//  assign out_inc={
+
+  always @ (posedge clk or posedge reset) begin
+    if (reset) latency_delay_r <= 0;
+    else       latency_delay_r <= latency_delay[LATENCY:0];
+
+    if    (reset)  in_address <= 0;
+    else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
+
+    if    (reset)            out_address <= 0;
+    else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
+    
+    if    (reset)                       in_count <= 0;
+    else if (!(valid && ready) && load) in_count <= in_count+1;
+    else if (valid && ready && !load)   in_count <= in_count-1;
+
+    if    (reset)                          out_count <= 0;
+    else if (!(valid && ready) && out_inc) out_count <= out_count+1;
+    else if (valid && ready && !out_inc)   out_count <= out_count-1;
+  end
+  always @ (posedge clk) begin
+    if (load) fifo[in_address] <= data_in;
+  end
+  
+endmodule
\ No newline at end of file

x393/simulation_modules/simul_axi_master_rdaddr.v

+/*******************************************************************************
+ * Module: simul_axi_master_rdaddr
+ * Date:2014-03-23  
+ * Author: Andrey Filippov     
+ * Description: Simulation model for AXI read address channel
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_axi_master_rdaddr.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_rdaddr.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+
+`timescale 1ns/1ps
+
+module simul_axi_master_rdaddr
+#(
+  parameter integer ID_WIDTH=12,
+  parameter integer ADDRESS_WIDTH=32,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+  
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      arid_in,
+    input  [ADDRESS_WIDTH-1:0] araddr_in,
+    input  [3:0]               arlen_in,
+    input  [1:0]               arsize_in,
+    input  [1:0]               arburst_in,
+    input  [3:0]               arcache_in,
+    input  [2:0]               arprot_in,
+
+    output [ID_WIDTH-1:0]      arid,
+    output [ADDRESS_WIDTH-1:0] araddr,
+    output [3:0]               arlen,
+    output [1:0]               arsize,
+    output [1:0]               arburst,
+    output [3:0]               arcache,
+    output [2:0]               arprot,
+    output                     arvalid,
+    input                      arready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+    wire [ID_WIDTH-1:0]      arid_out;
+    wire [ADDRESS_WIDTH-1:0] araddr_out;
+    wire [3:0]               arlen_out;
+    wire [1:0]               arsize_out;
+    wire [1:0]               arburst_out;
+    wire [3:0]               arcache_out;
+    wire [2:0]               arprot_out;
+    wire                     arvalid_out;
+    
+    assign #(DATA_DELAY) arid=    arid_out;
+    assign #(DATA_DELAY) araddr=  araddr_out;
+    assign #(DATA_DELAY) arlen=   arlen_out;
+    assign #(DATA_DELAY) arsize=  arsize_out;
+    assign #(DATA_DELAY) arburst= arburst_out;
+    assign #(DATA_DELAY) arcache= arcache_out;
+    assign #(DATA_DELAY) arprot=  arprot_out;
+    assign #(VALID_DELAY) arvalid=arvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+ADDRESS_WIDTH+15),     // total number of output bits
+      .LATENCY(LATENCY),                     // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                          // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({arid_in,araddr_in,arlen_in,arsize_in,arburst_in,arcache_in,arprot_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({arid_out,araddr_out,arlen_out,arsize_out,arburst_out,arcache_out,arprot_out}),    // output [WIDTH-1:0] data_out,
+    .valid(arvalid_out),       // output             valid,
+    .ready(arready));      //  input              ready);
+
+endmodule

x393/simulation_modules/simul_axi_master_wdata.v

+/*******************************************************************************
+ * Module: simul_axi_master_wdata
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI write data channel
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_master_wdata.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_wdata.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_master_wdata#(
+  parameter integer ID_WIDTH=12,
+  parameter integer DATA_WIDTH=32,
+  parameter integer WSTB_WIDTH= 4,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      wid_in,
+    input  [DATA_WIDTH-1:0]    wdata_in,
+    input  [WSTB_WIDTH-1:0]    wstrb_in,
+    input                      wlast_in,
+    output [ID_WIDTH-1:0]      wid,
+    output [DATA_WIDTH-1:0]    wdata,
+    output [WSTB_WIDTH-1:0]    wstrb,
+    output                     wlast,
+    output                     wvalid,
+    input                      wready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+
+    wire  [ID_WIDTH-1:0]      wid_out;
+    wire  [DATA_WIDTH-1:0]    wdata_out;
+    wire  [WSTB_WIDTH-1:0]    wstrb_out;
+    wire                      wlast_out;
+    wire                      wvalid_out;
+    
+    assign #(DATA_DELAY)  wid=    wid_out;
+    assign #(DATA_DELAY)  wdata=  wdata_out;
+    assign #(DATA_DELAY)  wstrb=  wstrb_out;
+    assign #(DATA_DELAY)  wlast=  wlast_out;
+    assign #(VALID_DELAY) wvalid= wvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+DATA_WIDTH+WSTB_WIDTH+1),  // total number of output bits
+      .LATENCY(LATENCY),                         // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                              // maximal number of commands in FIFO
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({wid_in, wdata_in, wstrb_in, wlast_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({wid_out, wdata_out, wstrb_out, wlast_out}),    // output [WIDTH-1:0] data_out,
+    .valid(wvalid_out),       // output             valid,
+    .ready(wready));          //  input              ready);
+
+endmodule
+

x393/simulation_modules/simul_axi_master_wraddr.v

+/*******************************************************************************
+ * Module: simul_axi_master_wraddr
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI write address channel
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_master_wraddr.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_master_wraddr.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_master_wraddr
+#(
+  parameter integer ID_WIDTH=12,
+  parameter integer ADDRESS_WIDTH=32,
+  parameter integer LATENCY=0,          // minimal delay between inout and output ( 0 - next cycle)
+  parameter integer DEPTH=8,            // maximal number of commands in FIFO
+  parameter DATA_DELAY = 3.5,
+  parameter VALID_DELAY = 4.0
+)(
+    input                      clk,
+    input                      reset,
+    input  [ID_WIDTH-1:0]      awid_in,
+    input  [ADDRESS_WIDTH-1:0] awaddr_in,
+    input  [3:0]               awlen_in,
+    input  [1:0]               awsize_in,
+    input  [1:0]               awburst_in,
+    input  [3:0]               awcache_in,
+    input  [2:0]               awprot_in,
+
+    output [ID_WIDTH-1:0]      awid,
+    output [ADDRESS_WIDTH-1:0] awaddr,
+    output [3:0]               awlen,
+    output [1:0]               awsize,
+    output [1:0]               awburst,
+    output [3:0]               awcache,
+    output [2:0]               awprot,
+    output                     awvalid,
+    input                      awready,
+
+    input                      set_cmd,  // latch all other input data at posedge of clock
+    output                     ready     // command/data FIFO can accept command
+);
+    wire [ID_WIDTH-1:0]      awid_out;
+    wire [ADDRESS_WIDTH-1:0] awaddr_out;
+    wire [3:0]               awlen_out;
+    wire [1:0]               awsize_out;
+    wire [1:0]               awburst_out;
+    wire [3:0]               awcache_out;
+    wire [2:0]               awprot_out;
+    wire                     awvalid_out;
+    
+    assign #(DATA_DELAY) awid=    awid_out;
+    assign #(DATA_DELAY) awaddr=  awaddr_out;
+    assign #(DATA_DELAY) awlen=   awlen_out;
+    assign #(DATA_DELAY) awsize=  awsize_out;
+    assign #(DATA_DELAY) awburst= awburst_out;
+    assign #(DATA_DELAY) awcache= awcache_out;
+    assign #(DATA_DELAY) awprot=  awprot_out;
+    assign #(VALID_DELAY) awvalid= awvalid_out;
+
+simul_axi_fifo
+    #(
+      .WIDTH(ID_WIDTH+ADDRESS_WIDTH+15),     // total number of output bits
+      .LATENCY(LATENCY),                     // minimal delay between inout and output ( 0 - next cycle)
+      .DEPTH(DEPTH)                          // maximal number of commands in FIFO
+//  parameter OUT_DELAY = 3.5,
+    ) simul_axi_fifo_i (
+    .clk(clk),         // input              clk,
+    .reset(reset),       // input              reset,
+    .data_in({awid_in,awaddr_in,awlen_in,awsize_in,awburst_in,awcache_in,awprot_in}),     // input  [WIDTH-1:0] data_in,
+    .load(set_cmd),        // input              load,
+    .input_ready(ready), // output             input_ready,
+    .data_out({awid_out,awaddr_out,awlen_out,awsize_out,awburst_out,awcache_out,awprot_out}),    // output [WIDTH-1:0] data_out,
+    .valid(awvalid_out),       // output             valid,
+    .ready(awready));      //  input              ready);
+
+endmodule
+

x393/simulation_modules/simul_axi_read.v

+/*******************************************************************************
+ * Module: simul_axi_read
+ * Date:2014-04-06  
+ * Author: Andrey Filippov
+ * Description: simulation of read data through maxi channel
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_axi_read.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_read.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_read #(
+    parameter ADDRESS_WIDTH=10
+    )(
+  input                     clk,
+  input                     reset,
+  input                     last,      // last data word in burst
+  input                     data_stb,  // data strobe (RVALID & RREADY) genearted externally
+  input  [ADDRESS_WIDTH-1:0] raddr,     // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd 
+  input              [ 3:0] rlen,      // burst length  as written by axi master, valid at rcmd
+  input                     rcmd,      // read command (address+length) strobe
+  output [ADDRESS_WIDTH-1:0] addr_out,  // output address
+  output                    burst,     // burst in progress
+  output reg                err_out);  // data last does not match predicted or FIFO over/under run
+
+  wire   [ADDRESS_WIDTH-1:0] raddr_fifo; // raddr after fifo
+  wire               [ 3:0] rlen_fifo;  // rlen after fifo
+  wire                      fifo_valid; // fifo out valid
+  reg                       burst_r=0;
+  reg                [ 3:0] left_plus_1;
+  wire                      start_burst=fifo_valid && data_stb && !burst_r;
+  wire                      generated_last= burst?(left_plus_1==1): ( fifo_valid && (rlen_fifo==0)) ;
+  wire                      fifo_in_rdy;
+  wire                      error_w= (data_stb && (last != generated_last)) || (rcmd && !fifo_in_rdy) || (start_burst && !fifo_valid);
+  reg    [ADDRESS_WIDTH-1:0] adr_out_r;
+
+  assign  burst=burst_r || start_burst;
+  assign  addr_out=start_burst?raddr_fifo:adr_out_r;
+  always @ (posedge reset or posedge clk) begin
+      if (reset)                 burst_r <= 0;
+      else if (start_burst)      burst_r <= rlen_fifo!=0;
+//      else if (last && data_stb) burst_r <= 0;
+      else if (generated_last && data_stb) burst_r <= 0;
+      if (reset)                 left_plus_1 <= 0;
+      else if (start_burst)      left_plus_1 <= rlen_fifo;
+      else if (data_stb)         left_plus_1 <= left_plus_1-1;
+      if (reset)                 err_out <= 0;
+      else                       err_out <= error_w;
+//      if (reset)                 was_last <= 0;
+//      else if (data_stb)         was_last <= last;
+
+  end
+  always @ (posedge clk) begin
+      if   (start_burst) adr_out_r <= raddr_fifo+1; // simulating only address incremental mode
+      else if (data_stb) adr_out_r <= adr_out_r + 1;
+  
+  end
+simul_fifo
+#(
+  .WIDTH(ADDRESS_WIDTH+4),
+  .DEPTH(64)
+)simmul_fifo_i(
+     .clk(clk),
+     .reset(reset),
+//     .data_in({rlen[3:0],raddr[11:2]}), // did not detect raddr[11:2] for  input  [ 9:0] raddr 
+     .data_in({rlen[3:0],raddr}),
+     .load(rcmd),
+     .input_ready(fifo_in_rdy),
+     .data_out({rlen_fifo, raddr_fifo}),
+     .valid(fifo_valid),
+     .ready(start_burst));
+endmodule
+

x393/simulation_modules/simul_axi_slow_ready.v

+/*******************************************************************************
+ * Module: simul_axi_slow_ready
+ * Date:2014-03-24  
+ * Author: Andrey Filippov    
+ * Description: Simulation model for AXI: slow ready generation
+ *
+ * Copyright (c) 2014 Elphel, Inc..
+ * simul_axi_slow_ready.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_axi_slow_ready.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  simul_axi_slow_ready(
+    input         clk,
+    input         reset,
+    input  [3:0]  delay,
+    input         valid,
+    output        ready
+    );
+    reg   [14:0]  rdy_reg;
+    assign ready=(delay==0)?1'b1: ((((rdy_reg[14:0] >> (delay-1)) & 1) != 0)?1'b1:1'b0);
+    always @ (posedge clk or posedge reset) begin
+        if (reset)                rdy_reg <=0;
+        else if (!valid || ready) rdy_reg <=0;
+        else rdy_reg <={rdy_reg[13:0],valid};
+    end
+    
+
+endmodule
+

x393/simulation_modules/simul_fifo.v

+/*******************************************************************************
+ * Module: simul_fifo
+ * Date:2014-04-06  
+ * Author: Andrey Filippov     
+ * Description: simple fifo for simulation
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * simul_fifo.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  simul_fifo.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module simul_fifo
+#(
+  parameter integer WIDTH=  32,         // total number of output bits
+  parameter integer DEPTH=  64,         // maximal number of words in FIFO
+//  parameter OUT_DELAY = 3.5,
+  parameter integer FIFO_DEPTH=DEPTH+1
+//  parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1
+)(
+  input              clk,
+  input              reset,
+  input  [WIDTH-1:0] data_in,
+  input              load,
+  output             input_ready,
+  output [WIDTH-1:0] data_out,
+  output             valid,
+  input              ready);
+  
+  reg  [WIDTH-1:0]   fifo [0:FIFO_DEPTH-1];
+  integer            in_address;
+  integer            out_address;
+  integer            count;
+  
+  assign data_out=    fifo[out_address];
+  assign valid=       count!=0;
+  assign input_ready= count<DEPTH;
+
+  always @ (posedge clk or posedge reset) begin
+    if    (reset)  in_address <= 0;
+    else if (load) in_address <= (in_address==(FIFO_DEPTH-1))?0:in_address+1;
+
+    if    (reset)            out_address <= 0;
+    else if (valid && ready) out_address <= (out_address==(FIFO_DEPTH-1))?0:out_address+1;
+
+    
+    if    (reset)                       count <= 0;
+    else if (!(valid && ready) && load) count <= count+1;
+    else if (valid && ready && !load)   count <= count-1;
+  end
+
+  always @ (posedge clk) begin
+    if (load) fifo[in_address] <= data_in;
+  end
+endmodule
\ No newline at end of file

x393/util_modules/axi_hp_clk.v

+/*******************************************************************************
+ * Module: axi_hp_clk
+ * Date:2015-04-27  
+ * Author: Andrey Filippov     
+ * Description: Generate global clock for axi_hp
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * axi_hp_clk.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  axi_hp_clk.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it