Commit 727bf4bc authored by Andrey Filippov's avatar Andrey Filippov
Browse files

merged with errhandl

parents e155806b c1fba53a

.pydevproject→.eclipse_project_setup/.pydevproject

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.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs

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FPGA_project_@_ImplementationTopFile=top.v

FPGA_project_@_ImplementationTopModule=top

FPGA_project_@_SimulationTopFile=tb/tb_top.v

FPGA_project_@_SimulationTopModule=tb

FPGA_project_@_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->

com.elphel.store.version.FPGA_project=1.0

eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs

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ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->

ISExst_@_constraints=ddrc_test01.xcf

com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->

eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs

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VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_force=true

com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->

eclipse.preferences.version=1

.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs

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VivadoPlace_@_verbose_place=true

com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->

eclipse.preferences.version=1