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x393_sata
Commit 727bf4bc authored by Andrey Filippov's avatar Andrey Filippov
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merged with errhandl

parents e155806b c1fba53a
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Showing with 696 additions and 513 deletions
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644
View file @ 727bf4bc
FPGA_project_@_ImplementationTopFile=top.v
FPGA_project_@_ImplementationTopModule=top
FPGA_project_@_SimulationTopFile=tb/tb_top.v
FPGA_project_@_SimulationTopModule=tb
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644
View file @ 727bf4bc
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644
View file @ 727bf4bc
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644
View file @ 727bf4bc
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoSynthesis.prefs 0 → 100644
View file @ 727bf4bc
VivadoSynthesis_@_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false
VivadoSynthesis_@_flatten_hierarchy=none
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_flatten_hierarchy<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs 0 → 100644
View file @ 727bf4bc
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs 0 → 100644
View file @ 727bf4bc
com.elphel.store.context.VivadoTimingReportImplemented=
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs 0 → 100644
View file @ 727bf4bc
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs 0 → 100644
View file @ 727bf4bc
com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_@_SaveLogsPreprocessor=true
iverilog_@_SaveLogsSimulator=true
iverilog_@_TopModulesOther=glbl<-@\#\#@->
.eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644
View file @ 727bf4bc
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
.eclipse_project_setup/README_eclipse_project_setup 0 → 100644
View file @ 727bf4bc
Directory .eclipse_project_setup contains "master"/initial settings for tyhis project in Eclipse IDE. Copy the contents to the project root after cloning the project (it may be done automatically if cloned by a script) or if you current settings get corrupted.
.gitignore
View file @ 727bf4bc
.cproject
.project
.externalToolBuilders/
.pydevproject
unisims
debug
vivado_*
......@@ -14,4 +17,5 @@ x393.prj
*.pickle
bitbake-logs
sysroots
attic/*
\ No newline at end of file
attic/*
image
.project deleted 100644 → 0
View file @ e155806b
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>x393_sata</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.python.pydev.PyDevBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
<value>echo &apos;Clean&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
<value>0</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
<value>echo &apos;No Build Configuration Specified&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
<value>true</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
<value>Default</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
<value></value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
<value></value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160313145052718.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313145052718.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160313145052718.log</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160313145052718.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 727bf4bc
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=top.v
FPGA_project_3_ImplementationTopModule=top
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
FPGA_project_@_ImplementationTopFile=top.v
FPGA_project_@_ImplementationTopModule=top
FPGA_project_@_SimulationTopFile=tb/tb_top.v
FPGA_project_@_SimulationTopModule=tb
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.settings/com.elphel.vdt.ISExst.prefs
View file @ 727bf4bc
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 727bf4bc
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ 727bf4bc
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 727bf4bc
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
VivadoSynthesis_@_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false
VivadoSynthesis_@_flatten_hierarchy=none
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_flatten_hierarchy<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ 727bf4bc
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ 727bf4bc
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
com.elphel.store.context.VivadoTimingReportImplemented=
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ 727bf4bc
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ 727bf4bc
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_95_IcarusTopFile<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IVerilogOther<-@\#\#@->iverilog_@_Param_Exe<-@\#\#@->iverilog_@_VVP_Exe<-@\#\#@->iverilog_@_GtkWave_Exe<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_105_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_110_ShowNoProblem=true
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_ahci_01.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_95_IcarusTopFile=tb/tb_ahci.tf
iverilog_99_GrepFindErrWarn=error|warning|sorry
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_@_Param_Exe=/usr/local/bin/iverilog
iverilog_@_SaveLogsPreprocessor=true
iverilog_@_SaveLogsSimulator=true
iverilog_@_ShowNoProblem=true
iverilog_@_TopModulesOther=glbl<-@\#\#@->
iverilog_@_VVP_Exe=/usr/local/bin/vvp
ahci/ahci_ctrl_stat.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_ctrl_stat
* Date:2016-01-12
* Author: andrey
* Description: Copy of significant register fields, updating them in
/*!
* <b>Module:</b>ahci_ctrl_stat
* @file ahci_ctrl_stat.v
* @date 2016-01-12
* @author Andrey Filippov
*
* @brief Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible)
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_ctrl_stat.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -18,7 +23,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_ctrl_stat #(
......@@ -493,7 +498,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0];
end
// HBA_PORT__PxCMD register - different behaviors of differtnt fields
// HBA_PORT__PxCMD register - different behaviors of different fields
// use PxCMD_MASK to prevent generation of unneeded register bits
always @(posedge mclk) begin
......
ahci/ahci_dma.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma
* Date:2016-01-01
* Author: Andrey Filippov
* Description: DMA R/W over 64-AXI channel for AHCI implementation
/*!
* <b>Module:</b>ahci_dma
* @file ahci_dma.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief DMA R/W over 64-AXI channel for AHCI implementation
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma (
......
ahci/ahci_dma_rd_fifo.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma_rd_fifo
* Date:2016-01-01
* Author: Andrey Filippov
* Description: cross clocks, word-realign, 64->32
/*!
* <b>Module:</b>ahci_dma_rd_fifo
* @file ahci_dma_rd_fifo.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 64->32
* Convertion from x64 QWORD-aligned AXI data @hclk to
* 32-bit word-aligned data at mclk
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_rd_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_rd_fifo#(
......
ahci/ahci_dma_rd_stuff.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma_rd_stuff
* Date:2016-01-01
* Author: andrey
* Description: Stuff DWORD data with missing words into continuous 32-bit data
/*!
* <b>Module:</b>ahci_dma_rd_stuff
* @file ahci_dma_rd_stuff.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief Stuff DWORD data with missing words into continuous 32-bit data
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma_rd_stuff.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_rd_stuff(
......
ahci/ahci_dma_wr_fifo.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma_wr_fifo
* Date:2016-01-02
* Author: Andrey Filippov
* Description: cross clocks, word-realign, 32 -> 64 with byte write mask
/*!
* <b>Module:</b>ahci_dma_wr_fifo
* @file ahci_dma_wr_fifo.v
* @date 2016-01-02
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 32 -> 64 with byte write mask
* Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned
* AXI data @hclk
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_wr_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_wr_fifo#(
......
ahci/ahci_fis_receive.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_fis_receive
* Date:2016-01-06
* Author: Andrey Filippov
* Description: Receives incoming FIS-es, forwards DMA ones to DMA engine
/*!
* <b>Module:</b>ahci_fis_receive
* @file ahci_fis_receive.v
* @date 2016-01-06
* @author Andrey Filippov
*
* @brief Receives incoming FIS-es, forwards DMA ones to DMA engine
* Stores received FIS-es if requested
*
* 'fis_first_vld' is asserted when the FIFO output contains first DWORD
......@@ -13,7 +15,10 @@
* one of the 3 states (fis_ok, fis_err and fis_ferr) are raised
* This module also receives/updates device signature and PxTFD ERR and STS.
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_fis_receive.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -26,7 +31,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fis_receive#(
......
ahci/ahci_fis_transmit.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_fis_transmit
* Date:2016-01-07
* Author: andrey
* Description: Fetches commands, command tables, creates/sends FIS
/*!
* <b>Module:</b>ahci_fis_transmit
* @file ahci_fis_transmit.v
* @date 2016-01-07
* @author Andrey Filippov
*
* @brief Fetches commands, command tables, creates/sends FIS
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fis_transmit.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fis_transmit #(
......
ahci/ahci_fsm.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_fsm
* Date:2016-01-10
* Author: andrey
* Description: AHCI host+port0 state machine
/*!
* <b>Module:</b>ahci_fsm
* @file ahci_fsm.v
* @date 2016-01-10
* @author Andrey Filippov
*
* @brief AHCI host+port0 state machine
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fsm.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fsm
......@@ -389,7 +394,9 @@ module ahci_fsm
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0;
//// if (hba_rst || pre_jump_w) fsm_transitions <= 0;
/// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code
if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0;
else if (fsm_transitions_w) fsm_transitions <= 1;
// else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
// (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
......
ahci/ahci_sata_layers.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_sata_layers
* Date:2016-01-19
* Author: andrey
* Description: Link and PHY SATA layers
/*!
* <b>Module:</b>ahci_sata_layers
* @file ahci_sata_layers.v
* @date 2016-01-19
* @author Andrey Filippov
*
* @brief Link and PHY SATA layers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_sata_layers #(
......
ahci/ahci_top.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_top
* Date:2016-01-09
* Author: Andrey Filippov
* Description: Top module of the AHCI implementation
/*!
* <b>Module:</b>ahci_top
* @file ahci_top.v
* @date 2016-01-09
* @author Andrey Filippov
*
* @brief Top module of the AHCI implementation
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_top#(
......
ahci/axi_ahci_regs.v
View file @ 727bf4bc
/*******************************************************************************
* Module: axi_ahci_regs
* Date:2015-12-29
* Author: Andrey Filippov
* Description: Registers for single-port AHCI over AXI implementation
/*!
* <b>Module:</b>axi_ahci_regs
* @file axi_ahci_regs.v
* @date 2015-12-29
* @author Andrey Filippov
*
* @brief Registers for single-port AHCI over AXI implementation
* Combination of PCI Headers, PCI power management, and HBA memory
* 128 DWORD registers
* Registers, with bits being RO, RW, RWC, RW1
*
* Copyright (c) 2015 Elphel, Inc .
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* axi_ahci_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -33,7 +38,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
......@@ -327,7 +332,8 @@ module axi_ahci_regs#(
end
always @ (hba_clk) begin
//// always @ (hba_clk) begin
always @ (posedge aclk) begin
was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]};
was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]};
end
......
ahci/axi_hp_abort.v
View file @ 727bf4bc
/*******************************************************************************
* Module: axi_hp_abort
* Date:2016-02-07
* Author: andrey
* Description: Trying to gracefully reset AXI HP after aborted transmission
/*!
* <b>Module:</b>axi_hp_abort
* @file axi_hp_abort.v
* @date 2016-02-07
* @author Andrey Filippov
*
* @brief Trying to gracefully reset AXI HP after aborted transmission
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w
* Reset only by global reset (system POR) - probably it is not possible to just
* reset PL or relaod bitfile,
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* axi_hp_abort.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -21,7 +26,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module axi_hp_abort(
......
ahci/freq_meter.v
View file @ 727bf4bc
/*******************************************************************************
* Module: freq_meter
* Date:2016-02-13
* Author: andrey
* Description: Measure device clock frequency to set the local clock
/*!
* <b>Module:</b>freq_meter
* @file freq_meter.v
* @date 2016-02-13
* @author Andrey Filippov
*
* @brief Measure device clock frequency to set the local clock
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* freq_meter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module freq_meter#(
......
ahci/sata_ahci_top.v
View file @ 727bf4bc
/*******************************************************************************
* Module: sata_ahci_top
* Date: 2015-07-11
* Author: Alexey
* Description: sata for z7nq top-level module
/*!
* <b>Module:</b>sata_ahci_top
* @file sata_ahci_top.v
* @date 2015-07-11
* @author Alexey
*
* @brief Top of the AHCI implementation of the host adapter
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* sata_ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
......
device/oob_dev.v
View file @ 727bf4bc
/*******************************************************************************
* Module: oob
* Date: 2015-07-11
* Author: Alexey
* Description: sata oob unit implementation
/*!
* <b>Module:</b>oob_dev
* @file oob_dev.v
* @date 2015-07-11
* @author Alexey
*
* Copyright (c) 2015 Elphel, Inc.
* oob.v is free software; you can redistribute it and/or modify
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* oob_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob.v file is distributed in the hope that it will be useful,
* oob_dev.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/*
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
......
device/sata_phy_dev.v
View file @ 727bf4bc
/*******************************************************************************
* Module: sata_phy
* Date: 2015-07-11
* Author: Alexey
* Description: phy-level, including oob, clock generation and GTXE2
/*!
* <b>Module:</b>sata_phy_dev
* @file sata_phy_dev.v
* @date 2015-07-11
* @author Alexey
*
* Copyright (c) 2015 Elphel, Inc.
* sata_phy.v is free software; you can redistribute it and/or modify
* @brief phy-level, including oob, clock generation and GTXE2
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* sata_phy_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sata_phy.v file is distributed in the hope that it will be useful,
* sata_phy_dev.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "oob_dev.v"
module sata_phy_dev #(
parameter DATA_BYTE_WIDTH = 4
......
generated/action_decoder.v
View file @ 727bf4bc
/*******************************************************************************
* Module: action_decoder
* Date:2016-03-12
* Author: auto-generated file, see ahci_fsm_sequence_old.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
/*!
* <b>Module:</b>action_decoder
* @file action_decoder.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
......
generated/condition_mux.v
View file @ 727bf4bc
/*******************************************************************************
* Module: condition_mux
* Date:2016-03-12
* Author: auto-generated file, see ahci_fsm_sequence_old.py
* Description: Select condition
*******************************************************************************/
/*!
* <b>Module:</b>condition_mux
* @file condition_mux.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Select condition
*/
`timescale 1ns/1ps
......
host/crc.v
View file @ 727bf4bc
/*******************************************************************************
* Module: crc
* Date: 2015-07-11
* Author: Alexey
* Description: crc calculations for the link layer
/*!
* <b>Module:</b>crc
* @file crc.v
* @date 2015-07-11
* @author Alexey
*
* @brief crc calculations for the link layer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* crc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/* same as for a scrambler, @ doc p.561 */
// TODO make it parallel, make another widths support
module crc #(
......
host/drp_other_registers.v
View file @ 727bf4bc
/*******************************************************************************
* Module: drp_other_registers
* Date:2016-03-13
* Author: andrey
* Description: Additional registers controlled/read back over DRP
/*!
* <b>Module:</b>drp_other_registers
* @file drp_other_registers.v
* @date 2016-03-13
* @author Andrey Filippov
*
* @brief Additional registers controlled/read back over DRP
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* drp_other_registers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module drp_other_registers#(
......
host/elastic1632.v
View file @ 727bf4bc
/*******************************************************************************
* Module: elastic1632
* Date:2016-02-03
* Author: andrey
* Description: Elastic buffer with 16-bit data input and 32-bit output
/*!
* <b>Module:</b>elastic1632
* @file elastic1632.v
* @date 2016-02-03
* @author Andrey Filippov
*
* @brief Elastic buffer with 16-bit data input and 32-bit output
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* elastic1632.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module elastic1632#(
......
host/gtx_10x8dec.v
View file @ 727bf4bc
/*******************************************************************************
* Module: gtx_10x8dec
* Date: 2015-07-11
* Author: Alexey
* Description: 8x10 encoder implementation
/*!
* <b>Module:</b>gtx_10x8dec
* @file gtx_10x8dec.v
* @date 2015-07-11
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_10x8dec.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_10x8dec(
input wire rst,
input wire clk,
......
host/gtx_8x10enc.v
View file @ 727bf4bc
/*******************************************************************************
* Module: gtx_8x10enc
* Date: 2015-07-11
* Author: Alexey
* Description: 8x10 encoder implementation
/*!
* <b>Module:</b>gtx_8x10enc
* @file gtx_8x10enc.v
* @date 2015-07-11
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_8x10enc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_8x10enc(
input wire rst,
input wire clk,
......
host/gtx_comma_align.v
View file @ 727bf4bc
/*******************************************************************************
* Module: gtx_comma_align
* Date: 2015-07-11
* Author: Alexey
* Description: comma aligner implementation
/*!
* <b>Module:</b>gtx_comma_align
* @file gtx_comma_align.v
* @date 2015-07-11
* @author Alexey
*
* @brief comma aligner implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_comma_align.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_comma_align(
input wire rst,
input wire clk,
......
host/gtx_elastic.v
View file @ 727bf4bc
/*******************************************************************************
* Module: gtx_elastic
* Date: 2015-07-11
* Author: Alexey
* Description: elastic buffer implementation
/*!
* <b>Module:</b>gtx_elastic
* @file gtx_elastic.v
* @date 2015-07-11
* @author Alexey
*
* @brief elastic buffer implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_elastic.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_elastic #(
parameter DEPTH_LOG2 = 4, // 3, // => 8 total rows
parameter OFFSET = 8 // 4 // distance between read and write pointers, = wr_ptr - rd_ptr
......
host/gtx_wrap.v
View file @ 727bf4bc
/*******************************************************************************
* Module: gtx_wrap
* Date: 2015-08-24
* Author: Alexey
* Description: shall replace gtx's PCS part functions, bypassing PCS itself in gtx
/*!
* <b>Module:</b>gtx_wrap
* @file gtx_wrap.v
* @date 2015-08-24
* @author Alexey
*
* @brief shall replace gtx's PCS part functions, bypassing PCS itself in gtx
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_wrap.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "gtx_8x10enc.v"
//`include "gtx_10x8dec.v"
//`include "gtx_comma_align.v"
......
host/link.v
View file @ 727bf4bc
/*******************************************************************************
* Module: link
* Date: 2015-07-11
* Author: Alexey
* Description: sata link layer implementation
/*!
* <b>Module:</b>link
* @file link.v
* @date 2015-07-11
* @author Alexey
*
* @brief sata link layer implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* link.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "scrambler.v"
//`include "crc.v"
module link #(
......
host/oob.v
View file @ 727bf4bc
/*******************************************************************************
* Module: oob
* Date: 2015-07-11
* Author: Alexey
* Description: sata oob unit implementation
/*!
* <b>Module:</b>oob
* @file oob.v
* @date 2015-07-11
* @author Alexey
*
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* oob.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/*
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
......
host/oob_ctrl.v
View file @ 727bf4bc
/*******************************************************************************
* Module: oob_ctrl
* Date: 2015-07-11
* Author: Alexey
* Description: module to start oob sequences and to handle errors
/*!
* <b>Module:</b>oob_ctrl
* @file oob_ctrl.v
* @date 2015-07-11
* @author Alexey
*
* @brief module to start oob sequences and to handle errors
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "oob.v"
module oob_ctrl #(
parameter DATA_BYTE_WIDTH = 4,
......
host/sata_phy.v
View file @ 727bf4bc
/*******************************************************************************
* Module: sata_phy
* Date: 2015-07-11
* Author: Alexey
* Description: phy-level, including oob, clock generation and GTXE2
/*!
* <b>Module:</b>sata_phy
* @file sata_phy.v
* @date 2015-07-11
* @author Alexey
*
* @brief phy-level, including oob, clock generation and GTXE2
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* sata_phy.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "oob_ctrl.v"
//`include "gtx_wrap.v"
module sata_phy #(
......
host/scrambler.v
View file @ 727bf4bc
/*******************************************************************************
* Module: scrambler
* Date: 2015-07-11
* Author: Alexey
* Description: a scrambler for the link layer
/*!
* <b>Module:</b>scrambler
* @file scrambler.v
* @date 2015-07-11
* @author Alexey
*
* @brief a scrambler for the link layer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* scrambler.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/*
* Algorithm is taken from the doc, p.565. TODO make it parallel
*/
......
includes/ahci_defaults.vh
View file @ 727bf4bc
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000B001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @ 727bf4bc
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h2;
localparam PCI_Header__RID__RID__DFLT = 'hb;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
includes/tasks_tests_memory.vh
View file @ 727bf4bc
/*******************************************************************************
* Module: tasks_tests_memory
* Date:2015-08-01
* Author: andrey
* Author: Andrey Filippov
* Description: Top-level tasks for testing memory subsystem functionality
*
* Copyright (c) 2015 Elphel, Inc .
......@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
......@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
......@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
......@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end
......@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
......
includes/x393_parameters.vh
View file @ 727bf4bc
......@@ -332,7 +332,7 @@
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
......
includes/x393_tasks_ps_pio.vh
View file @ 727bf4bc
......@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to
input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
......
py393sata/.project
View file @ 727bf4bc
......@@ -14,4 +14,11 @@
<natures>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393_sata/py393sata/vivado_logs/VivadoSynthesis-20161206185119051.log</location>
</link>
</linkedResources>
</projectDescription>
py393sata/ahci_fsm_sequence.py
View file @ 727bf4bc
......@@ -490,13 +490,14 @@ def bin_cnk (n,k):
result.append(d)
return result
def condition_mux_verilog(conditions, condition_vals, module_name, fanout, file=None):
header_template="""/*******************************************************************************
* Module: %s
* Date:%s
* Author: auto-generated file, see %s
* Description: Select condition
*******************************************************************************/
def condition_mux_verilog(conditions, condition_vals, module_name, fanout, header_file="", file=None):
header_template="""/*!
* <b>Module:</b>%s
* @file %s
* @date %s
* @author auto-generated file, see %s
* @brief Select condition
*/
`timescale 1ns/1ps
......@@ -505,6 +506,10 @@ module %s (
input ce, // enable recording all conditions
input [%2d:0] sel,
output condition,"""
if header_file:
header_file = os.path.basename(header_file)
else:
header_file=""
v=max(condition_vals.values())
num_inputs = 0;
while v:
......@@ -512,7 +517,7 @@ module %s (
v >>= 1
maximal_length = max([len(n) for n in conditions])
numregs = (len(conditions) + fanout) // fanout # one more bit for 'always' (sel == 0)
header = header_template%(module_name, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
header = header_template%(module_name, header_file, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
print(header,file=file)
for input_name in conditions[:len(conditions)-1]:
print(" input %s,"%(input_name), file=file)
......@@ -564,13 +569,14 @@ module %s (
print("endmodule",file=file)
def action_decoder_verilog(actions, action_vals, module_name, file=None):
header_template="""/*******************************************************************************
* Module: %s
* Date:%s
* Author: auto-generated file, see %s
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
def action_decoder_verilog(actions, action_vals, module_name, header_file="", file=None):
header_template="""/*!
* <b>Module:</b>%s
* @file %s
* @date %s
* @author auto-generated file, see %s
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
......@@ -578,6 +584,10 @@ module %s (
input clk,
input enable,
input [%2d:0] data,"""
if header_file:
header_file = os.path.basename(header_file)
else:
header_file=""
v=max(action_vals.values())
num_inputs = 0;
while v:
......@@ -591,7 +601,7 @@ module %s (
names.append(a)
maximal_length = max([len(n) for n in names])
header = header_template%(module_name, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
header = header_template%(module_name, header_file, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
print(header,file=file)
for output_name in names[:len(names)-1]:
print(" output reg %s,"%(output_name),file=file)
......@@ -862,14 +872,14 @@ if not action_decoder_verilog_path:
action_decoder_verilog(actions, action_vals, action_decoder_module_name)
else:
with open(os.path.abspath(os.path.join(os.path.dirname(__file__), action_decoder_verilog_path)),"w") as out_file:
action_decoder_verilog(actions, action_vals, action_decoder_module_name, out_file)
action_decoder_verilog(actions, action_vals, action_decoder_module_name, action_decoder_verilog_path, out_file)
print ("AHCI FSM actions decoder is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), action_decoder_verilog_path))))
if not condition_mux_verilog_path:
condition_mux_verilog(conditions, condition_vals, condition_mux_module_name, condition_mux_fanout)
else:
with open(os.path.abspath(os.path.join(os.path.dirname(__file__), condition_mux_verilog_path)),"w") as out_file:
condition_mux_verilog(conditions, condition_vals,condition_mux_module_name, condition_mux_fanout, out_file)
condition_mux_verilog(conditions, condition_vals,condition_mux_module_name, condition_mux_fanout, condition_mux_verilog_path, out_file)
print ("AHCI FSM conditions multiplexer is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), condition_mux_verilog_path))))
code = code_generator (sequence, action_vals, condition_vals, labels)
......
py393sata/create_ahci_registers.py
View file @ 727bf4bc
......@@ -27,7 +27,11 @@ __status__ = "Development"
#import sys
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
RID = 0x02 # Revision ID (use for bitstream version)
#RID = 0x02 # Revision ID (use for bitstream version)
"""
**** Modify next value for new file versions, re-run this file *****
"""
RID = 0x0b # Revision ID
VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001
SSVID = 0xfffe
......
py393sata/x393sata.py
View file @ 727bf4bc
......@@ -281,14 +281,14 @@ class x393sata(object):
else:
for d in data:
self.x393_mem.write_mem(FPGA_RST_CTRL,d)
def get_mem_buf_args(self, saddr=None, len=None):
def get_mem_buf_args(self, saddr=None, length=None):
#Is it really needed? Or use cache line size (32B), not PAGE_SIZE?
args=""
if (saddr is None) or (len is None):
if (saddr is None) or (length is None):
return ""
else:
eaddr = PAGE_SIZE * ((saddr+len) // PAGE_SIZE)
if ((saddr+len) % PAGE_SIZE):
eaddr = PAGE_SIZE * ((saddr+length) // PAGE_SIZE)
if ((saddr+length) % PAGE_SIZE):
eaddr += PAGE_SIZE
saddr = PAGE_SIZE * (saddr // PAGE_SIZE)
return "%d %d"%(saddr, eaddr-saddr )
......@@ -299,14 +299,14 @@ class x393sata(object):
return "_d2h"
elif direction.upper()[0] in "B":
return "_bidir"
def sync_for_cpu(self, direction, saddr=None, len=None):
def sync_for_cpu(self, direction, saddr=None, length=None):
with open (MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, len),file=f)
print (self.get_mem_buf_args(saddr, length),file=f)
def sync_for_device(self, direction, saddr=None, len=None):
def sync_for_device(self, direction, saddr=None, length=None):
with open (MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, len),file=f)
print (self.get_mem_buf_args(saddr, length),file=f)
'''
def flush_mem(self, saddr=None, len=None):
......@@ -368,13 +368,13 @@ class x393sata(object):
if not bitfile:
bitfile=DEFAULT_BITFILE
if quiet < 2:
print ("FPGA clock OFF")
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
if quiet < 2:
print ("Reset ON")
print ("Reset ON")
self.reset(0)
if quiet < 2:
print ("cat %s >%s"%(bitfile,FPGA_LOAD_BITSTREAM))
print ("cat %s >%s"%(bitfile,FPGA_LOAD_BITSTREAM))
if not self.DRY_MODE:
l=0
with open(bitfile, 'rb') as src, open(FPGA_LOAD_BITSTREAM, 'wb') as dst:
......@@ -414,22 +414,22 @@ class x393sata(object):
def set_zynq_esata(self):
self.vsc3304.connect_zynq_esata()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def set_zynq_ssata(self):
self.vsc3304.connect_zynq_ssata()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def set_esata_ssd(self):
self.vsc3304.connect_esata_ssd()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def set_debug_oscilloscope(self):
self.vsc3304.connect_debug()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def reinit_mux(self):
"""
......@@ -644,8 +644,8 @@ class x393sata(object):
(0x80 << 8) | # set C = 1
(ATA_IDFY << 16) | # Command = 0xEC (IDFY)
( 0 << 24)) # features = 0 ?
# All other 4 DWORDs are 0 for this command
# Set PRDT (single item) TODO: later check multiple small ones
# All other 4 DWORDs are 0 for this command
# Set PRDT (single item) TODO: later check multiple small ones
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (0 << 2), DATAIN_ADDRESS + IDENTIFY_BUF)
prdt_int = 0
if prd_irqs:
......@@ -700,7 +700,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -819,7 +819,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -944,7 +944,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -1059,7 +1059,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -1174,7 +1174,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -1449,7 +1449,7 @@ class x393sata(object):
if not write_mode is None:
mode = ((mode ^ ((write_mode & 0xf) << 4)) & (0xf << 4)) ^ mode
if not read_mode is None:
mode = ((mode ^ ((reade_mode & 0xf) << 0)) & (0xf << 0)) ^ mode
mode = ((mode ^ ((read_mode & 0xf) << 0)) & (0xf << 0)) ^ mode
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__AFI_CACHE'), mode)
return {'write':(mode >> 4) & 0xf, 'read':(mode >> 0) & 0xf}
......@@ -1474,6 +1474,7 @@ def init_sata():
sata.reinit_mux()
sata.configure(bitfile=None,
quiet=4) # 4 will be really quiet
print ("PCI_Header__RID = 0x%x"%(sata.x393_mem.read_mem(sata.get_reg_address('PCI_Header__RID'))))
sata.drp (0x20b,0x221) # bypass, clock align
#hex(sata.drp (0x20b))
......@@ -1496,6 +1497,51 @@ if __name__ == "__main__":
"""
x393sata.py
modprobe ahci_elphel &
sleep 2
echo 1 > /sys/devices/soc0/amba@0/80000000.elphel-ahci/load_module
#to remove:
umount /dev/sda
rmmod ahci_elphel
142615472
wget -O - "http://localhost/x393_vsc330x.php?c:zynq=esata"
wget -O - "http://localhost/x393_vsc330x.php?c:zynq=ssd"
cd /usr/local/bin; python
from __future__ import print_function
from __future__ import division
import x393sata
import x393_mem
mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata()
hex(mem.read_mem(sata.get_reg_address('PCI_Header__RID')))
sata.setup_pio_read_identify_command()
sata.dd_read_dma_ext(142615470, 512, 512)
sata.dd_read_dma_ext(142615472, 512, 512)
Read write pointer to datascope:
hex(((mem.read_mem(0x80000ffc) >> 10) & 0xffc) + 0x80001000)
Datascope has a ring buffer of 4K: 0x80001000..0x80001fff
mem.write_mem(0x80000118,0x10) # stop
dd if=/dev/sdj count=1 skip=142615470 of=/dev/null
s=set()
for i in range(10000):
s.add(mem.read_mem (0x80000ffc) & 0x1ff)
s
hex(mem.read_mem (0x80000ffc))
def get_MAC():
with open("/sys/class/net/eth0/address") as sysfile:
return sysfile.read()
......
system_defines.vh
View file @ 727bf4bc
/*!
* @file system_defines.vh
* @date 2015-02-28
* @author Andrey Filippov
*
* @brief Preprocessor macros definitions to be included in AHCI SATA project
* files when built as a stanalone project (https://github.com/Elphel/x393_sata).
* Not used when AHCI SATA is a part of the x393 project.
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* system_defines.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* system_defines.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
......
tb/tb_ahci.tf
View file @ 727bf4bc
......@@ -38,7 +38,7 @@
`define PRELOAD_BRAMS
`define CHECKERS_ENABLED
`define use200Mhz 1
//`define SEND_READ_ERROR
/*
* using x393_testbench01.tf style, contains a lot of copy-pasted code from there
*/
......@@ -1409,12 +1409,29 @@ initial begin //Host
// maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
// maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt
//// maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup)
//// maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK | HBA_PORT__PxIE__TFEE__MASK); // allow DHR and TFEE interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK | HBA_PORT__PxIE__TFEE__MASK); // clear those interrupts
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 3); // Record current time in datascope with a 3-bit tag
wait (IRQ);
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 4); // Record current time in datascope with a 3-bit tag
maxigp1_print (HBA_PORT__PxIS__PSS__ADDR << 2,"HBA_PORT__PxIS__PSS__ADDR after got d2h");
if (registered_rdata & HBA_PORT__PxIE__TFEE__MASK) begin
repeat (20) @(posedge CLK);
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
// clear command issued
// maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 0); // 'PxCI' - Clear 'Command issued' for slot 0 (the only one)
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0
repeat (20) @(posedge CLK);
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__TFEE__MASK); // clear this interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
repeat (100) @(posedge CLK);
$finish;
end
// TESTBENCH_TITLE = "Got Identify";
TESTBENCH_TITLE = "Got D2HRFIS";
......@@ -1592,7 +1609,19 @@ initial begin //Device
dev.send_dma_activate (69, // input integer id;
status); // output integer status;
end else if (func_is_dev_read_dma_ext(dev.receive_data[0])) begin
`ifdef SEND_READ_ERROR
dev.send_D2HR(70, // same data as received from bad block read (HDD)
1, // irq,
8'h25, // status
8'h40, // error
8'h08, // device
24'h8023b1, // lba_low
24'h000008, // lba_high
16'h0001, // count
status); // output: result status
DEVICE_TITLE = "Device sent ERROR (bad block)";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
`else
// dev.send_incrementing_data(70, // input integer id;
dev.send_incrementing_data_pause(70, // input integer id;
128, // number of dwords to send, later decode count field
......@@ -1612,7 +1641,7 @@ initial begin //Device
status); // output: result status
DEVICE_TITLE = "Device sent D2H FIS (DMA D2H over)";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
`endif
end else if (func_is_h2d_data(dev.receive_data[0])) begin
DEVICE_TITLE = "Got H2D data";
$display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time);
......
wrapper/GTXE2_GPL.v
View file @ 727bf4bc
/*******************************************************************************
* Module: GTXE2_GPL
* Date: 2015-09-08
* Author: Alexey
* Description: emulates GTXE2_CHANNEL primitive behaviour.
/*!
* <b>Module:</b>GTXE2_GPL
* @file GTXE2_GPL.v
* @date 2015-09-08
* @author Alexey
*
* @brief emulates GTXE2_CHANNEL primitive behaviour.
* The file is gathered from multiple files
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -31,7 +36,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/**
* Original unisims primitive's interfaces, according to xilinx's user guide:
* "7 Series FPGAs GTX/GTH Transceivers User Guide UG476(v1.11)", which is further
......
wrapper/clock_inverter.v
View file @ 727bf4bc
/*******************************************************************************
* Module: clock_inverter
* Date:2016-02-11
* Author: andrey
* Description: Glitch-free clock controlled inverter
/*!
* <b>Module:</b>clock_inverter
* @file clock_inverter.v
* @date 2016-02-11
* @author Andrey Filippov
*
* @brief Glitch-free clock controlled inverter
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* clock_inverter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module clock_inverter(
......
wrapper/gtxe2_channel_wrapper.v
View file @ 727bf4bc
/*******************************************************************************
* Module: gtxe2_channel_wrapper
* Date: 2015-09-07
* Author: Alexey
* Description: wrapper to switch between closed unisims primitive and open-source one
/*!
* <b>Module:</b>gtxe2_channel_wrapper
* @file gtxe2_channel_wrapper.v
* @date 2015-09-07
* @author Alexey
*
* @brief wrapper to switch between closed unisims primitive and open-source one
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`include "system_defines.vh"
module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37
......
x393_sata.bit
View file @ 727bf4bc
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