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x393_sata
Commit 727bf4bc authored by Andrey Filippov's avatar Andrey Filippov
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merged with errhandl

parents e155806b c1fba53a
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Showing with 696 additions and 513 deletions
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs 0 → 100644
View file @ 727bf4bc
FPGA_project_@_ImplementationTopFile=top.v
FPGA_project_@_ImplementationTopModule=top
FPGA_project_@_SimulationTopFile=tb/tb_top.v
FPGA_project_@_SimulationTopModule=tb
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs 0 → 100644
View file @ 727bf4bc
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs 0 → 100644
View file @ 727bf4bc
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs 0 → 100644
View file @ 727bf4bc
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoSynthesis.prefs 0 → 100644
View file @ 727bf4bc
VivadoSynthesis_@_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false
VivadoSynthesis_@_flatten_hierarchy=none
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_flatten_hierarchy<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs 0 → 100644
View file @ 727bf4bc
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs 0 → 100644
View file @ 727bf4bc
com.elphel.store.context.VivadoTimingReportImplemented=
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs 0 → 100644
View file @ 727bf4bc
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs 0 → 100644
View file @ 727bf4bc
com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_@_SaveLogsPreprocessor=true
iverilog_@_SaveLogsSimulator=true
iverilog_@_TopModulesOther=glbl<-@\#\#@->
.eclipse_project_setup/.settings/com.elphel.vdt.prefs 0 → 100644
View file @ 727bf4bc
com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
eclipse.preferences.version=1
.eclipse_project_setup/README_eclipse_project_setup 0 → 100644
View file @ 727bf4bc
Directory .eclipse_project_setup contains "master"/initial settings for tyhis project in Eclipse IDE. Copy the contents to the project root after cloning the project (it may be done automatically if cloned by a script) or if you current settings get corrupted.
.gitignore
View file @ 727bf4bc
.cproject
.project
.externalToolBuilders/
.pydevproject
unisims
debug
vivado_*
......@@ -14,4 +17,5 @@ x393.prj
*.pickle
bitbake-logs
sysroots
attic/*
\ No newline at end of file
attic/*
image
.project deleted 100644 → 0
View file @ e155806b
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>x393_sata</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.python.pydev.PyDevBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
<value>echo &apos;Clean&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
<value>0</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
<value>echo &apos;No Build Configuration Specified&apos;</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
<value>true</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
<value>Default</value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
<value></value>
</dictionary>
<dictionary>
<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
<value></value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160313145052718.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313145052718.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160313145236495.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160313145052718.log</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160313145236495.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160313145052718.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 727bf4bc
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=top.v
FPGA_project_3_ImplementationTopModule=top
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
FPGA_project_@_ImplementationTopFile=top.v
FPGA_project_@_ImplementationTopModule=top
FPGA_project_@_SimulationTopFile=tb/tb_top.v
FPGA_project_@_SimulationTopModule=tb
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.settings/com.elphel.vdt.ISExst.prefs
View file @ 727bf4bc
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 727bf4bc
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ 727bf4bc
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 727bf4bc
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
VivadoSynthesis_@_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false
VivadoSynthesis_@_flatten_hierarchy=none
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_flatten_hierarchy<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ 727bf4bc
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ 727bf4bc
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
com.elphel.store.context.VivadoTimingReportImplemented=
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ 727bf4bc
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ 727bf4bc
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_95_IcarusTopFile<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IVerilogOther<-@\#\#@->iverilog_@_Param_Exe<-@\#\#@->iverilog_@_VVP_Exe<-@\#\#@->iverilog_@_GtkWave_Exe<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_105_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_110_ShowNoProblem=true
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_ahci_01.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_95_IcarusTopFile=tb/tb_ahci.tf
iverilog_99_GrepFindErrWarn=error|warning|sorry
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_@_Param_Exe=/usr/local/bin/iverilog
iverilog_@_SaveLogsPreprocessor=true
iverilog_@_SaveLogsSimulator=true
iverilog_@_ShowNoProblem=true
iverilog_@_TopModulesOther=glbl<-@\#\#@->
iverilog_@_VVP_Exe=/usr/local/bin/vvp
ahci/ahci_ctrl_stat.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_ctrl_stat
* Date:2016-01-12
* Author: andrey
* Description: Copy of significant register fields, updating them in
/*!
* <b>Module:</b>ahci_ctrl_stat
* @file ahci_ctrl_stat.v
* @date 2016-01-12
* @author Andrey Filippov
*
* @brief Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible)
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_ctrl_stat.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -18,7 +23,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_ctrl_stat #(
......@@ -493,7 +498,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0];
end
// HBA_PORT__PxCMD register - different behaviors of differtnt fields
// HBA_PORT__PxCMD register - different behaviors of different fields
// use PxCMD_MASK to prevent generation of unneeded register bits
always @(posedge mclk) begin
......
ahci/ahci_dma.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma
* Date:2016-01-01
* Author: Andrey Filippov
* Description: DMA R/W over 64-AXI channel for AHCI implementation
/*!
* <b>Module:</b>ahci_dma
* @file ahci_dma.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief DMA R/W over 64-AXI channel for AHCI implementation
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma (
......
ahci/ahci_dma_rd_fifo.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma_rd_fifo
* Date:2016-01-01
* Author: Andrey Filippov
* Description: cross clocks, word-realign, 64->32
/*!
* <b>Module:</b>ahci_dma_rd_fifo
* @file ahci_dma_rd_fifo.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 64->32
* Convertion from x64 QWORD-aligned AXI data @hclk to
* 32-bit word-aligned data at mclk
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_rd_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_rd_fifo#(
......
ahci/ahci_dma_rd_stuff.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma_rd_stuff
* Date:2016-01-01
* Author: andrey
* Description: Stuff DWORD data with missing words into continuous 32-bit data
/*!
* <b>Module:</b>ahci_dma_rd_stuff
* @file ahci_dma_rd_stuff.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief Stuff DWORD data with missing words into continuous 32-bit data
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma_rd_stuff.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_rd_stuff(
......
ahci/ahci_dma_wr_fifo.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_dma_wr_fifo
* Date:2016-01-02
* Author: Andrey Filippov
* Description: cross clocks, word-realign, 32 -> 64 with byte write mask
/*!
* <b>Module:</b>ahci_dma_wr_fifo
* @file ahci_dma_wr_fifo.v
* @date 2016-01-02
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 32 -> 64 with byte write mask
* Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned
* AXI data @hclk
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_wr_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_wr_fifo#(
......
ahci/ahci_fis_receive.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_fis_receive
* Date:2016-01-06
* Author: Andrey Filippov
* Description: Receives incoming FIS-es, forwards DMA ones to DMA engine
/*!
* <b>Module:</b>ahci_fis_receive
* @file ahci_fis_receive.v
* @date 2016-01-06
* @author Andrey Filippov
*
* @brief Receives incoming FIS-es, forwards DMA ones to DMA engine
* Stores received FIS-es if requested
*
* 'fis_first_vld' is asserted when the FIFO output contains first DWORD
......@@ -13,7 +15,10 @@
* one of the 3 states (fis_ok, fis_err and fis_ferr) are raised
* This module also receives/updates device signature and PxTFD ERR and STS.
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_fis_receive.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -26,7 +31,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fis_receive#(
......
ahci/ahci_fis_transmit.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_fis_transmit
* Date:2016-01-07
* Author: andrey
* Description: Fetches commands, command tables, creates/sends FIS
/*!
* <b>Module:</b>ahci_fis_transmit
* @file ahci_fis_transmit.v
* @date 2016-01-07
* @author Andrey Filippov
*
* @brief Fetches commands, command tables, creates/sends FIS
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fis_transmit.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fis_transmit #(
......
ahci/ahci_fsm.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_fsm
* Date:2016-01-10
* Author: andrey
* Description: AHCI host+port0 state machine
/*!
* <b>Module:</b>ahci_fsm
* @file ahci_fsm.v
* @date 2016-01-10
* @author Andrey Filippov
*
* @brief AHCI host+port0 state machine
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fsm.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fsm
......@@ -389,7 +394,9 @@ module ahci_fsm
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0;
//// if (hba_rst || pre_jump_w) fsm_transitions <= 0;
/// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code
if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0;
else if (fsm_transitions_w) fsm_transitions <= 1;
// else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
// (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
......
ahci/ahci_sata_layers.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_sata_layers
* Date:2016-01-19
* Author: andrey
* Description: Link and PHY SATA layers
/*!
* <b>Module:</b>ahci_sata_layers
* @file ahci_sata_layers.v
* @date 2016-01-19
* @author Andrey Filippov
*
* @brief Link and PHY SATA layers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_sata_layers #(
......
ahci/ahci_top.v
View file @ 727bf4bc
/*******************************************************************************
* Module: ahci_top
* Date:2016-01-09
* Author: Andrey Filippov
* Description: Top module of the AHCI implementation
/*!
* <b>Module:</b>ahci_top
* @file ahci_top.v
* @date 2016-01-09
* @author Andrey Filippov
*
* @brief Top module of the AHCI implementation
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_top#(
......
ahci/axi_ahci_regs.v
View file @ 727bf4bc
/*******************************************************************************
* Module: axi_ahci_regs
* Date:2015-12-29
* Author: Andrey Filippov
* Description: Registers for single-port AHCI over AXI implementation
/*!
* <b>Module:</b>axi_ahci_regs
* @file axi_ahci_regs.v
* @date 2015-12-29
* @author Andrey Filippov
*
* @brief Registers for single-port AHCI over AXI implementation
* Combination of PCI Headers, PCI power management, and HBA memory
* 128 DWORD registers
* Registers, with bits being RO, RW, RWC, RW1
*
* Copyright (c) 2015 Elphel, Inc .
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* axi_ahci_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -33,7 +38,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
......@@ -327,7 +332,8 @@ module axi_ahci_regs#(
end
always @ (hba_clk) begin
//// always @ (hba_clk) begin
always @ (posedge aclk) begin
was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]};
was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]};
end
......
ahci/axi_hp_abort.v
View file @ 727bf4bc
/*******************************************************************************
* Module: axi_hp_abort
* Date:2016-02-07
* Author: andrey
* Description: Trying to gracefully reset AXI HP after aborted transmission
/*!
* <b>Module:</b>axi_hp_abort
* @file axi_hp_abort.v
* @date 2016-02-07