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byte_lane.v Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
cmd_addr.v adjusting constraint attributes in the source
cmda_single.v moved directory phy under memcntrl (as it is a part of memory controller)
dm_single.v Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
dq_single.v adjusting constraint attributes in the source
dqs_single.v moved directory phy under memcntrl (as it is a part of memory controller)
dqs_single_nofine.v moved directory phy under memcntrl (as it is a part of memory controller)
mcontr_sequencer.v simulating multiple simultanerous sesnor/compressor channels
phy_cmd.v Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
phy_top.v Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation