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.settings working on hardware testing, added utility functions to load bitstream and use GPIO for debugging
dbg preparing for testing membridge module on the target system
.project creating Python program to pass Verilog parameters to Python FPGA tests
.pydevproject creating Python program to pass Verilog parameters to Python FPGA tests
args added save/load state with pickle
get_test_dq_dqs_data.py Cleaning up the code, adding provisions for multiple solutions for the same phase - this will be the case at higher clock frequencies
hargs added save/load state with pickle
hargs-auto cleaned up, before multiple branches in dqs and cmda
import_verilog_parameters.py chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
test_mcntrl.py preparing for testing membridge module on the target system
verilog_utils.py Implemented measurement/processing of address/bank lines output delays
vrlg.py Debugging hardware, added functionality to detect cache-related problems
x393_axi_control_status.py Debugging hardware, added functionality to detect cache-related problems
x393_lma.py added method to generate parameters summary
x393_mcntrl_adjust.py debugging qith hardware
x393_mcntrl_buffers.py debugging qith hardware
x393_mcntrl_eyepatterns.py Split py393/x393_mcntrl_adjust.py
x393_mcntrl_membridge.py Debugging hardware, added functionality to detect cache-related problems
x393_mcntrl_tests.py Debugging hardware, added functionality to detect cache-related problems
x393_mcntrl_timing.py Cleaning up the code, adding provisions for multiple solutions for the same phase - this will be the case at higher clock frequencies
x393_mem.py preparing for testing membridge module on the target system
x393_pio_sequences.py debugging qith hardware
x393_utils.py debugging qith hardware