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x393_cur_params_target.vh timing parameters generated by the hardware testing
x393_localparams.vh Fixed ddr3 -> system memory transfer
x393_mcontr_encode_cmd.vh working on Python code for hardware testing
x393_parameters.vh Debugging hardware, added functionality to detect cache-related problems
x393_simulation_parameters.vh working on hardware testing, added utility functions to load bitstream and use GPIO for debugging
x393_tasks01.vh Debugging hardware, added functionality to detect cache-related problems
x393_tasks_afi.vh moved afi-related tasks here from the top simulation test fixture
x393_tasks_mcntrl_buffers.vh Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
x393_tasks_mcntrl_en_dis_priority.vh re-organized top structure
x393_tasks_mcntrl_timing.vh Debugging hardware, added functionality to detect cache-related problems
x393_tasks_pio_sequences.vh co-debugging simulation with hardware tests to make them match
x393_tasks_ps_pio.vh more verilog tasks converted to python
x393_tasks_status.vh simulating/debugging