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Commit f35c087d authored by Andrey Filippov's avatar Andrey Filippov
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simulating/debugging LWIR sensor FPGA code

parent 654584f3
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cocotb/x393_cocotb_lwir_04.sav
View file @ f35c087d
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cocotb/x393_dut.v
View file @ f35c087d
......@@ -1746,8 +1746,7 @@ simul_axi_hp_wr #(
);
/* Instance template for module simul_lwir160x120_vospi */
/*
wire lwir1_miso;
simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
......@@ -1791,7 +1790,7 @@ simul_axi_hp_wr #(
.telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0]
);
*/
`ifdef LWIR
simul_lwir160x120_vospi #(
.DATA_FILE (LWIR_DATA_FILE1),
......@@ -1967,9 +1966,7 @@ simul_axi_hp_wr #(
`endif
`else
simul_sensor12bits #(
......@@ -2133,6 +2130,7 @@ simul_axi_hp_wr #(
.VACT (PX4_VACT), // output
.VACT1 () // output
);
`endif
/*
sim_soc_interrupts #(
.NUM_INTERRUPTS (NUM_INTERRUPTS)
......
compressor_jp/cmprs_cmd_decode.v
View file @ f35c087d
......@@ -318,7 +318,7 @@ module cmprs_cmd_decode#(
if (mrst) cmprs_fmode_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];
if (mrst) rows_lsb_mclk <= 4'h0f;
if (mrst) rows_lsb_mclk <= 4'hf;
else if (ctrl_we_r && di_r[CMPRS_CBIT_ROWS_LSB]) rows_lsb_mclk <= di_r[CMPRS_CBIT_ROWS_LSB-1 -:CMPRS_CBIT_ROWS_LSB_BITS];
if (mrst) bayer_shift_mclk <= 0;
......
compressor_jp/jp_channel.v
View file @ f35c087d
......@@ -247,7 +247,7 @@ module jp_channel#(
wire jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones
// wire [ 1:0] tile_margin; // margins around 16x16 tiles (0/1/2)
// wire [ 2:0] tile_shift; // tile shift from top left corner
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)
wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 6 - raw, 7 - mono8 (not yet implemented)
wire scale_diff; // divide differences by 2 (to fit in 8-bit range)
wire hdr; // second green absolute, not difference
wire subtract_dc; // subtract/restore DC components
......
includes/x393_parameters.vh
View file @ f35c087d
......@@ -305,8 +305,16 @@
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
`ifdef SIMULATION
`ifdef LWIR
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 100, // initial delay value for start pulse
`else
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
`endif
`else
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
`endif
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
......@@ -566,8 +574,13 @@
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
`ifdef SIMULATION
parameter VOSPI_SOF_TO_HACT = 1000, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 1000, // pixel clock is 480 MHz, need to slow down for memory
`else
parameter VOSPI_SOF_TO_HACT = 10, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
//`else
//sensor_fifo parameters (for parallel12)
......@@ -1000,8 +1013,14 @@
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
`ifdef SIMULATION
parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
`else
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
`endif
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
......
py393/x393_cmprs.py
View file @ f35c087d
......@@ -528,7 +528,7 @@ class X393Cmprs(object):
qbank,
dc_sub,
cmode,
bit16,
bits16,
multi_frame,
bayer,
focus_mode,
......@@ -559,7 +559,7 @@ class X393Cmprs(object):
CMPRS_CBIT_CMODE_MONO1 = 11 - mono JPEG (not yet implemented)
CMPRS_CBIT_CMODE_MONO4 = 14 - mono 4 blocks
CMPRS_CBIT_CMODE_RAW = 15 - raw (uncompressed) mode
@param bit16 - 16-bit (2 bytes per pixel) mode
@param bits16 - 16-bit (2 bytes per pixel) mode
@param multi_frame - False - single-frame buffer, True - multi-frame video memory buffer,
@param bayer - Bayer shift (0..3)
@param focus_mode - focus mode - how to combine image with "focus quality" in the result image
......@@ -584,13 +584,15 @@ class X393Cmprs(object):
print ( "row_lsb_raw = ", row_lsb_raw)
self.compressor_control(
chn = chn, # compressor channel number (0..3)
run_mode = None, # no change
qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode:
multi_frame = multi_frame, # [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
bayer = bayer, # [20:18] # Bayer shift
focus_mode = focus_mode) # [23:21] Set focus mode
focus_mode = focus_mode, # [23:21] Set focus mode
row_lsb_raw = row_lsb_raw) # [3:0] LSBs of the window height that do not fit into compressor format
self.compressor_format(
chn = chn, # compressor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
......
py393/x393_sens_cmprs.py
View file @ f35c087d
This diff is collapsed.
py393/x393_sensor.py
View file @ f35c087d
......@@ -505,7 +505,7 @@ class X393Sensor(object):
rslt |= 1 << vrlg.VOSPI_OUT_EN_SINGL
if reset_crc:
rslt |= 1 << vrlg.VOSPI_RESET_CRC
if not out_en is None:
if not spi_clk is None:
rslt |= (2,3)[spi_clk] << vrlg.VOSPI_SPI_CLK
if not gpio0 is None:
rslt |= (gpio0 & 3) << (vrlg.VOSPI_GPIO + 0)
......@@ -1042,6 +1042,7 @@ class X393Sensor(object):
# TODO: Make one for HiSPi (it is different)
def set_sensor_io_ctl_lwir (self,
num_sensor,
mrst = None,
pwdn = None,
mclk = None,
......
sensor/sens_lepton3.v
View file @ f35c087d
......@@ -259,7 +259,7 @@ module sens_lepton3 #(
assign fake_out = set_ctrl_r && data_r[VOSPI_FAKE_OUT];
assign spi_mosi_int = set_ctrl_r && data_r[VOSPI_MOSI]; // not used
assign prsts = prst | lwir_mrst_pclk[1];
assign prsts = prst | !lwir_mrst_pclk[1];
always @(posedge mclk) begin
if (mrst) data_r <= 0;
......@@ -346,6 +346,10 @@ module sens_lepton3 #(
// implement I/O ports, including fake ones, to be able to assign them I/O pads
// generate clocka to sesnor output, controlled by control word bits
// SPI clock (10..20MHz)
reg prst_r;
always @ (posedge pclk) begin
prst_r <= prst;
end
oddr_ss #( // spi_clk
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW),
......@@ -353,13 +357,13 @@ module sens_lepton3 #(
.INIT (1'b0),
.SRTYPE ("SYNC")
) spi_clk_i (
.clk (pclk), // input
.ce (spi_clk_en_pclk[1] | spi_clken), // input
.rst (prst), // input
.set (1'b0), // input
.din (2'b01), // input[1:0]
.tin (1'b0), // input
.dq (spi_clk) // output
.clk (pclk), // input
.ce (spi_clk_en_pclk[1] | spi_clken | prst_r), // input
.rst (prst), // input
.set (1'b0), // input
.din (2'b01), // input[1:0]
.tin (1'b0), // input
.dq (spi_clk) // output
);
// sensor master clock (25MHz)
iobuf #( // lwir_mclk
......@@ -430,7 +434,7 @@ module sens_lepton3 #(
generate // gpio[3:0]
genvar i;
for (i=0; i < (VOSPI_GPIO_BITS / 2); i=i+1) begin: gpio_block
gpio_bit gpio_bit_i (
gpio393_bit gpio_bit_i (
.clk (mclk), // input
.srst (mrst), // input
.we (set_ctrl_r), // input
......
sensor/sensor_channel.v
View file @ f35c087d
......@@ -362,8 +362,8 @@ module sensor_channel#(
input sns_clkp,
input sns_clkn,
`elsif LWIR
input [ 4:0] sns_dp40,
input [ 4:0] sns_dn40,
inout [ 4:0] sns_dp40,
inout [ 4:0] sns_dn40,
inout sns_dp5, // diff MIPI signals (not yet implemented)
inout sns_dn5, // diff MIPI signals (not yet implemented)
inout [ 7:6] sns_dp76,
......@@ -1069,12 +1069,12 @@ module sensor_channel#(
// .sns_mclk(), // input
.spi_miso (sns_dp40[0]), // inout
.spi_mosi (sns_dn40[0]), // inout
.spi_cs (sns_dp40[1]), // inout
.spi_clk (sns_dn40[1]), // inout
.spi_cs (sns_dp40[1]), // output
.spi_clk (sns_dn40[1]), // output
.gpio ({sns_dp40[4], sns_dn40[4], sns_dp40[3], sns_dn40[3]}), // inout [3:0]
.lwir_mclk (sns_dp76[6]), // inout
.lwir_mrst (sns_dp76[7]), // inout
.lwir_pwdn (sns_dn76[7]), // inout
.lwir_mclk (sns_dp76[6]), // output
.lwir_mrst (sns_dp76[7]), // output
.lwir_pwdn (sns_dn76[7]), // output
.mipi_dp (sns_dp5), // inout
.mipi_dn (sns_dn5), // inout
.mipi_clkp (sns_clkp), // inout
......
sensor/sensors393.v
View file @ f35c087d
......@@ -398,8 +398,8 @@ module sensors393 #(
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`elsif LWIR
input [19:0] sns_dp40,
input [19:0] sns_dn40,
inout [19:0] sns_dp40,
inout [19:0] sns_dn40,
inout [ 3:0] sns_dp5, // diff MIPI signals (not yet implemented)
inout [ 3:0] sns_dn5, // diff MIPI signals (not yet implemented)
inout [ 7:0] sns_dp76,
......
sensor/vospi_packet_80.v
View file @ f35c087d
......@@ -71,6 +71,7 @@ module vospi_packet_80#(
reg set_crc_r;
reg set_d_r;
reg den_r;
reg [1:0] packet_header = 2'b11;
reg [15:0] d_sr;
reg [ 1:0] start_r;
......@@ -88,7 +89,9 @@ module vospi_packet_80#(
assign pre_last_w = pre_lsb_w && (wcntr == (VOSPI_PACKET_WORDS + 1));
assign packet_done = packet_end[2];
assign id = id_r;
assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff);
// assign dmask = den_r ? 16'hffff: (wcntr[0]?16'h0: 16'h0fff);
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w);
assign dv = dv_r;
assign dout = d_r;
......@@ -96,7 +99,7 @@ module vospi_packet_80#(
always @ (posedge clk) begin
if (rst || packet_end[0]) cs_r[0] <= 0;
else if (start) cs_r[1] <= 1;
else if (start) cs_r[0] <= 1;
cs_r[1] <= cs_r[0];
......@@ -111,8 +114,11 @@ module vospi_packet_80#(
if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0;
else if (lsb_r) wcntr <= wcntr + 1;
if (rst || !cs_r[0] ) packet_end <= 0;
else packet_end <= {packet_end[1:0], pre_last_w};
if (rst || !cs_r[0] ) packet_end[1:0] <= 0;
else packet_end[1:0] <= {packet_end[0], pre_last_w};
if (rst) packet_end[2] <= 0;
else packet_end[2] <= packet_end[1];
if (rst) start_r <= 0;
else start_r <= {start_r[0],start};
......@@ -121,10 +127,11 @@ module vospi_packet_80#(
set_crc_r <= !rst && (wcntr == 1) && lsb_r;
set_d_r <= !rst && den_r && lsb_r;
if (rst || !cs_r[1]) den_r <= 0;
else if (set_crc_r) den_r <= 1;
if (rst || !cs_r[1] || packet_done) den_r <= 0;
else if (set_crc_r) den_r <= 1;
if (cs_r[0]) d_sr <= {miso, d_sr[15:1]};
// if (cs_r[0]) d_sr <= {miso, d_sr[15:1]};
if (cs_r[0]) d_sr <= {d_sr[14:0],miso};
if (set_id_r) id_r <= d_sr;
if (set_crc_r) crc_r <= d_sr;
if (set_d_r) d_r <= d_sr;
......@@ -135,6 +142,9 @@ module vospi_packet_80#(
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
id_stb <= set_id_r;
if (rst || start || packet_done) packet_header <= 2'b11;
else if (copy_word) packet_header <= {packet_header[0], 1'b0};
end
crc16_x16x12x5x0 crc16_x16x12x5x0_i (
......
sensor/vospi_segment_61.v
View file @ f35c087d
......@@ -101,6 +101,8 @@ module vospi_segment_61#(
wire packet_dv; // read full packet
wire [15:0] packet_dout; // read full packet
wire [15:0] packet_id;
wire [ 3:0] segment_id;
wire packet_invalid;
wire id_stb;
wire is_first_segment_w;
wire is_last_segment_w;
......@@ -119,7 +121,9 @@ module vospi_segment_61#(
assign is_first_segment_w = (exp_segment == VOSPI_SEGMENT_FIRST);
assign is_last_segment_w = (exp_segment == VOSPI_SEGMENT_LAST);
assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_id = packet_id[15:12];
// assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_good_w = (segment_id == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT);
assign we = segment_running && !discard_segment_r && packet_dv;
assign crc_err = packet_done && packet_crc_err; // crc_err_r;
......@@ -160,9 +164,9 @@ module vospi_segment_61#(
if (start_d) segment_start_packet <= full_packet;
if (start_d) segment_start_waddr <= waddr;
if (rst || (start && is_first_segment_w)) full_packet <= 0;
else if (discard_set) full_packet <= segment_start_packet;
else if (!discard_segment_r && packet_done) full_packet <= full_packet + 1;
if (rst || (start && is_first_segment_w)) full_packet <= 0;
else if (discard_set) full_packet <= segment_start_packet;
else if (!discard_segment_r && !packet_invalid && packet_done) full_packet <= full_packet + 1;
// if (rst || start) crc_err_r <= 0;
// else if (packet_done && packet_crc_err) crc_err_r <= 0;
......@@ -176,7 +180,8 @@ module vospi_segment_61#(
if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
packet_start <= !rst && !packet_busy && segment_busy_r;
// packet_start <= !rst && !packet_busy && segment_busy_r;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
if (rst) waddr <= 0;
else if (discard_set) waddr <= segment_start_waddr;
......@@ -201,7 +206,11 @@ module vospi_segment_61#(
wire frame_dav;
wire hact_start_w; // (hact will start next cycle
wire hact_end_w;
`ifdef SIMULATION
reg [15:0] duration_cntr;
`else
reg [ 7:0] duration_cntr;
`endif
reg [2:0] hact_r;
reg pend_eof_r;
reg [10:0] raddr;
......@@ -211,13 +220,13 @@ module vospi_segment_61#(
assign start_out_frame_w = segment_good && is_first_segment_w && out_request;
assign packets_avail = {1'b0,full_packet_verified} - {1'b0,full_packet_out} - VOSPI_PACKETS_PER_LINE;
// assign frame_out_done_w = packet_out_done && (full_packet_out == (VOSPI_PACKETS_FRAME - 1));
assign frame_out_done_w = hact_end_w && (full_packet_out == (VOSPI_PACKETS_FRAME - 1));
assign frame_out_done_w = hact_end_w && (full_packet_out == (VOSPI_PACKETS_FRAME - VOSPI_PACKETS_PER_LINE));
assign frame_dav = !packets_avail[8] || out_pending;
assign hact_start_w = out_frame && (duration_cntr == 0) && !hact_r[0] && frame_dav;
assign hact_end_w = (duration_cntr == 0) && hact_r[0];
assign eof_w = out_frame && (duration_cntr == 0) && pend_eof_r;
assign sof_w = rst && start_out_frame_w;
assign sof_w = !rst && start_out_frame_w;
assign hact = hact_r[2];
assign eof = eof_r[2];
assign sof = sof_r;
......@@ -249,7 +258,8 @@ module vospi_segment_61#(
if (rst) pend_eof_r <= 0; // not needed?
else if (frame_out_done_w) pend_eof_r <= 1;
else if (eof_r[0]) pend_eof_r <= 0;
// else if (eof_r[0]) pend_eof_r <= 0;
else if (eof_w) pend_eof_r <= 0;
if (rst) duration_cntr <= 0;
else if (start_out_frame_w) duration_cntr <= VOSPI_SOF_TO_HACT;
......@@ -278,7 +288,7 @@ module vospi_segment_61#(
.packet_busy (packet_busy), // output
.crc_err (packet_crc_err), // output
.id (packet_id), // output[15:0]
.packet_invalid (), // output - not used, processed internally, no dv generated
.packet_invalid (packet_invalid), // output - not used, processed internally, no dv generated
.id_stb (id_stb) // output reg
);
......
util_modules/gpio393.v
View file @ f35c087d
......@@ -161,7 +161,7 @@ module gpio393 #(
generate
genvar i;
for (i=0; i < GPIO_N; i=i+1) begin: gpio_block
gpio_bit gpio_bit_i (
gpio393_bit gpio_bit_i (
// .rst (rst), // input
.clk (mclk), // input
.srst (mrst), // input
......
util_modules/gpio393_bit.v
View file @ f35c087d
/*!
* <b>Module:</b>gpio393
* <b>Module:</b>gpio393_bit
* @file gpio393.v
* @date 2015-07-06
* @author Andrey Filippov
......@@ -48,7 +48,7 @@
// 1 0 2 1 1
// 1 1 3 0 0
module gpio_bit (
module gpio393_bit (
// input rst, // global reset
input clk, // system clock
input srst, // @posedge clk - sync reset
......
x393.v
View file @ f35c087d
......@@ -88,8 +88,8 @@ module x393 #(
inout sns4_ctl,
inout sns4_pg,
`elsif LWIR
input [4:0] sns1_dp40,
input [4:0] sns1_dn40,
inout [4:0] sns1_dp40,
inout [4:0] sns1_dn40,
inout sns1_dp5, // diff MIPI signals (not yet implemented)
inout sns1_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns1_dp76,
......@@ -101,8 +101,8 @@ module x393 #(
inout sns1_ctl,
inout sns1_pg,
input [4:0] sns2_dp40,
input [4:0] sns2_dn40,
inout [4:0] sns2_dp40,
inout [4:0] sns2_dn40,
inout sns2_dp5, // diff MIPI signals (not yet implemented)
inout sns2_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns2_dp76,
......@@ -114,8 +114,8 @@ module x393 #(
inout sns2_ctl,
inout sns2_pg,
input [4:0] sns3_dp40,
input [4:0] sns3_dn40,
inout [4:0] sns3_dp40,
inout [4:0] sns3_dn40,
inout sns3_dp5, // diff MIPI signals (not yet implemented)
inout sns3_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns3_dp76,
......@@ -127,8 +127,8 @@ module x393 #(
inout sns3_ctl,
inout sns3_pg,
input [4:0] sns4_dp40,
input [4:0] sns4_dn40,
inout [4:0] sns4_dp40,
inout [4:0] sns4_dn40,
inout sns4_dp5, // diff MIPI signals (not yet implemented)
inout sns4_dn5, // diff MIPI signals (not yet implemented)
inout [7:6] sns4_dp76,
......
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