simulating/debugging LWIR sensor FPGA code (f35c087d) · Commits · Elphel / x393

cocotb/x393_cocotb_lwir_04.sav

+4025 −231

File changed.

File size exceeds preview limit.

cocotb/x393_dut.v

+4 −6

Original line number	Diff line number	Diff line
		@@ -1746,8 +1746,7 @@ simul_axi_hp_wr #(
		);



		/* Instance template for module simul_lwir160x120_vospi */
		/*
		wire lwir1_miso;
		simul_lwir160x120_vospi #(
		.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
		@@ -1791,7 +1790,7 @@ simul_axi_hp_wr #(
		.telemetry_agc_low ( 16'd200), // input[15:0]
		.telemetry_video_format (32'haaaa5555) // input[31:0]
		);

		*/
		`ifdef LWIR
		simul_lwir160x120_vospi #(
		.DATA_FILE (LWIR_DATA_FILE1),
		@@ -1967,9 +1966,7 @@ simul_axi_hp_wr #(



		`endif


		`else


		simul_sensor12bits #(
		@@ -2133,6 +2130,7 @@ simul_axi_hp_wr #(
		.VACT (PX4_VACT), // output
		.VACT1 () // output
		);
		`endif
		/*
		sim_soc_interrupts #(
		.NUM_INTERRUPTS (NUM_INTERRUPTS)

compressor_jp/cmprs_cmd_decode.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -318,7 +318,7 @@ module cmprs_cmd_decode#(
		if (mrst) cmprs_fmode_mclk <= 0;
		else if (ctrl_we_r && di_r[CMPRS_CBIT_FOCUS]) cmprs_fmode_mclk <= di_r[CMPRS_CBIT_FOCUS-1 -:CMPRS_CBIT_FOCUS_BITS];

		if (mrst) rows_lsb_mclk <= 4'h0f;
		if (mrst) rows_lsb_mclk <= 4'hf;
		else if (ctrl_we_r && di_r[CMPRS_CBIT_ROWS_LSB]) rows_lsb_mclk <= di_r[CMPRS_CBIT_ROWS_LSB-1 -:CMPRS_CBIT_ROWS_LSB_BITS];

		if (mrst) bayer_shift_mclk <= 0;

compressor_jp/jp_channel.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -247,7 +247,7 @@ module jp_channel#(
		wire jp4_dc_improved; // in JP4 mode, compare DC coefficients to the same color ones
		// wire [ 1:0] tile_margin; // margins around 16x16 tiles (0/1/2)
		// wire [ 2:0] tile_shift; // tile shift from top left corner
		wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)
		wire [ 2:0] converter_type; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 6 - raw, 7 - mono8 (not yet implemented)
		wire scale_diff; // divide differences by 2 (to fit in 8-bit range)
		wire hdr; // second green absolute, not difference
		wire subtract_dc; // subtract/restore DC components

includes/x393_parameters.vh

+23 −4

Original line number	Diff line number	Diff line
		@@ -305,8 +305,16 @@
		parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)

		parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse

		`ifdef SIMULATION
		`ifdef LWIR
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 100, // initial delay value for start pulse
		`else
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
		`endif
		`else
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
		`endif
		// Channel test module parameters
		parameter MCNTRL_TEST01_ADDR= 'h0f0,
		parameter MCNTRL_TEST01_MASK= 'h7f0,
		@@ -566,8 +574,13 @@
		parameter VOSPI_PACKET_FIRST = 0,
		parameter VOSPI_PACKET_LAST = 60,
		parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
		parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
		`ifdef SIMULATION
		parameter VOSPI_SOF_TO_HACT = 1000, // clock cycles from SOF to HACT
		parameter VOSPI_HACT_TO_HACT_EOF = 1000, // pixel clock is 480 MHz, need to slow down for memory
		`else
		parameter VOSPI_SOF_TO_HACT = 10, // clock cycles from SOF to HACT
		parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
		`endif
		parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
		//`else
		//sensor_fifo parameters (for parallel12)
		@@ -1000,8 +1013,14 @@
		parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
		parameter DIVCLK_DIVIDE_PCLK = 1,
		parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
		`ifdef SIMULATION
		parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
		parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
		`else
		parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
		parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
		`endif

		`else
		parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
		parameter DIVCLK_DIVIDE_PCLK = 1,

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