debugging hardware

[*]

[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI

[*] Tue Jun 10 23:54:44 2014

[*] Wed Jun 11 02:38:51 2014

[*]

[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140610170704485.lxt"

[dumpfile_mtime] "Tue Jun 10 23:11:05 2014"

[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140610175433027.lxt"

[dumpfile_mtime] "Tue Jun 10 23:58:40 2014"

[dumpfile_size] 75451369

[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"

[timestart] 137157300

[timestart] 138628110

[size] 1920 1180

[pos] -1 -1

*-15.445735 137359375 134765625 134912600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-12.445735 138646045 134765625 134912600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] ddrc_test01_testbench.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].

[treeopen] ddrc_test01_testbench.simul_axi_master_rdaddr_i.

[treeopen] ddrc_test01_testbench.simul_axi_master_wdata_i.

[treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i.

[sst_width] 219

[sst_width] 302

[signals_width] 367

[sst_expanded] 1

[sst_vpaned_height] 820

[sst_vpaned_height] 694

@c00200

-PS7_AXI

@22

-ddrc_sequencer

@800200

-ddr_sequencer_i_selected

@800201

-ddr_read_data

@29

ddrc_test01_testbench.DQSL[0]

@23

ddrc_test01_testbench.SDD[15:0]

@29

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_di[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_dly[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]

@23

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dout[31:0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dout[63:0]

@1000201

-ddr_read_data

@200

-

@c00200

-tristate_control

@28

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wr[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wr_negedge[0]

@29

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0]

@22

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_addr[9:0]

ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.in_count[31:0]

@28

ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.input_ready[0]

@22

ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.latency_delay[5:0]

ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.latency_delay_r[4:0]

@28

ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.load[0]

@22

ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_address[31:0]

// Set special values for DQS idelay for write leveling

    axi_set_dqs_idelay_wlv;

// Set write buffer (from DDR3) WE signal delay for write leveling mode

    axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_WLV});

//    axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_WLV});

    axi_set_wbuf_delay(WBUF_DLY_WLV);

//axi_set_dqs_idelay_nominal;

    run_write_lev;

// restore normal dqs idelay (after write leveling)

    axi_set_dqs_idelay_nominal;

// restore normal write buffer (from DDR3) WE signal delay

    axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_DFLT});

//    axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_DFLT});

    axi_set_wbuf_delay(WBUF_DLY_DFLT);

// test reading pattern       

//    set_read_pattern(8); // 8x2*64 bits, 32x32 bits to read

            target_phase <= phase;

        end

    endtask

    task axi_set_wbuf_delay;

        input [3:0] delay;

        begin

            $display("SET WBUF DELAY to 0x%x @ %t",delay,$time);

            axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, delay});

        end

    endtask

/*

    assign rdata={21'b0,run_busy,locked,ps_rdy,ps_out[7:0]};

*/    

    task wait_phase_shifter_ready;

  # Set MR3, read nrep*8 words, save to buffer (port0). No ACTIVATE/PRECHARGE are needed/allowed

def set_read_pattern( #    task set_read_pattern;

        nrep): # input integer nrep;

        nrep, # input integer nrep;

        npat):#trying pattern type (only 0 defined)

#        reg   [31:0] cmd_addr;

#        reg   [31:0] data;

#        reg                 [17:0] mr3_norm;

                0) # 2'h0)    # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...

    mr3_pattern = ddr3_mr3 (

                1, # 1'h1,     #       mpr;    # MPR mode: 0 - normal, 1 - dataflow from MPR

                0) # 2'h0)    # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...

                npat & 3) # 2'h0)    # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...

# Set pattern mode

    data =  encode_seq_word(

            ((0 &     0x1) <<  6) | # phy_dqs_en_in #phy_dqs_tri_in,  # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)

            ((0 &     0x1) <<  5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern

            (( 1 &    0x1) <<  4) | # phy_dci_en_in  #phy_dci_in,      # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)

            (( 1 &    0x1) <<  3) | # phy_buf_wr # connect to external buffer (but only if not paused)

#            (( 1 &    0x1) <<  3) | # phy_buf_wr # connect to external buffer (but only if not paused)

            ((0 &    0x1) <<  3) | # phy_buf_wr # connect to external buffer (but only if not paused)

            ((0 &     0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

            ((0 &     0x1) <<  1))  # add_nop    # add NOP after the current command, keep other data

    axi_write_single(cmd_addr, data)

    axi_write_single(cmd_addr, data)

    cmd_addr = cmd_addr + 4

# see if pause is needed . See when buffer read should be started - maybe before WR command

    data = encode_seq_skip(1,0,0,0) # tRCD

#    data = encode_seq_skip(1,0,0,0) # tRCD

    data = encode_seq_skip(2,0,0,0) # tRCD

    axi_write_single(cmd_addr, data)

    cmd_addr = cmd_addr + 4

# first write

            ((0x3 &   0x7) << 11) | # 3'b011, # phy_rcw_in[2:0],      # {ras,cas,we}

            (( 1 &    0x1) << 10) | # phy_odt_in

            ((0 &     0x1) <<  9) | # phy_cke_inv   # invert CKE

            (( 1 &    0x1) <<  8) | # phy_sel_in   # first/second half-cycle, other will be nop (cke+odt applicable to both)

#            (( 1 &    0x1) <<  8) | # phy_sel_in   # first/second half-cycle, other will be nop (cke+odt applicable to both)

            ((0  &    0x1) <<  8) | # phy_sel_in   # first/second half-cycle, other will be nop (cke+odt applicable to both)

            ((0 &     0x1) <<  7) | # phy_dq_en_in #phy_dq_tri_in,   # tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)

            ((0 &     0x1) <<  6) | # phy_dqs_en_in #phy_dqs_tri_in,  # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)

            ((0 &     0x1) <<  5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern

            ((0 &     0x1) <<  4) | # phy_dci_en_in  #phy_dci_in,      # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)

            ((0 &     0x1) <<  3) | # phy_buf_wr # connect to external buffer (but only if not paused)

            ((0 &     0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

#            ((0 &     0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

            (( 1 &     0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

            ((0 &     0x1) <<  1))  # add_nop    # add NOP after the current command, keep other data

    axi_write_single(cmd_addr, data)

    cmd_addr = cmd_addr + 4

                ((0x3 &   0x7) << 11) | # 3'b011, # phy_rcw_in[2:0],      # {ras,cas,we}

                (( 1 &    0x1) << 10) | # phy_odt_in

                ((0 &     0x1) <<  9) | # phy_cke_inv   # invert CKE

                (( 1 &    0x1) <<  8) | # phy_sel_in   # first/second half-cycle, other will be nop (cke+odt applicable to both)

#                (( 1 &    0x1) <<  8) | # phy_sel_in   # first/second half-cycle, other will be nop (cke+odt applicable to both)

                (( 0 &    0x1) <<  8) | # phy_sel_in   # first/second half-cycle, other will be nop (cke+odt applicable to both)

                (( 1 &    0x1) <<  7) | # phy_dq_en_in #phy_dq_tri_in,   # tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)

                (( 1 &    0x1) <<  6) | # phy_dqs_en_in #phy_dqs_tri_in,  # tristate DQS lines (internal timing sequencer for 0->1 and 1->0)

                (( 1 &    0x1) <<  5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern

            (( 1 &    0x1) <<  5) | # phy_dqs_toggle_en #enable toggle DQS according to the pattern

            ((0 &     0x1) <<  4) | # phy_dci_en_in  #phy_dci_in,      # DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)

            ((0 &     0x1) <<  3) | # phy_buf_wr # connect to external buffer (but only if not paused)

            (( 1 &    0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

#            (( 1 &    0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

            (( 0 &    0x1) <<  2) | # phy_buf_rd # connect to external buffer (but only if not paused)

            ((0 &     0x1) <<  1))  # add_nop    # add NOP after the current command, keep other data

    axi_write_single(cmd_addr, data)

    cmd_addr = cmd_addr + 4

#   target_phase <= phase;

def axi_set_wbuf_delay(#    task axi_set_wbuf_delay;

        delay): #input [3:0] delay;

    global BASEADDR_WBUF_DELAY

    print("SET WBUF DELAY to 0x%x"%delay);

    axi_write_single(BASEADDR_WBUF_DELAY, delay);

def set_all_sequences(): #    task set_all_sequences;

    print("SET MRS")    

    set_mrs(1)

    print("SET WRITE LEVELING")    

    set_write_lev(16) # write leveling, 16 times   (full buffer - 128) 

    print("SET READ PATTERN")    

    set_read_pattern(8) # 8x2*64 bits, 32x32 bits to read

    set_read_pattern(8,0) # 8x2*64 bits, 32x32 bits to read (second 0 - pattern type, only 0 defined)

    print("SET WRITE BLOCK")    

    set_write_block(

                5,      # 3'h5,     # bank

            )

def set_up(): #    task set_up;

    global DLY_DQ_IDELAY,DLY_DQ_ODELAY,DLY_DQS_IDELAY,DLY_DQS_ODELAY,DLY_DM_ODELAY,DLY_CMDA_ODELAY

    global DLY_DQ_IDELAY,DLY_DQ_ODELAY,DLY_DQS_IDELAY,DLY_DQS_ODELAY,DLY_DM_ODELAY,DLY_CMDA_ODELAY,WBUF_DLY_DFLT,DLY_PHASE

# set dq /dqs tristate on/off patterns

    axi_set_tristate_patterns()

# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)

            #axi_set_delays;

#    set clock phase relative to DDR clk

    axi_set_phase(DLY_PHASE)

    axi_set_wbuf_delay(WBUF_DLY_DFLT)

# main

if len(sys.argv)<2:

    print ("Usage: %s command [hex_parameter, ...]"%sys.argv[0])

    read_buf(args[0])

    print("read_buf() OK")

elif command=="set_read_pattern":

    check_args(1,command,args)

    set_read_pattern(args[0])

    check_args(2,command,args)

    set_read_pattern(args[0],args[1])

    print("set_read_pattern(0x%x) OK"%(args[0]))

elif command=="set_read_block":

    check_args(3,command,args)

    axi_set_phase(args[0])

    print("axi_set_phase(0x%x) OK"%(args[0]))

elif command=="axi_set_wbuf_delay":

    check_args(1,command,args)

    axi_set_wbuf_delay(args[0])

    print("axi_set_wbuf_delay(0x%x) OK"%(args[0]))

elif command=="set_write_lev":

    check_args(1,command,args)

    set_write_lev(args[0])