Commit ed32ff53 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

hardware debugging/testing

parent 09a3a7cd

.project

+14 −14
Original line number Diff line number Diff line
@@ -62,42 +62,42 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150831151630695.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,32 +107,32 @@ 
		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150831152219741.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150831151630695.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150903211518672.log</location>

		</link>

		<link>

			<name>vivado_state/x393-opt-phys.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150831152219741.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150903211518672.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-place.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150831152219741.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-place-20150903211518672.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-route.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150831152219741.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-route-20150903211518672.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150831151630695.dcp</location>

			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150903211518672.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

compressor_jp/compressor393.v

+9 −0
Original line number Diff line number Diff line
@@ -111,6 +111,9 @@ module compressor393 # ( 
        parameter CMPRS_AFIMUX_WIDTH =         26, // maximal for status: currently only works with 26)

        parameter CMPRS_AFIMUX_CYCBITS =        3,

        parameter AFI_MUX_BUF_LATENCY =      4'd2  // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used

`ifdef DEBUG_RING

        ,parameter DEBUG_CMD_LATENCY = 2 

`endif        



)(

//    input                         rst,    // global reset
@@ -231,6 +234,12 @@ module compressor393 # ( 
    input                  [ 7:0] afi1_wcount,

    input                  [ 5:0] afi1_wacount,

    output                        afi1_wrissuecap1en

`ifdef DEBUG_RING       

    ,output                       debug_do, // output to the debug ring

     input                        debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load

     input                        debug_di  // input from the debug ring

`endif         

    

);



    wire   [47:0] status_ad_mux;

fpga_version.vh

+1 −1
Original line number Diff line number Diff line 
    parameter FPGA_VERSION =          32'h03930003;
 
    parameter FPGA_VERSION =          32'h0393000f;
 
 No newline at end of file

includes/x393_parameters.vh

+12 −0
Original line number Diff line number Diff line
@@ -724,6 +724,18 @@ 
    parameter CLK_CNTRL =                 0,

    parameter CLK_STATUS =                1,



`ifdef DEBUG_RING

// Debug module (read/write serial ring)

    parameter DEBUG_ADDR =                'h710, //..'h713

    parameter DEBUG_MASK =                'h7fc,

    parameter DEBUG_STATUS_REG_ADDR =     'hfc,  // address where status can be read out 

    parameter DEBUG_READ_REG_ADDR =       'hfd,  // read 32-bit received shifted data

    parameter DEBUG_SHIFT_DATA =          'h0,   // shift i/o data by 32 bits

    parameter DEBUG_LOAD =                'h1,   // parallel load of the distributed shift registe (both ways)

    parameter DEBUG_SET_STATUS =          'h2,    // program status (mode 3?)

    parameter DEBUG_CMD_LATENCY =          2, // >0 extra registers in the debug_sl (distriburted in parallel)

`endif

    

    parameter CLKIN_PERIOD_AXIHP =        20, //ns >1.25, 600<Fvco<1200

    parameter DIVCLK_DIVIDE_AXIHP =       1,

    parameter CLKFBOUT_MULT_AXIHP =       18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE

py393/x393_camsync.py

+7 −4
Original line number Diff line number Diff line
@@ -157,14 +157,15 @@ class X393Camsync(object): 
        @param delay -              delay value in 10 ns steps - max 42.95 sec (or list/tuple if different for channels)

        """

        self.set_camsync_period  (0) # reset circuitry

        self.set_gpio_ports (port_a = True)

        self.X393_gpio.set_gpio_ports (port_a = True)

        self.set_camsync_mode (

                               en = True,

                               snd_en = True,

                               en_snd = True,

                               en_ts_external = external_timestamp,

                               triggered_mode = trigger_mode,

                               master_chn =     0,

                               chn_en = sensor_mask)

        

        # setting I/Os after camsync is enabled

        self.reset_camsync_inout (is_out = 0)        # reset input selection

        if ext_trigger_mode :
@@ -180,6 +181,8 @@ class X393Camsync(object): 
        if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):

            camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)

        for i, dly in enumerate (camsync_delay): 

            if not dly is None:

                self.set_camsync_delay(sub_chn = i, delay = dly)



        if not camsync_period is None:

            self.set_camsync_period  (period = camsync_period) # set period (start generating) - in 353 was after everything else was set