Commit ed32ff53 authored by Andrey Filippov's avatar Andrey Filippov

hardware debugging/testing

parent 09a3a7cd
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150831151630695.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,32 +107,32 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150831151630695.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150903211518672.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150831152219741.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150903211518672.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150831152219741.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150903211518672.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150831152219741.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150903211518672.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150831151630695.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150903211518672.dcp</location>
</link>
</linkedResources>
</projectDescription>
......@@ -111,6 +111,9 @@ module compressor393 # (
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
)(
// input rst, // global reset
......@@ -231,6 +234,12 @@ module compressor393 # (
input [ 7:0] afi1_wcount,
input [ 5:0] afi1_wacount,
output afi1_wrissuecap1en
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
input debug_di // input from the debug ring
`endif
);
wire [47:0] status_ad_mux;
......
parameter FPGA_VERSION = 32'h03930003;
parameter FPGA_VERSION = 32'h0393000f;
\ No newline at end of file
......@@ -723,6 +723,18 @@
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
`ifdef DEBUG_RING
// Debug module (read/write serial ring)
parameter DEBUG_ADDR = 'h710, //..'h713
parameter DEBUG_MASK = 'h7fc,
parameter DEBUG_STATUS_REG_ADDR = 'hfc, // address where status can be read out
parameter DEBUG_READ_REG_ADDR = 'hfd, // read 32-bit received shifted data
parameter DEBUG_SHIFT_DATA = 'h0, // shift i/o data by 32 bits
parameter DEBUG_LOAD = 'h1, // parallel load of the distributed shift registe (both ways)
parameter DEBUG_SET_STATUS = 'h2, // program status (mode 3?)
parameter DEBUG_CMD_LATENCY = 2, // >0 extra registers in the debug_sl (distriburted in parallel)
`endif
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1,
......
......@@ -157,14 +157,15 @@ class X393Camsync(object):
@param delay - delay value in 10 ns steps - max 42.95 sec (or list/tuple if different for channels)
"""
self.set_camsync_period (0) # reset circuitry
self.set_gpio_ports (port_a = True)
self.X393_gpio.set_gpio_ports (port_a = True)
self.set_camsync_mode (
en = True,
snd_en = True,
en_snd = True,
en_ts_external = external_timestamp,
triggered_mode = trigger_mode,
master_chn = 0,
chn_en = sensor_mask)
# setting I/Os after camsync is enabled
self.reset_camsync_inout (is_out = 0) # reset input selection
if ext_trigger_mode :
......@@ -179,7 +180,9 @@ class X393Camsync(object):
self.set_camsync_period (SYNC_BIT_LENGTH) #set (bit_length -1) (should be 2..255), not the period
if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):
camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)
for i, dly in enumerate (camsync_delay):
for i, dly in enumerate (camsync_delay):
if not dly is None:
self.set_camsync_delay(sub_chn = i, delay = dly)
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
if not camsync_period is None:
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
......@@ -390,7 +390,7 @@ class X393Cmprs(object):
print ( "bayer = ",bayer)
print ( "focus_mode = ",focus_mode)
self.compressor_control(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode:
......@@ -399,18 +399,18 @@ class X393Cmprs(object):
focus_mode = focus_mode) # [23:21] Set focus mode
self.compressor_format(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1
left_margin = left_margin) # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
self.compressor_color_saturation(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100%
colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100%
self.compressor_coring(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
coring = coring); # coring value
......@@ -44,8 +44,10 @@ import x393_rtc
import x393_utils
#import time
import time
import vrlg
PAGE_SIZE = 4096
SI5338_PATH = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
......@@ -154,9 +156,8 @@ class X393SensCmprs(object):
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 0,
histogram_height_m1 = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 1935, #0,
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -215,22 +216,25 @@ class X393SensCmprs(object):
frame_start_address = (last_buf_frame + 1) * frame_start_address_inc * num_sensor
# histogram_start_phys_page - system memory 4K page number to start histogram
histogram_start_phys_page = self.get_histogram_byte_start() // 4096
histogram_start_phys_page = self.get_histogram_byte_start() // 4096
if verbose >0 :
print ("setup_sensor_channel:")
print ("num_sensor = ", num_sensor)
print ("frame_full_width = ", frame_full_width)
print ("window_width = ", window_width)
print ("window_height = ", window_height)
print ("window_left = ", window_left)
print ("window_top = ", window_top)
print ("frame_start_address = ", frame_start_address)
print ("frame_start_address_inc = ", frame_start_address_inc)
print ("last_buf_frame = ", last_buf_frame)
print ("num_macro_cols_m1 = ", num_macro_cols_m1)
print ("num_macro_rows_m1 = ", num_macro_rows_m1)
print ("verbose = ", verbose)
print ("num_sensor = ", num_sensor)
print ("frame_full_width = ", frame_full_width)
print ("window_width = ", window_width)
print ("window_height = ", window_height)
print ("window_left = ", window_left)
print ("window_top = ", window_top)
print ("frame_start_address = 0x%x"%(frame_start_address))
print ("frame_start_address_inc = 0x%x"%(frame_start_address_inc))
print ("histogram_start_phys_page = 0x%x"%(histogram_start_phys_page))
print ("histogram start address = 0x%x"%(histogram_start_phys_page * 4096))
print ("last_buf_frame = ", last_buf_frame)
print ("num_macro_cols_m1 = ", num_macro_cols_m1)
print ("num_macro_rows_m1 = ", num_macro_rows_m1)
print ("verbose = ", verbose)
if exit_step == 10: return False
self.x393Sensor.program_status_sensor_i2c(
......@@ -243,7 +247,7 @@ class X393SensCmprs(object):
seq_num = 0); # input [5:0] seq_num;
self.x393Cmprs.program_status_compressor(
num_sensor = num_sensor, # input [1:0] num_sensor;
cmprs_chn = num_sensor, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
if exit_step == 11: return False
......@@ -307,7 +311,7 @@ class X393SensCmprs(object):
if exit_step == 15: return False
self.x393Cmprs.compressor_control(
num_sensor = num_sensor,
chn = num_sensor,
run_mode = 3) # run repetitive mode
if exit_step == 16: return False
......@@ -357,8 +361,8 @@ class X393SensCmprs(object):
self.x393Sensor.test_i2c_353() # test soft/sequencer i2c
"""
if verbose >0 :
print ("===================== LENS_FLAT_SETUP =========================")
self.x393Sensor.set_sensor_lens_flat_heights (self,
print ("===================== LENS_FLAT_SETUP ========================= num_sensor=",num_sensor)
self.x393Sensor.set_sensor_lens_flat_heights (
num_sensor = num_sensor,
height0_m1 = 0xffff,
height1_m1 = None,
......@@ -381,7 +385,7 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== GAMMA_SETUP =========================")
self.x393Sensor.set_sensor_gamma_heights (self,
self.x393Sensor.set_sensor_gamma_heights (
num_sensor = num_sensor,
height0_m1 = 0xffff,
height1_m1 = 0,
......@@ -392,7 +396,7 @@ class X393SensCmprs(object):
print ("===================== HISTOGRAMS_SETUP =========================")
self.x393Sensor.set_sensor_histogram_window ( # 353 did it using command sequencer)
num_sensor = num_sensor,
num_sub_sensor = 0,
subchannel = 0,
left = histogram_left,
top = histogram_top,
width_m1 = histogram_width_m1,
......@@ -458,9 +462,9 @@ class X393SensCmprs(object):
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 0,
histogram_height_m1 = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 799, #0,
circbuf_chn_size= 0x1000000, #16777216
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -496,9 +500,35 @@ class X393SensCmprs(object):
@param histogram_top - histogram window top margin
@param histogram_width_m1 - one less than window width. If 0 - use frame right margin (end of HACT)
@param histogram_height_m1 - one less than window height. If 0 - use frame bottom margin (end of VACT)
@param circbuf_chn_size - circular buffer size for each channel, in bytes
@parame verbose - verbose level
@return True if all done, False if exited prematurely by exit_step
"""
# camsync_setup (
# 4'hf ); # sensor_mask); #
circbuf_start = self.get_circbuf_byte_start()
mem_end= self.get_circbuf_byte_end()
#circbuf_chn_size
circbuf_starts=[]
for i in range(16):
circbuf_starts.append(circbuf_start + i*circbuf_chn_size)
circbuf_end = circbuf_start + 4*circbuf_chn_size
#TODO: calculate addersses/lengths
afi_cmprs0_sa = circbuf_starts[0] // 4
afi_cmprs1_sa = circbuf_starts[1] // 4
afi_cmprs2_sa = circbuf_starts[2] // 4
afi_cmprs3_sa = circbuf_starts[3] // 4
afi_cmprs_len = circbuf_chn_size // 4
if verbose >0 :
print ("compressor system memory buffers:")
print ("circbuf start 0 = 0x%x"%(circbuf_starts[0]))
print ("circbuf start 1 = 0x%x"%(circbuf_starts[1]))
print ("circbuf start 2 = 0x%x"%(circbuf_starts[2]))
print ("circbuf start 3 = 0x%x"%(circbuf_starts[3]))
print ("circbuf end = 0x%x"%(circbuf_end))
print ("memory buffer end = 0x%x"%(mem_end))
if sensor_mask & 3: # Need mower for sesns1 and sens 2
if verbose >0 :
print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
......@@ -528,14 +558,6 @@ class X393SensCmprs(object):
self.x393Rtc.set_rtc () # no correction, use current system time
if exit_step == 3: return False
# camsync_setup (
# 4'hf ); # sensor_mask); #
#TODO: calculate addersses/lengths
afi_cmprs0_sa = 0
afi_cmprs1_sa = 0
afi_cmprs2_sa = 0
afi_cmprs3_sa = 0
afi_cmprs_len = 0
for num_sensor in range(4):
if sensor_mask & (1 << num_sensor):
......@@ -583,6 +605,67 @@ class X393SensCmprs(object):
afi_cmprs2_len = afi_cmprs_len,
afi_cmprs3_sa = afi_cmprs3_sa,
afi_cmprs3_len = afi_cmprs_len)
if exit_step == 21: return False
self.x393Sensor.print_status_sensor_io (num_sensor = num_sensor)
self.x393Sensor.print_status_sensor_i2c (num_sensor = num_sensor)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = True)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
num_bytes = 3,
dly = 100, # ??None,
scl_ctl = None,
sda_ctl = None)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = False)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
run_cmd = True)
if exit_step == 21: return False
self.x393_camsync_setup ( sensor_mask = sensor_mask ) # sensor_mask); #
self.x393Camsync.camsync_setup (
sensor_mask = sensor_mask,
trigger_mode = False, #False - async (free running) sensor mode, True - triggered (global reset) sensor mode
ext_trigger_mode = False, # True - external trigger source, 0 - local FPGA trigger source
external_timestamp = False, # True - use received timestamp in the image file, False - use local timestamp
camsync_period = None,
camsync_delay = None)
def print_status_sensor(self,
restart = False,
chn = None):
"""
Decode and print channel-related status
@param restart - reset "alive" bits, wait 1 second, read status
@param chn - channel numberr or None - in that case print it for all channels
"""
if chn is None:
sensors=range(4)
else:
sensors = [chn]
if restart:
for chn in sensors:
self.x393Sensor.program_status_sensor_i2c(
num_sensor = chn, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
self.x393Sensor.program_status_sensor_io(
num_sensor = chn, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
self.x393Cmprs.program_status_compressor(
cmprs_chn = chn, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
time.sleep(1)
for chn in sensors:
self.x393Sensor.print_status_sensor_io (num_sensor = chn)
self.x393Sensor.print_status_sensor_i2c (num_sensor = chn)
......@@ -97,6 +97,72 @@ class X393Sensor(object):
vrlg.SENSIO_STATUS,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def get_status_sensor_io ( self,
num_sensor):
"""
Read sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
@return sesnor_io status
"""
return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL))
def print_status_sensor_io (self,
num_sensor):
"""
Print sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
"""
status= self.get_status_sensor_io(num_sensor)
print ("print_status_sensor_io(%d):"%(num_sensor))
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
print (" last_in_line_1cyc_mclk = %d"%((status>>23) & 1))
print (" dout_valid_1cyc_mclk = %d"%((status>>22) & 1))
print (" alive_hist0_gr = %d"%((status>>21) & 1))
print (" alive_hist0_rq = %d"%((status>>20) & 1))
print (" sof_out_mclk = %d"%((status>>19) & 1))
print (" eof_mclk = %d"%((status>>18) & 1))
print (" sof_mclk = %d"%((status>>17) & 1))
print (" sol_mclk = %d"%((status>>16) & 1))
print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" ps_rdy = %d"%((status>> 9) & 1))
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" xfpgatdo = %d"%((status>>25) & 1))
print (" senspgmin = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
#vact_alive, hact_ext_alive, hact_alive
def get_status_sensor_i2c ( self,
num_sensor):
"""
Read sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
@return sesnor_io status
"""
return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL))
def print_status_sensor_i2c (self,
num_sensor):
"""
Print sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
"""
status= self.get_status_sensor_i2c(num_sensor)
print ("print_status_sensor_i2c(%d):"%(num_sensor))
print (" reset_on = %d"%((status>> 7) & 1))
print (" req_clr = %d"%((status>> 6) & 1))
print (" alive_fs = %d"%((status>> 5) & 1))
print (" busy = %d"%((status>> 4) & 1))
print (" frame_num = %d"%((status>> 0) & 0xf))
print (" sda_in = %d"%((status>>25) & 1))
print (" scl_in = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
# Functions used by sensor-related tasks
def func_sensor_mode (self,
......@@ -497,7 +563,7 @@ class X393Sensor(object):
@param fatzero_out (16 bits)
@param post_scale (4 bits) - shift of the result
"""
def func_lens_data (self,
def func_lens_data (
num_sensor,
addr,
data,
......@@ -653,8 +719,17 @@ class X393Sensor(object):
"""
raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3]
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_LEFT_TOP, ((top & 0xffff) << 16) | (left & 0xff))
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_WIDTH_HEIGHT, ((height_m1 & 0xffff) << 16) | (width_m1 & 0xff))
if self.DEBUG_MODE:
print("set_sensor_histogram_window():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
print("left = ", left)
print("top = ", top)
print("width_m1 = ", width_m1)
print("height_m1 = ", height_m1)
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_LEFT_TOP, ((top & 0xffff) << 16) | (left & 0xffff))
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_WIDTH_HEIGHT, ((height_m1 & 0xffff) << 16) | (width_m1 & 0xffff))
def set_sensor_histogram_saxi (self,
en,
nrst,
......@@ -667,6 +742,12 @@ class X393Sensor(object):
@param confirm_write - wait for the write confirmed (over B channel) before switching channels
@param cache_mode AXI cache mode, default should be 4'h3
"""
if self.DEBUG_MODE:
print("set_sensor_histogram_saxi():")
print("en = ", en)
print("nrst = ", nrst)
print("confirm_write = ", confirm_write)
print("cache_mode= ", cache_mode)
data = 0;
data |= (0,1)[en] << vrlg.HIST_SAXI_EN
data |= (0,1)[nrst] << vrlg.HIST_SAXI_NRESET
......@@ -684,6 +765,11 @@ class X393Sensor(object):
@param num_sub_sensor - sub-sensor attached to the same port through multiplexer (0..3)
@param page - system memory page address (in 4KB units)
"""
if self.DEBUG_MODE:
print("set_sensor_histogram_saxi_addr():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
print("page = ", page)
channel = ((num_sensor & 3) << 2) + (subchannel & 3)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,page)
......
......@@ -35,6 +35,7 @@ module sens_histogram #(
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x,
input sof,
input eof,
input hact,
input [7:0] hist_di, // 8-bit pixel data
......@@ -48,6 +49,7 @@ module sens_histogram #(
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware
,output debug_mclk
);
localparam PXD_2X_LATENCY = 2;
reg hist_bank_pclk;
......@@ -101,7 +103,7 @@ module sens_histogram #(
reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle
wire hist_done_mclk;
reg vert_woi; // vertically in window
reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window
reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
reg hor_woi; // vertically in window
......@@ -123,6 +125,8 @@ module sens_histogram #(
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
reg debug_vert_woi_r;
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
......@@ -135,7 +139,7 @@ module sens_histogram #(
assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en;
//AF2015-new mod
wire line_start_w = hact && !hact_d[0];
wire line_start_w = hact && !hact_d[0]; // // tested active
reg pre_first_line;
reg frame_active; // until done
reg hist_en_pclk2x;
......@@ -157,6 +161,9 @@ module sens_histogram #(
reg monochrome_pclk;
reg monochrome_2x;
// assign debug_mclk = hist_done_mclk;
// assign debug_mclk = set_width_height_w;
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
else pxd_wa <= pxd_wa + 1;
......@@ -196,7 +203,10 @@ module sens_histogram #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vcntr_zero_w && vert_woi && line_start_w;
debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;
// hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0;
else if (sof && en_new) frame_active <= 1;
......@@ -338,6 +348,17 @@ module sens_histogram #(
end
pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (vert_woi && !debug_vert_woi_r), // line_start_w), // input vcntr_zero_w
// .in_pulse (vcntr_zero_w && !debug_vert_woi_r), // line_start_w), // input
.in_pulse (vcntr_zero_w && vert_woi && !debug_vert_woi_r), // line_start_w), // input
.out_pulse (debug_mclk), // output
.busy() // output
);
cmd_deser #(
.ADDR (HISTOGRAM_ADDR),
......
......@@ -75,8 +75,8 @@ module sens_parallel12 #(
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STATUS_ALIVE_WIDTH = 4
)(
// input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
......@@ -103,7 +103,9 @@ module sens_parallel12 #(
// output
output reg [11:0] pxd_out,
output reg vact_out,
output hact_out,
output hact_out,
input [STATUS_ALIVE_WIDTH-1:0] status_alive_1cyc, //extra toggle @mclk bits to report with status
// JTAG to program 10359
// input xpgmen, // enable programming mode for external FPGA
......@@ -171,7 +173,7 @@ module sens_parallel12 #(
wire [14:0] status;
wire [17:0] status;
wire cmd_we;
wire [2:0] cmd_a;
......@@ -188,10 +190,24 @@ module sens_parallel12 #(
reg xfpgatdi=0; // TDI to be sent to external FPGA
wire hact_ext; // received hact signal
reg hact_ext_r; // received hact signal, delayed by 1 clock
reg hact_r; // received or regenerated hact
reg hact_r; // received or regenerated hact
// for debug/test alive
reg vact_r;
reg hact_r2;
wire vact_a_mclk;
wire hact_ext_a_mclk;
wire hact_a_mclk;
reg vact_alive;
reg hact_ext_alive;
reg hact_alive;
reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3];
assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin};
assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
assign hact_out = hact_r;
assign iaro = trigger_mode? ~trig : iaro_soft;
......@@ -285,8 +301,28 @@ module sens_parallel12 #(
pxd_out <= pxd_out_pre;
vact_out <= vact_out_pre;
// for debug/test alive
vact_r <= vact_out_pre;
hact_r2 <= hact_r;
end
// for debug/test alive
always @(posedge mclk) begin
if (mclk_rst || set_status_r) vact_alive <= 0;
else if (vact_a_mclk) vact_alive <= 1;
if (mclk_rst || set_status_r) hact_ext_alive <= 0;
else if (hact_ext_a_mclk) hact_ext_alive <= 1;
if (mclk_rst || set_status_r) hact_alive <= 0;
else if (hact_a_mclk) hact_alive <= 1;
if (mclk_rst || set_status_r) status_alive <= 0;
else status_alive <= status_alive | status_alive_1cyc;
end
/*
Control programming of external FPGA on the sensor/sensor multiplexor board
Mulptiplex status signals into a single line
......@@ -346,14 +382,14 @@ module sens_parallel12 #(
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)