Skip to content

X
x393
Commit ed32ff53 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

hardware debugging/testing

parent 09a3a7cd
Hide whitespace changes
Inline Side-by-side
Showing with 663 additions and 149 deletions
.project
View file @ ed32ff53
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150831151630695.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,32 +107,32 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150831152219741.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150903211518672.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150831151630695.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150903211518672.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150831152219741.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150903211518672.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150831152219741.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150903211518672.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150831152219741.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150903211518672.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150831151630695.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150903211518672.dcp</location>
</link>
</linkedResources>
</projectDescription>
compressor_jp/compressor393.v
View file @ ed32ff53
......@@ -111,6 +111,9 @@ module compressor393 # (
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 4'd2 // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
)(
// input rst, // global reset
......@@ -231,6 +234,12 @@ module compressor393 # (
input [ 7:0] afi1_wcount,
input [ 5:0] afi1_wacount,
output afi1_wrissuecap1en
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
input debug_di // input from the debug ring
`endif
);
wire [47:0] status_ad_mux;
......
fpga_version.vh
View file @ ed32ff53
parameter FPGA_VERSION = 32'h03930003;
parameter FPGA_VERSION = 32'h0393000f;
\ No newline at end of file
includes/x393_parameters.vh
View file @ ed32ff53
......@@ -723,6 +723,18 @@
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
`ifdef DEBUG_RING
// Debug module (read/write serial ring)
parameter DEBUG_ADDR = 'h710, //..'h713
parameter DEBUG_MASK = 'h7fc,
parameter DEBUG_STATUS_REG_ADDR = 'hfc, // address where status can be read out
parameter DEBUG_READ_REG_ADDR = 'hfd, // read 32-bit received shifted data
parameter DEBUG_SHIFT_DATA = 'h0, // shift i/o data by 32 bits
parameter DEBUG_LOAD = 'h1, // parallel load of the distributed shift registe (both ways)
parameter DEBUG_SET_STATUS = 'h2, // program status (mode 3?)
parameter DEBUG_CMD_LATENCY = 2, // >0 extra registers in the debug_sl (distriburted in parallel)
`endif
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1,
......
py393/x393_camsync.py
View file @ ed32ff53
......@@ -157,14 +157,15 @@ class X393Camsync(object):
@param delay - delay value in 10 ns steps - max 42.95 sec (or list/tuple if different for channels)
"""
self.set_camsync_period (0) # reset circuitry
self.set_gpio_ports (port_a = True)
self.X393_gpio.set_gpio_ports (port_a = True)
self.set_camsync_mode (
en = True,
snd_en = True,
en_snd = True,
en_ts_external = external_timestamp,
triggered_mode = trigger_mode,
master_chn = 0,
chn_en = sensor_mask)
# setting I/Os after camsync is enabled
self.reset_camsync_inout (is_out = 0) # reset input selection
if ext_trigger_mode :
......@@ -179,7 +180,9 @@ class X393Camsync(object):
self.set_camsync_period (SYNC_BIT_LENGTH) #set (bit_length -1) (should be 2..255), not the period
if not isinstance(camsync_delay,list) or isinstance(camsync_delay,tuple):
camsync_delay = (camsync_delay, camsync_delay, camsync_delay, camsync_delay)
for i, dly in enumerate (camsync_delay):
for i, dly in enumerate (camsync_delay):
if not dly is None:
self.set_camsync_delay(sub_chn = i, delay = dly)
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
if not camsync_period is None:
self.set_camsync_period (period = camsync_period) # set period (start generating) - in 353 was after everything else was set
py393/x393_cmprs.py
View file @ ed32ff53
......@@ -390,7 +390,7 @@ class X393Cmprs(object):
print ( "bayer = ",bayer)
print ( "focus_mode = ",focus_mode)
self.compressor_control(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
qbank = qbank, # [6:3] quantization table page
dc_sub = dc_sub, # [8:7] subtract DC
cmode = cmode, # [13:9] color mode:
......@@ -399,18 +399,18 @@ class X393Cmprs(object):
focus_mode = focus_mode) # [23:21] Set focus mode
self.compressor_format(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1
left_margin = left_margin) # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
self.compressor_color_saturation(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100%
colorsat_red = colorsat_red) # color saturation for red (10 bits) # 'b6 for 100%
self.compressor_coring(
num_sensor = num_sensor, # sensor channel number (0..3)
chn = num_sensor, # sensor channel number (0..3)
coring = coring); # coring value
py393/x393_sens_cmprs.py
View file @ ed32ff53
......@@ -44,8 +44,10 @@ import x393_rtc
import x393_utils
#import time
import time
import vrlg
PAGE_SIZE = 4096
SI5338_PATH = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
......@@ -154,9 +156,8 @@ class X393SensCmprs(object):
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 0,
histogram_height_m1 = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 1935, #0,
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -215,22 +216,25 @@ class X393SensCmprs(object):
frame_start_address = (last_buf_frame + 1) * frame_start_address_inc * num_sensor
# histogram_start_phys_page - system memory 4K page number to start histogram
histogram_start_phys_page = self.get_histogram_byte_start() // 4096
histogram_start_phys_page = self.get_histogram_byte_start() // 4096
if verbose >0 :
print ("setup_sensor_channel:")
print ("num_sensor = ", num_sensor)
print ("frame_full_width = ", frame_full_width)
print ("window_width = ", window_width)
print ("window_height = ", window_height)
print ("window_left = ", window_left)
print ("window_top = ", window_top)
print ("frame_start_address = ", frame_start_address)
print ("frame_start_address_inc = ", frame_start_address_inc)
print ("last_buf_frame = ", last_buf_frame)
print ("num_macro_cols_m1 = ", num_macro_cols_m1)
print ("num_macro_rows_m1 = ", num_macro_rows_m1)
print ("verbose = ", verbose)
print ("num_sensor = ", num_sensor)
print ("frame_full_width = ", frame_full_width)
print ("window_width = ", window_width)
print ("window_height = ", window_height)
print ("window_left = ", window_left)
print ("window_top = ", window_top)
print ("frame_start_address = 0x%x"%(frame_start_address))
print ("frame_start_address_inc = 0x%x"%(frame_start_address_inc))
print ("histogram_start_phys_page = 0x%x"%(histogram_start_phys_page))
print ("histogram start address = 0x%x"%(histogram_start_phys_page * 4096))
print ("last_buf_frame = ", last_buf_frame)
print ("num_macro_cols_m1 = ", num_macro_cols_m1)
print ("num_macro_rows_m1 = ", num_macro_rows_m1)
print ("verbose = ", verbose)
if exit_step == 10: return False
self.x393Sensor.program_status_sensor_i2c(
......@@ -243,7 +247,7 @@ class X393SensCmprs(object):
seq_num = 0); # input [5:0] seq_num;
self.x393Cmprs.program_status_compressor(
num_sensor = num_sensor, # input [1:0] num_sensor;
cmprs_chn = num_sensor, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
if exit_step == 11: return False
......@@ -307,7 +311,7 @@ class X393SensCmprs(object):
if exit_step == 15: return False
self.x393Cmprs.compressor_control(
num_sensor = num_sensor,
chn = num_sensor,
run_mode = 3) # run repetitive mode
if exit_step == 16: return False
......@@ -357,8 +361,8 @@ class X393SensCmprs(object):
self.x393Sensor.test_i2c_353() # test soft/sequencer i2c
"""
if verbose >0 :
print ("===================== LENS_FLAT_SETUP =========================")
self.x393Sensor.set_sensor_lens_flat_heights (self,
print ("===================== LENS_FLAT_SETUP ========================= num_sensor=",num_sensor)
self.x393Sensor.set_sensor_lens_flat_heights (
num_sensor = num_sensor,
height0_m1 = 0xffff,
height1_m1 = None,
......@@ -381,7 +385,7 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== GAMMA_SETUP =========================")
self.x393Sensor.set_sensor_gamma_heights (self,
self.x393Sensor.set_sensor_gamma_heights (
num_sensor = num_sensor,
height0_m1 = 0xffff,
height1_m1 = 0,
......@@ -392,7 +396,7 @@ class X393SensCmprs(object):
print ("===================== HISTOGRAMS_SETUP =========================")
self.x393Sensor.set_sensor_histogram_window ( # 353 did it using command sequencer)
num_sensor = num_sensor,
num_sub_sensor = 0,
subchannel = 0,
left = histogram_left,
top = histogram_top,
width_m1 = histogram_width_m1,
......@@ -458,9 +462,9 @@ class X393SensCmprs(object):
clk_sel = 1, # 1
histogram_left = 0,
histogram_top = 0,
histogram_width_m1 = 0,
histogram_height_m1 = 0,
histogram_width_m1 = 2559, #0,
histogram_height_m1 = 799, #0,
circbuf_chn_size= 0x1000000, #16777216
verbose = 1):
"""
Setup one sensor+compressor channel (for one sub-channel only)
......@@ -496,9 +500,35 @@ class X393SensCmprs(object):
@param histogram_top - histogram window top margin
@param histogram_width_m1 - one less than window width. If 0 - use frame right margin (end of HACT)
@param histogram_height_m1 - one less than window height. If 0 - use frame bottom margin (end of VACT)
@param circbuf_chn_size - circular buffer size for each channel, in bytes
@parame verbose - verbose level
@return True if all done, False if exited prematurely by exit_step
"""
# camsync_setup (
# 4'hf ); # sensor_mask); #
circbuf_start = self.get_circbuf_byte_start()
mem_end= self.get_circbuf_byte_end()
#circbuf_chn_size
circbuf_starts=[]
for i in range(16):
circbuf_starts.append(circbuf_start + i*circbuf_chn_size)
circbuf_end = circbuf_start + 4*circbuf_chn_size
#TODO: calculate addersses/lengths
afi_cmprs0_sa = circbuf_starts[0] // 4
afi_cmprs1_sa = circbuf_starts[1] // 4
afi_cmprs2_sa = circbuf_starts[2] // 4
afi_cmprs3_sa = circbuf_starts[3] // 4
afi_cmprs_len = circbuf_chn_size // 4
if verbose >0 :
print ("compressor system memory buffers:")
print ("circbuf start 0 = 0x%x"%(circbuf_starts[0]))
print ("circbuf start 1 = 0x%x"%(circbuf_starts[1]))
print ("circbuf start 2 = 0x%x"%(circbuf_starts[2]))
print ("circbuf start 3 = 0x%x"%(circbuf_starts[3]))
print ("circbuf end = 0x%x"%(circbuf_end))
print ("memory buffer end = 0x%x"%(mem_end))
if sensor_mask & 3: # Need mower for sesns1 and sens 2
if verbose >0 :
print ("===================== Sensor power setup: sensor ports 0 and 1 =========================")
......@@ -528,14 +558,6 @@ class X393SensCmprs(object):
self.x393Rtc.set_rtc () # no correction, use current system time
if exit_step == 3: return False
# camsync_setup (
# 4'hf ); # sensor_mask); #
#TODO: calculate addersses/lengths
afi_cmprs0_sa = 0
afi_cmprs1_sa = 0
afi_cmprs2_sa = 0
afi_cmprs3_sa = 0
afi_cmprs_len = 0
for num_sensor in range(4):
if sensor_mask & (1 << num_sensor):
......@@ -583,6 +605,67 @@ class X393SensCmprs(object):
afi_cmprs2_len = afi_cmprs_len,
afi_cmprs3_sa = afi_cmprs3_sa,
afi_cmprs3_len = afi_cmprs_len)
if exit_step == 21: return False
self.x393Sensor.print_status_sensor_io (num_sensor = num_sensor)
self.x393Sensor.print_status_sensor_i2c (num_sensor = num_sensor)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = True)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
num_bytes = 3,
dly = 100, # ??None,
scl_ctl = None,
sda_ctl = None)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
rst_cmd = False)
self.x393Sensor.set_sensor_i2c_command (
num_sensor = num_sensor,
run_cmd = True)
if exit_step == 21: return False
self.x393_camsync_setup ( sensor_mask = sensor_mask ) # sensor_mask); #
self.x393Camsync.camsync_setup (
sensor_mask = sensor_mask,
trigger_mode = False, #False - async (free running) sensor mode, True - triggered (global reset) sensor mode
ext_trigger_mode = False, # True - external trigger source, 0 - local FPGA trigger source
external_timestamp = False, # True - use received timestamp in the image file, False - use local timestamp
camsync_period = None,
camsync_delay = None)
def print_status_sensor(self,
restart = False,
chn = None):
"""
Decode and print channel-related status
@param restart - reset "alive" bits, wait 1 second, read status
@param chn - channel numberr or None - in that case print it for all channels
"""
if chn is None:
sensors=range(4)
else:
sensors = [chn]
if restart:
for chn in sensors:
self.x393Sensor.program_status_sensor_i2c(
num_sensor = chn, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
self.x393Sensor.program_status_sensor_io(
num_sensor = chn, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
self.x393Cmprs.program_status_compressor(
cmprs_chn = chn, # input [1:0] num_sensor;
mode = 3, # input [1:0] mode;
seq_num = 0); # input [5:0] seq_num;
time.sleep(1)
for chn in sensors:
self.x393Sensor.print_status_sensor_io (num_sensor = chn)
self.x393Sensor.print_status_sensor_i2c (num_sensor = chn)
py393/x393_sensor.py
View file @ ed32ff53
......@@ -97,6 +97,72 @@ class X393Sensor(object):
vrlg.SENSIO_STATUS,
mode,
seq_num)# //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
def get_status_sensor_io ( self,
num_sensor):
"""
Read sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
@return sesnor_io status
"""
return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSIO_STATUS_REG_REL))
def print_status_sensor_io (self,
num_sensor):
"""
Print sensor_io status word (no sync)
@param num_sensor - number of the sensor port (0..3)
"""
status= self.get_status_sensor_io(num_sensor)
print ("print_status_sensor_io(%d):"%(num_sensor))
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
print (" last_in_line_1cyc_mclk = %d"%((status>>23) & 1))
print (" dout_valid_1cyc_mclk = %d"%((status>>22) & 1))
print (" alive_hist0_gr = %d"%((status>>21) & 1))
print (" alive_hist0_rq = %d"%((status>>20) & 1))
print (" sof_out_mclk = %d"%((status>>19) & 1))
print (" eof_mclk = %d"%((status>>18) & 1))
print (" sof_mclk = %d"%((status>>17) & 1))
print (" sol_mclk = %d"%((status>>16) & 1))
print (" vact_alive = %d"%((status>>15) & 1))
print (" hact_ext_alive = %d"%((status>>14) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" ps_rdy = %d"%((status>> 9) & 1))
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" xfpgatdo = %d"%((status>>25) & 1))
print (" senspgmin = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
#vact_alive, hact_ext_alive, hact_alive
def get_status_sensor_i2c ( self,
num_sensor):
"""
Read sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
@return sesnor_io status
"""
return self.x393_axi_tasks.read_status(
address=(vrlg.SENSI2C_STATUS_REG_BASE + num_sensor * vrlg.SENSI2C_STATUS_REG_INC + vrlg.SENSI2C_STATUS_REG_REL))
def print_status_sensor_i2c (self,
num_sensor):
"""
Print sensor_i2c status word (no sync)
@param num_sensor - number of the sensor port (0..3)
"""
status= self.get_status_sensor_i2c(num_sensor)
print ("print_status_sensor_i2c(%d):"%(num_sensor))
print (" reset_on = %d"%((status>> 7) & 1))
print (" req_clr = %d"%((status>> 6) & 1))
print (" alive_fs = %d"%((status>> 5) & 1))
print (" busy = %d"%((status>> 4) & 1))
print (" frame_num = %d"%((status>> 0) & 0xf))
print (" sda_in = %d"%((status>>25) & 1))
print (" scl_in = %d"%((status>>24) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
# Functions used by sensor-related tasks
def func_sensor_mode (self,
......@@ -497,7 +563,7 @@ class X393Sensor(object):
@param fatzero_out (16 bits)
@param post_scale (4 bits) - shift of the result
"""
def func_lens_data (self,
def func_lens_data (
num_sensor,
addr,
data,
......@@ -653,8 +719,17 @@ class X393Sensor(object):
"""
raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3]
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_LEFT_TOP, ((top & 0xffff) << 16) | (left & 0xff))
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_WIDTH_HEIGHT, ((height_m1 & 0xffff) << 16) | (width_m1 & 0xff))
if self.DEBUG_MODE:
print("set_sensor_histogram_window():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
print("left = ", left)
print("top = ", top)
print("width_m1 = ", width_m1)
print("height_m1 = ", height_m1)
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_LEFT_TOP, ((top & 0xffff) << 16) | (left & 0xffff))
self.x393_axi_tasks.write_control_register(reg_addr + vrlg.HISTOGRAM_WIDTH_HEIGHT, ((height_m1 & 0xffff) << 16) | (width_m1 & 0xffff))
def set_sensor_histogram_saxi (self,
en,
nrst,
......@@ -667,6 +742,12 @@ class X393Sensor(object):
@param confirm_write - wait for the write confirmed (over B channel) before switching channels
@param cache_mode AXI cache mode, default should be 4'h3
"""
if self.DEBUG_MODE:
print("set_sensor_histogram_saxi():")
print("en = ", en)
print("nrst = ", nrst)
print("confirm_write = ", confirm_write)
print("cache_mode= ", cache_mode)
data = 0;
data |= (0,1)[en] << vrlg.HIST_SAXI_EN
data |= (0,1)[nrst] << vrlg.HIST_SAXI_NRESET
......@@ -684,6 +765,11 @@ class X393Sensor(object):
@param num_sub_sensor - sub-sensor attached to the same port through multiplexer (0..3)
@param page - system memory page address (in 4KB units)
"""
if self.DEBUG_MODE:
print("set_sensor_histogram_saxi_addr():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
print("page = ", page)
channel = ((num_sensor & 3) << 2) + (subchannel & 3)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + vrlg.HIST_SAXI_ADDR_REL + channel,page)
......
sensor/sens_histogram.v
View file @ ed32ff53
......@@ -35,6 +35,7 @@ module sens_histogram #(
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x,
input sof,
input eof,
input hact,
input [7:0] hist_di, // 8-bit pixel data
......@@ -48,6 +49,7 @@ module sens_histogram #(
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware
,output debug_mclk
);
localparam PXD_2X_LATENCY = 2;
reg hist_bank_pclk;
......@@ -101,7 +103,7 @@ module sens_histogram #(
reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle
wire hist_done_mclk;
reg vert_woi; // vertically in window
reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window
reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
reg hor_woi; // vertically in window
......@@ -123,6 +125,8 @@ module sens_histogram #(
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
reg debug_vert_woi_r;
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
......@@ -135,7 +139,7 @@ module sens_histogram #(
assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en;
//AF2015-new mod
wire line_start_w = hact && !hact_d[0];
wire line_start_w = hact && !hact_d[0]; // // tested active
reg pre_first_line;
reg frame_active; // until done
reg hist_en_pclk2x;
......@@ -157,6 +161,9 @@ module sens_histogram #(
reg monochrome_pclk;
reg monochrome_2x;
// assign debug_mclk = hist_done_mclk;
// assign debug_mclk = set_width_height_w;
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
else pxd_wa <= pxd_wa + 1;
......@@ -196,7 +203,10 @@ module sens_histogram #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vcntr_zero_w && vert_woi && line_start_w;
debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;
// hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0;
else if (sof && en_new) frame_active <= 1;
......@@ -338,6 +348,17 @@ module sens_histogram #(
end
pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (vert_woi && !debug_vert_woi_r), // line_start_w), // input vcntr_zero_w
// .in_pulse (vcntr_zero_w && !debug_vert_woi_r), // line_start_w), // input
.in_pulse (vcntr_zero_w && vert_woi && !debug_vert_woi_r), // line_start_w), // input
.out_pulse (debug_mclk), // output
.busy() // output
);
cmd_deser #(
.ADDR (HISTOGRAM_ADDR),
......
sensor/sens_parallel12.v
View file @ ed32ff53
......@@ -75,8 +75,8 @@ module sens_parallel12 #(
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STATUS_ALIVE_WIDTH = 4
)(
// input rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
......@@ -103,7 +103,9 @@ module sens_parallel12 #(
// output
output reg [11:0] pxd_out,
output reg vact_out,
output hact_out,
output hact_out,
input [STATUS_ALIVE_WIDTH-1:0] status_alive_1cyc, //extra toggle @mclk bits to report with status
// JTAG to program 10359
// input xpgmen, // enable programming mode for external FPGA
......@@ -171,7 +173,7 @@ module sens_parallel12 #(
wire [14:0] status;
wire [17:0] status;
wire cmd_we;
wire [2:0] cmd_a;
......@@ -188,10 +190,24 @@ module sens_parallel12 #(
reg xfpgatdi=0; // TDI to be sent to external FPGA
wire hact_ext; // received hact signal
reg hact_ext_r; // received hact signal, delayed by 1 clock
reg hact_r; // received or regenerated hact
reg hact_r; // received or regenerated hact
// for debug/test alive
reg vact_r;
reg hact_r2;
wire vact_a_mclk;
wire hact_ext_a_mclk;
wire hact_a_mclk;
reg vact_alive;
reg hact_ext_alive;
reg hact_alive;
reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3];
assign status = {locked_pxd_mmcm,clkin_pxd_stopped_mmcm,clkfb_pxd_stopped_mmcm,xfpgadone,ps_rdy, ps_out,xfpgatdo,senspgmin};
assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out, xfpgatdo, senspgmin};
assign hact_out = hact_r;
assign iaro = trigger_mode? ~trig : iaro_soft;
......@@ -285,8 +301,28 @@ module sens_parallel12 #(
pxd_out <= pxd_out_pre;
vact_out <= vact_out_pre;
// for debug/test alive
vact_r <= vact_out_pre;
hact_r2 <= hact_r;
end
// for debug/test alive
always @(posedge mclk) begin
if (mclk_rst || set_status_r) vact_alive <= 0;
else if (vact_a_mclk) vact_alive <= 1;
if (mclk_rst || set_status_r) hact_ext_alive <= 0;
else if (hact_ext_a_mclk) hact_ext_alive <= 1;
if (mclk_rst || set_status_r) hact_alive <= 0;
else if (hact_a_mclk) hact_alive <= 1;
if (mclk_rst || set_status_r) status_alive <= 0;
else status_alive <= status_alive | status_alive_1cyc;
end
/*
Control programming of external FPGA on the sensor/sensor multiplexor board
Mulptiplex status signals into a single line
......@@ -346,14 +382,14 @@ module sens_parallel12 #(
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(15) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mclk_rst), // input
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
.status (status), // input[25:0]
.status ({status_alive,status}), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......@@ -691,6 +727,34 @@ module sens_parallel12 #(
// BUFR ipclk_bufr_i (.O(ipclk), .CE(), .CLR(), .I(ipclk_pre));
// BUFR ipclk2x_bufr_i (.O(ipclk2x), .CE(), .CLR(), .I(ipclk2x_pre));
// for debug/test alive
pulse_cross_clock pulse_cross_clock_vact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (vact_out_pre && !vact_r), // input
.out_pulse (vact_a_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hact_ext_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (hact_ext && !hact_ext_r), // input
.out_pulse (hact_ext_a_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (hact_r && !hact_r2), // input
.out_pulse (hact_a_mclk), // output
.busy() // output
);
endmodule
sensor/sensor_channel.v
View file @ ed32ff53
......@@ -25,7 +25,7 @@ module sensor_channel#(
parameter SENSOR_NUMBER = 0, // sensor number (0..3)
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter SENSI2C_STATUS_REG_BASE = 'h30, // 4 locations" x30, x32, x34, x36
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x30, x32, x34, x36
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h30, 'h32, 'h34, 'h36
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h31, 'h33, 'h35, 'h37
......@@ -311,7 +311,7 @@ module sensor_channel#(
reg [SENSOR_MODE_WIDTH-1:0] mode;
wire [3:0] hist_en;
wire en_mclk; // enable this channel
wire en_pclk; // enabole in pclk domain
wire en_pclk; // enable in pclk domain
wire [3:0] hist_nrst;
wire bit16; // 16-bit mode, 0 - 8 bit mode
wire [3:0] hist_rq;
......@@ -446,7 +446,99 @@ module sensor_channel#(
.scl (sns_scl), // inout
.sda (sns_sda) // inout
);
wire [3:0] debug_hist_mclk;
wire irst; // @ posedge ipclk
localparam STATUS_ALIVE_WIDTH = 8;
wire [STATUS_ALIVE_WIDTH - 1 : 0] status_alive;
reg hact_r; // hact delayed by 1 cycle to generate start pulse
wire sol_mclk;
wire sof_mclk;
wire eof_mclk;
reg hist_rq0_r;
/// reg hist_gr0_r;
wire alive_hist0_rq = hist_rq[0] && !hist_rq0_r;
/// wire alive_hist0_gr = hist_gr[0] && !hist_gr0_r;
// sof_out_mclk - already exists
reg dout_valid_d_pclk; //@ pclk - delayed by 1 clk from dout_valid to detect edge
reg last_in_line_d_pclk; //@ pclk - delayed by 1 clk from last_in_line to detect edge
wire dout_valid_1cyc_mclk;
wire last_in_line_1cyc_mclk;
// debug_hist_mclk is never active, alive_hist0_rq == 0
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
/*
sof, hact are tested to be active
.sof (gamma_sof_out), // input
.hact (gamma_hact_out), // input
*/
always @ (posedge pclk) begin
// hact_r <= hact;
hact_r <= gamma_hact_out;
dout_valid_d_pclk <= dout_valid;
last_in_line_d_pclk <= last_in_line;
end
always @ (posedge mclk) begin
hist_rq0_r <= en_mclk & (hist_rq[0] ^ hist_rq0_r);
/// hist_gr0_r <= hist_gr[0];
end
/*
.hist_rq (hist_rq[0]), // output
.hist_grant (hist_gr[0]), // input
*/
// for debug/test alive
pulse_cross_clock pulse_cross_clock_sol_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (hact && !hact_r), // input
.in_pulse (gamma_hact_out && !hact_r), // input
.out_pulse (sol_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_sof_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (sof), // input
.in_pulse (gamma_sof_out), // input
.out_pulse (sof_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (eof), // input
.out_pulse (eof_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_dout_valid_1cyc_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (dout_valid && !dout_valid_d_pclk), // input
.out_pulse (dout_valid_1cyc_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_last_in_line_1cyc_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (last_in_line && !last_in_line_d_pclk), // input
.out_pulse (last_in_line_1cyc_mclk), // output
.busy() // output
);
sens_parallel12 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -492,7 +584,8 @@ module sensor_channel#(
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH)
) sens_parallel12_i (
// .rst (rst), // input
.pclk (pclk), // input
......@@ -512,9 +605,10 @@ module sensor_channel#(
.arst (sns_dn[7]), // inout
.aro (sns_ctl), // inout
.dclk (sns_dp[0]), // output
.pxd_out (pxd_to_fifo[11:0]), // output[11:0]
.vact_out (vact_to_fifo), // output
.hact_out (hact_to_fifo), // output: either delayed input, or regenerated from the leading edge and programmable duration
.pxd_out (pxd_to_fifo[11:0]), // output[11:0] @posedge ipclk
.vact_out (vact_to_fifo), // output @posedge ipclk
.hact_out (hact_to_fifo), // output @posedge ipclk: either delayed input, or regenerated from the leading edge and programmable duration
.status_alive_1cyc (status_alive), // input [3:0] @ posedge mclk, each bit single cycle pulse
.mclk (mclk), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
......@@ -536,10 +630,10 @@ module sensor_channel#(
.pxd_in (pxd_to_fifo), // input[11:0]
.vact (vact_to_fifo), // input
.hact (hact_to_fifo), // input
.pxd_out (pxd), // output[11:0]
.data_valid (hact), // output
.sof (sof), // output
.eof (eof) // output
.pxd_out (pxd), // output[11:0] @posedge pclk
.data_valid (hact), // output @posedge pclk
.sof (sof), // output @posedge pclk
.eof (eof) // output @posedge pclk
);
sens_sync #(
......@@ -563,10 +657,10 @@ module sensor_channel#(
.hact (hact), // input
.trigger_mode (trigger_mode), // input
.trig_in (trig_in), // input
.trig (trig), // output
.sof_out_pclk (sof_out_sync), // output reg
.sof_out (sof_out_mclk), // output
.sof_late (sof_late_mclk), // output
.trig (trig), // output @pclk
.sof_out_pclk (sof_out_sync), // output reg @pclk
.sof_out (sof_out_mclk), // output @mclk
.sof_late (sof_late_mclk), // output @mclk
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
);
......@@ -670,6 +764,7 @@ module sensor_channel#(
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
......@@ -681,7 +776,8 @@ module sensor_channel#(
.hist_dv (hist_dv[0]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[0])
);
else
sens_histogram_dummy sens_histogram_dummy_i (
......@@ -705,6 +801,7 @@ module sensor_channel#(
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
......@@ -716,7 +813,8 @@ module sensor_channel#(
.hist_dv (hist_dv[1]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[1])
);
else
sens_histogram_dummy sens_histogram_dummy_i (
......@@ -740,6 +838,7 @@ module sensor_channel#(
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
......@@ -752,6 +851,7 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[2])
);
else
sens_histogram_dummy sens_histogram_dummy_i (
......@@ -775,6 +875,7 @@ module sensor_channel#(
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
......@@ -787,6 +888,7 @@ module sensor_channel#(
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.monochrome (HIST_MONOCHROME) // input
,.debug_mclk(debug_hist_mclk[3])
);
else
sens_histogram_dummy sens_histogram_dummy_i (
......
sensor/sensor_i2c.v
View file @ ed32ff53
......@@ -21,14 +21,14 @@
`timescale 1ns/1ps
module sensor_i2c#(
parameter SENSI2C_ABS_ADDR = 'h300,
parameter SENSI2C_REL_ADDR = 'h310,
parameter SENSI2C_ABS_ADDR = 'h410,
parameter SENSI2C_REL_ADDR = 'h420,
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_CTRL_ADDR = 'h320,
parameter SENSI2C_CTRL_ADDR = 'h402,
parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1,
parameter SENSI2C_STATUS_REG = 'h30,
parameter SENSI2C_STATUS_REG = 'h20,
// Control register bits
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
......@@ -54,7 +54,7 @@ module sensor_i2c#(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start,// Acknowledge of the first status packet byte (address)
input frame_sync, // increment/reset frame number
input frame_sync, // @posedge mclk increment/reset frame number
// input frame_0, // reset frame number to zero - can be done by soft reset before first enabled frame
// output busy, // busy (do not use software i2i)
input scl_in, // i2c SCL input
......@@ -121,7 +121,7 @@ module sensor_i2c#(
wire [3:0] frame_num=wpage0[3:0];
//fifo write pointers (dual port distributed RAM)
reg [5:0] fifo_wr_pointers [0:15]; // dual ported read?
reg [5:0] fifo_wr_pointers_ram [0:15]; // dual ported read?
wire [5:0] fifo_wr_pointers_outw; // pointer dual-ported RAM - write port out, valid next after command
wire [5:0] fifo_wr_pointers_outr; // pointer dual-ported RAM - read port out
......@@ -188,16 +188,16 @@ module sensor_i2c#(
reg wen_fifo; // [1] was not used - we_fifo_wp was used instead
assign set_ctrl_w = we_cmd && (wa == SENSI2C_CTRL );// ==0
assign set_status_w = we_cmd && (wa == SENSI2C_STATUS );// ==0
assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
assign scl_out=i2c_run? scl_hard: scl_soft ;
assign sda_out=i2c_run? sda_hard: sda_soft ;
assign scl_en=i2c_run? 1'b1: scl_en_soft ;
assign sda_en=i2c_run? sda_en_hard: sda_en_soft ;
assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc) && (req_clr || reset_on) ;
assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ;
assign fifo_wr_pointers_outw = fifo_wr_pointers[wpage_wr[3:0]]; // valid next after command
assign fifo_wr_pointers_outr = fifo_wr_pointers[page_r[3:0]];
assign fifo_wr_pointers_outw = fifo_wr_pointers_ram[wpage_wr[3:0]]; // valid next after command
assign fifo_wr_pointers_outr = fifo_wr_pointers_ram[page_r[3:0]];
// wire we_abs;
......@@ -207,7 +207,12 @@ module sensor_i2c#(
// wire [3:0] wa;
assign wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w?
reg alive_fs;
always @ (posedge mclk) begin
if (set_status_w) alive_fs <= 0;
else if (frame_sync) alive_fs <= 1;
end
cmd_deser #(
.ADDR (SENSI2C_ABS_ADDR),
......@@ -232,14 +237,14 @@ module sensor_i2c#(
status_generate #(
.STATUS_REG_ADDR(SENSI2C_STATUS_REG),
.PAYLOAD_BITS(7) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(7+3) // STATUS_PAYLOAD_BITS)
) status_generate_sens_i2c_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (di[7:0]), // input[7:0]
.status ({busy, frame_num, sda_in, scl_in}), // input[25:0]
.status ({reset_on, req_clr, alive_fs,busy, frame_num, sda_in, scl_in}), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......@@ -292,27 +297,28 @@ module sensor_i2c#(
// write pointer memory
wpage0_inc <= {wpage0_inc[0],pre_wpage0_inc};
// reset pointers in all 16 pages:
reset_on <= reset_cmd || (reset_on && !(wpage0_inc && ( wpage0[3:0] == 4'hf)));
reset_on <= reset_cmd || (reset_on && !(wpage0_inc[0] && ( wpage0[3:0] == 4'hf)));
// request to clear pointer(s)? for one page - during reset or delayed frame sync (if previous was not finished)
req_clr <= frame_sync || (req_clr && !wpage0_inc);
req_clr <= frame_sync || (req_clr && !wpage0_inc[0]);
if (reset_cmd) wpage0 <= 0;
if (reset_cmd) wpage0 <= 0;
// else if (frame_0) wpage0 <= 0;
else if (wpage0_inc) wpage0<=wpage0+1;
else if (wpage0_inc[0]) wpage0<=wpage0+1;
if (reset_cmd) wpage_prev<=4'hf;
else if (wpage0_inc) wpage_prev<=wpage0;
if (reset_cmd) wpage_prev<=4'hf;
else if (wpage0_inc[0]) wpage_prev<=wpage0;
if (we_abs) wpage_wr <= ((wa==wpage_prev)? wpage0[3:0] : wa);
else if (we_rel) wpage_wr <= wpage0+wa;
else if (wpage0_inc) wpage_wr <= wpage_prev; // only for erasing?
if (we_abs) wpage_wr <= ((wa==wpage_prev)? wpage0[3:0] : wa);
else if (we_rel) wpage_wr <= wpage0+wa;
else if (wpage0_inc[0]) wpage_wr <= wpage_prev; // only for erasing?
// we_fifo_wp <= wen || wpage0_inc; // during commands and during reset?
/// we_fifo_wp <= wen_fifo[0] || wpage0_inc; // during commands and during reset?
// we_fifo_wp <= wen_fifo[0] || we_rel || we_abs; // ??
we_fifo_wp <= wen_fifo || we_rel || we_abs; // ??
//// we_fifo_wp <= wen_fifo || we_rel || we_abs; // ??
we_fifo_wp <= wen_fifo || wpage0_inc[0];
// reg [1:0] wen_r;
// reg [1:0] wen_fifo;
......@@ -322,7 +328,7 @@ module sensor_i2c#(
if (wen_fifo) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
// write to dual-port pointer memory
if (we_fifo_wp) fifo_wr_pointers[wpage_wr] <= wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
if (we_fifo_wp) fifo_wr_pointers_ram[wpage_wr] <= wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command i2c fifo (RAMB16_S9_S18)
......@@ -342,7 +348,7 @@ module sensor_i2c#(
if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0;
else if (i2c_done) rpointer[5:0] <= rpointer[5:0] + 1;
i2c_run <= !reset_cmd && (i2c_start || (i2c_run && !i2c_done));
i2c_run <= !reset_cmd && !reset_on && (i2c_start || (i2c_run && !i2c_done));
i2c_start <= i2c_enrun && !i2c_run && !i2c_start && (rpointer[5:0]!= fifo_wr_pointers_outr_r[5:0]) && !(|page_r_inc);
page_r_inc[1:0] <= {page_r_inc[0],
!i2c_run && // not i2c in progress
......@@ -394,7 +400,7 @@ module sensor_i2c#(
scl_hard <= scl_0;
sda_en_hard <= i2c_run && (!sda_0 || (!i2c_is_ackn && !sda_hard));
if (wen) busy_cntr <= 4'hf;
if (wen) busy_cntr <= 4'hf;
else if (|busy_cntr) busy_cntr <= busy_cntr-1;
busy <= (i2c_enrun && ((rpointer[5:0]!= fifo_wr_pointers_outr_r[5:0]) || (page_r!=wpage0))) ||
......
sensor/sensor_i2c_io.v
View file @ ed32ff53
......@@ -21,10 +21,10 @@
`timescale 1ns/1ps
module sensor_i2c_io#(
parameter SENSI2C_ABS_ADDR = 'h300,
parameter SENSI2C_REL_ADDR = 'h310,
parameter SENSI2C_ABS_ADDR = 'h410,
parameter SENSI2C_REL_ADDR = 'h420,
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_CTRL_ADDR = 'h320,
parameter SENSI2C_CTRL_ADDR = 'h402, // channel 0 will be 'h402..'h403
parameter SENSI2C_CTRL_MASK = 'h7fe,
parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1,
......
sensor/sensors393.v
View file @ ed32ff53
......@@ -224,6 +224,9 @@ module sensors393 #(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2
`endif
) (
// input rst,
......@@ -304,6 +307,11 @@ module sensors393 #(
output saxi_bready, // AXI PS Slave GP0 BREADY, input
input [ 5:0] saxi_bid, // AXI PS Slave GP0 BID[5:0], output
input [ 1:0] saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
input debug_di // input from the debug ring
`endif
);
wire [1:0] idelay_ctrl_rdy; // need to connect outputs to prevent optimizing out
......
system_defines.vh
View file @ ed32ff53
......@@ -2,6 +2,7 @@
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define PRELOAD_BRAMS
`define DEBUG_RING
// Enviroment-dependent options
`ifdef IVERILOG
`define SIMULATION
......
x393.v
View file @ ed32ff53
......@@ -311,6 +311,16 @@ module x393 #(
wire status_clocks_rq; // Other status request
wire status_clocks_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
`ifdef DEBUG_RING
wire [7:0] status_debug_ad; // saxi1 - logger data Other status byte-wide address/data
wire status_debug_rq; // Other status request
wire status_debug_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
localparam DEBUG_RING_LENGTH = 10;
wire [DEBUG_RING_LENGTH-1:0] debug_ring; // TODO: adjust number of bits
wire debug_sl; // debug shift/load: 0 - idle, (1,0) - shift, (1,1) - load
`endif
// Insert register layer if needed
reg [7:0] cmd_mcontr_ad;
reg cmd_mcontr_stb;
......@@ -345,6 +355,10 @@ module x393 #(
reg [7:0] cmd_clocks_ad;
reg cmd_clocks_stb;
`ifdef DEBUG_RING
reg [7:0] cmd_debug_ad;
reg cmd_debug_stb;
`endif
// membridge
wire frame_start_chn1; // input
wire next_page_chn1; // input
......@@ -533,6 +547,11 @@ module x393 #(
cmd_clocks_ad <= cmd_root_ad;
cmd_clocks_stb <= cmd_root_stb;
`ifdef DEBUG_RING
cmd_debug_ad <= cmd_root_ad;
cmd_debug_stb <= cmd_root_stb;
`endif
end
// For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
......@@ -892,9 +911,9 @@ assign axi_grst = axi_rst_pre;
.rq_in10 (status_clocks_rq), // input
.start_in10(status_clocks_start), // output
.db_in11 (8'b0), // input[7:0]
.rq_in11 (1'b0), // input
.start_in11(), // output
.db_in11 (status_debug_ad), // input[7:0]
.rq_in11 (status_debug_rq), // input
.start_in11(status_debug_start), // output
.db_in12 (8'b0), // input[7:0]
.rq_in12 (1'b0), // input
......@@ -1518,6 +1537,9 @@ assign axi_grst = axi_rst_pre;
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sensors393_i (
// .rst (axi_rst), // input
.pclk (pclk), // input
......@@ -1585,7 +1607,12 @@ assign axi_grst = axi_rst_pre;
.saxi_bvalid (saxi0_bvalid), // input
.saxi_bready (saxi0_bready), // output
.saxi_bid (saxi0_bid), // input[5:0]
.saxi_bresp (saxi0_bresp) // input[1:0]
.saxi_bresp (saxi0_bresp) // input[1:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[1]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[0]) // input
`endif
);
// AFI1 (AXI_HP1) signals - write channels only
......@@ -1720,6 +1747,10 @@ assign axi_grst = axi_rst_pre;
.CMPRS_AFIMUX_WIDTH (CMPRS_AFIMUX_WIDTH),
.CMPRS_AFIMUX_CYCBITS (CMPRS_AFIMUX_CYCBITS),
.AFI_MUX_BUF_LATENCY (AFI_MUX_BUF_LATENCY)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) compressor393_i (
// .rst (axi_rst), // input
.xclk (xclk), // input
......@@ -1809,6 +1840,12 @@ assign axi_grst = axi_rst_pre;
.afi1_wcount (afi2_wcount), // input[7:0]
.afi1_wacount (afi2_wacount), // input[5:0]
.afi1_wrissuecap1en (afi2_wrissuecap1en) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[DEBUG_RING_LENGTH-1]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[1]) // input
`endif
);
// general purpose I/Os, connected to the 10389 boards
......@@ -2146,6 +2183,30 @@ assign axi_grst = axi_rst_pre;
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
);
`ifdef DEBUG_RING
debug_master #(
.DEBUG_ADDR (DEBUG_ADDR),
.DEBUG_MASK (DEBUG_MASK),
.DEBUG_STATUS_REG_ADDR (DEBUG_STATUS_REG_ADDR),
.DEBUG_READ_REG_ADDR (DEBUG_READ_REG_ADDR),
.DEBUG_SHIFT_DATA (DEBUG_SHIFT_DATA),
.DEBUG_LOAD (DEBUG_LOAD),
.DEBUG_SET_STATUS (DEBUG_SET_STATUS),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_master_i (
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_debug_ad), // input[7:0]
.cmd_stb (cmd_debug_stb), // input
.status_ad (status_debug_ad), // output[7:0]
.status_rq (status_debug_rq), // output
.status_start (status_debug_start), // input
.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // output
.debug_di (debug_ring[DEBUG_RING_LENGTH-1]) // input
);
`endif
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
......
x393_testbench02.tf
View file @ ed32ff53
......@@ -78,7 +78,7 @@ module x393_testbench02 #(
//`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
parameter TRIGGER_MODE = 1; // 0 - auto, 1 - triggered
parameter TRIGGER_MODE = 0; // 1; // 0 - auto, 1 - triggered
parameter EXT_TRIGGER_MODE = 1 ; // 0 - internal, 1 - external trigger (camsync)
parameter EXTERNAL_TIMESTAMP = 1 ; // embed local timestamp, 1 - embed received timestamp
......@@ -922,7 +922,59 @@ assign #10 gpio_pins[9] = gpio_pins[8];
// camsync_setup (
// 4'hf ); // sensor_mask); //
TEST_TITLE = "RESEST_I2C_SEQUENCER0";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_i2c_command(
0, // input [1:0] num_sensor;
1'b1, // input rst_cmd; // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
2'b0, // input [SENSI2C_CMD_RUN_PBITS : 0] run_cmd; // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
1'b1, // input set_bytes; // [11] if 1, use bytes (below), 0 - nop
2'h3, // input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
1'b1, // input set_dly; // [8] if 1, use dly (0 - ignore)
8'h0a, // input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
2'b0, // input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
2'b0); // input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
TEST_TITLE = "RESEST_I2C_SEQUENCER1";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_i2c_command(
1, // input [1:0] num_sensor;
1'b1, // input rst_cmd; // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
2'b0, // input [SENSI2C_CMD_RUN_PBITS : 0] run_cmd; // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
1'b1, // input set_bytes; // [11] if 1, use bytes (below), 0 - nop
2'h3, // input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
1'b1, // input set_dly; // [8] if 1, use dly (0 - ignore)
8'h0a, // input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
2'b0, // input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
2'b0); // input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
TEST_TITLE = "RESEST_I2C_SEQUENCER2";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_i2c_command(
2, // input [1:0] num_sensor;
1'b1, // input rst_cmd; // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
2'b0, // input [SENSI2C_CMD_RUN_PBITS : 0] run_cmd; // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
1'b1, // input set_bytes; // [11] if 1, use bytes (below), 0 - nop
2'h3, // input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
1'b1, // input set_dly; // [8] if 1, use dly (0 - ignore)
8'h0a, // input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
2'b0, // input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
2'b0); // input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
TEST_TITLE = "RESEST_I2C_SEQUENCER3";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_i2c_command(
3, // input [1:0] num_sensor;
1'b1, // input rst_cmd; // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
2'b0, // input [SENSI2C_CMD_RUN_PBITS : 0] run_cmd; // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
1'b1, // input set_bytes; // [11] if 1, use bytes (below), 0 - nop
2'h3, // input [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes; // [10:9] set command bytes to send after slave address (0..3)
1'b1, // input set_dly; // [8] if 1, use dly (0 - ignore)
8'h0a, // input [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly; // [7:0] - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
2'b0, // input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
2'b0); // input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
TEST_TITLE = "DELAY_FOR_I2C_RESET";
$display("===================== TEST_%s =========================",TEST_TITLE);
#1000; // Wait 1 usec
TEST_TITLE = "TEST_SENSOR1";
$display("===================== TEST_%s =========================",TEST_TITLE);
setup_sensor_channel (
......@@ -2313,7 +2365,7 @@ task setup_sensor_channel;
num_sensor, // input [1:0] num_sensor;
3, // input [1:0] mrst; // <2: keep MRST, 2 - MRST low (active), 3 - high (inactive)
3, // input [1:0] arst; // <2: keep ARST, 2 - ARST low (active), 3 - high (inactive)
3, // input [1:0] aro; // <2: keep ARO, 2 - set ARO (software controlled) low, 3 - set ARO (software controlled) high
TRIGGER_MODE?3:2, // input [1:0] aro; // <2: keep ARO, 2 - set ARO (software controlled) low, 3 - set ARO (software controlled) high
0, // input [1:0] mmcm_rst; // <2: keep MMCM reset, 2 - MMCM reset off, 3 - MMCM reset on
3, // input [1:0] clk_sel; // <2: keep MMCM clock source, 2 - use internal pixel clock, 3 - use pixel clock from the sensor
0, // input set_delays; // (self-clearing) load all pre-programmed delays
......@@ -2343,7 +2395,7 @@ task setup_sensor_channel;
TEST_TITLE = "I2C_TEST";
$display("===================== TEST_%s =========================",TEST_TITLE);
test_i2c_353; // test soft/sequencer i2c
test_i2c_353 (num_sensor); // test soft/sequencer i2c
TEST_TITLE = "LENS_FLAT_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
......@@ -2817,9 +2869,12 @@ endtask
task test_i2c_353;
input [1:0] chn;
begin
// Reset moved out, done for all channels, then 1 usec delay
/*
set_sensor_i2c_command(
2'b0, // input [1:0] num_sensor;
chn, // input [1:0] num_sensor;
1'b1, // input rst_cmd; // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
2'b0, // input [SENSI2C_CMD_RUN_PBITS : 0] run_cmd; // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
1'b1, // input set_bytes; // [11] if 1, use bytes (below), 0 - nop
......@@ -2829,33 +2884,34 @@ task test_i2c_353;
2'b0, // input [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl; // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
2'b0); // input [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl; // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA
repeat (10) @ (posedge CLK); // wait for initialization to be done TODO: use status
set_sensor_i2c_command (0, 0, 3, 0, 0, 0, 0, 0, 0); // run i2c - reset software bits
set_sensor_i2c_command (0, 0, 2, 0, 0, 0, 0, 0, 0); // stop i2c, enable software control
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 0, 2); // SDA = 1
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 0, 1); // SDA = 0
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 2, 0); // SCL = 1
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 1, 0); // SCL = 0
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 0, 2); // SDA = 1
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 2, 0); // SCL = 1
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 0, 3); // SDA = 'bz
set_sensor_i2c_command (0, 0, 0, 0, 0, 0, 0, 3, 0); // SCL = 'bz
set_sensor_i2c_command (0, 0, 3, 0, 0, 0, 0, 0, 0); // run i2c
*/
set_sensor_i2c_command (chn, 0, 3, 0, 0, 0, 0, 0, 0); // run i2c - reset software bits
set_sensor_i2c_command (chn, 0, 2, 0, 0, 0, 0, 0, 0); // stop i2c, enable software control
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 2); // SDA = 1
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 1); // SDA = 0
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 2, 0); // SCL = 1
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 1, 0); // SCL = 0
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 2); // SDA = 1
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 2, 0); // SCL = 1
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 3); // SDA = 'bz
set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 3, 0); // SCL = 'bz
set_sensor_i2c_command (chn, 0, 3, 0, 0, 0, 0, 0, 0); // run i2c
write_sensor_i2c (
0, // input [1:0] num_sensor;
chn, // input [1:0] num_sensor;
0, // input rel_addr; // 0 - absolute, 1 - relative
1, // input integer addr;
'h90040793); // input [31:0] data;
write_sensor_i2c (0, 0, 1,'h90050a23);
write_sensor_i2c (0, 0, 2,'h90080001);
write_sensor_i2c (0, 0, 3,'h90090123);
write_sensor_i2c (0, 1, 2,'h90091234);
write_sensor_i2c (0, 0, 4,'h9004001f);
write_sensor_i2c (0, 0, 4,'h9005002f);
write_sensor_i2c (0, 1, 3,'h90020013);
write_sensor_i2c (0, 1, 3,'h90030017);
write_sensor_i2c (chn, 0, 1,'h90050a23);
write_sensor_i2c (chn, 0, 2,'h90080001);
write_sensor_i2c (chn, 0, 3,'h90090123);
write_sensor_i2c (chn, 1, 2,'h90091234);
write_sensor_i2c (chn, 0, 4,'h9004001f);
write_sensor_i2c (chn, 0, 4,'h9005002f);
write_sensor_i2c (chn, 1, 3,'h90020013);
write_sensor_i2c (chn, 1, 3,'h90030017);
end
endtask
......@@ -2990,6 +3046,8 @@ task set_sensor_i2c_command;
reg [31:0] tmp;
begin
// only needs wait busy for software i2c
// #80; // instead of wait busy - check if it is needed
tmp= {func_sensor_i2c_command(rst_cmd, run_cmd, set_bytes, bytes, set_dly, dly, scl_ctl, sda_ctl)};
write_contol_register( SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC +SENSI2C_CTRL_RADDR, tmp);
end
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment