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Commit ed27aded authored by Andrey Filippov's avatar Andrey Filippov
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comparing MCLT Verilog vs Java through next stages

parent 07baa42b
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dsp/mclt16x16.v
View file @ ed27aded
...@@ -92,50 +92,51 @@ module mclt16x16#( ...@@ -92,50 +92,51 @@ module mclt16x16#(
mpix_a_w[4] & ~mpix_a_w[0], mpix_a_w[4] & ~mpix_a_w[0],
~mpix_a_w[4] & mpix_a_w[0], ~mpix_a_w[4] & mpix_a_w[0],
~mpix_a_w[4] & ~mpix_a_w[0]}; ~mpix_a_w[4] & ~mpix_a_w[0]};
wire mpix_use = |(bayer_d & bayer_1hot); //not disabled by bayer, valid with mpix_a_w
wire mpix_use_d; // delayed wire mpix_use = |(bayer_d & bayer_1hot); //not disabled by bayer, valid with mpix_a_w
reg mpix_use_r; // delayed wire mpix_use_d; // delayed
wire [ 3:0] mpix_sgn_d; reg mpix_use_r; // delayed
reg [ 3:0] mpix_sgn_r; wire [ 3:0] mpix_sgn_d;
wire [WND_WIDTH-1:0] window_w; reg [ 3:0] mpix_sgn_r;
reg [WND_WIDTH-1:0] window_r; wire signed [WND_WIDTH-1:0] window_w;
reg [PIXEL_WIDTH-1:0] mpixel_d_r; // registered pixel data (to be absorbed by MPY) reg signed [WND_WIDTH-1:0] window_r;
reg signed [PIXEL_WIDTH-1:0] mpixel_d_r; // registered pixel data (to be absorbed by MPY)
reg [PIXEL_WIDTH + WND_WIDTH - 1:0] pix_wnd_r; reg signed [PIXEL_WIDTH + WND_WIDTH - 1:0] pix_wnd_r; // MSB not used: positive[PIXEL_WIDTH]*positive[WND_WIDTH]->positive[PIXEL_WIDTH+WND_WIDTH-1]
reg [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow reg signed [DTT_IN_WIDTH-1:0] pix_wnd_r2; // pixels (positive) multiplied by window(positive), two MSBs == 2'b0 to prevent overflow
// parameter DTT_IN_WIDTH = 24 // parameter DTT_IN_WIDTH = 24
// wire [DTT_IN_WIDTH-3:0] pix_wnd = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 1 -: DTT_IN_WIDTH-2]; // wire [DTT_IN_WIDTH-3:0] pix_wnd = pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 1 -: DTT_IN_WIDTH-2];
reg [DTT_IN_WIDTH-1:0] data_cc_r; reg signed [DTT_IN_WIDTH-1:0] data_cc_r;
reg [DTT_IN_WIDTH-1:0] data_sc_r; reg signed [DTT_IN_WIDTH-1:0] data_sc_r;
reg [DTT_IN_WIDTH-1:0] data_cs_r; reg signed [DTT_IN_WIDTH-1:0] data_cs_r;
reg [DTT_IN_WIDTH-1:0] data_ss_r; reg signed [DTT_IN_WIDTH-1:0] data_ss_r;
// delay data to appear at different time slots from data_cc_r // delay data to appear at different time slots from data_cc_r
wire [DTT_IN_WIDTH-1:0] data_sc_w0; // delayed by 1 cycle wire signed [DTT_IN_WIDTH-1:0] data_sc_w0; // delayed by 1 cycle
wire [DTT_IN_WIDTH-1:0] data_cs_w1; // delayed by 2 cycles wire signed [DTT_IN_WIDTH-1:0] data_cs_w1; // delayed by 2 cycles
wire [DTT_IN_WIDTH-1:0] data_ss_w2; // delayed by 3 cycles wire signed [DTT_IN_WIDTH-1:0] data_ss_w2; // delayed by 3 cycles
reg [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data reg signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
reg [1:0] mode_mux; reg [1:0] mode_mux;
reg [7:0] dtt_in_cntr; // reg [7:0] dtt_in_cntr; //
reg dtt_in_page; reg dtt_in_page;
wire [8:0] dtt_in_wa = {dtt_in_page, dtt_in_cntr[1:0], dtt_in_cntr[7:2]}; wire [8:0] dtt_in_wa = {dtt_in_page, dtt_in_cntr[1:0], dtt_in_cntr[7:2]};
wire dtt_we = in_busy[16]; wire dtt_we = in_busy[16];
wire var_first_d; // adding subtracting first variant of 4 folds wire var_first_d; // adding subtracting first variant of 4 folds
reg var_first_r; // adding subtracting first variant of 4 folds reg var_first_r; // adding subtracting first variant of 4 folds
wire var_last; // next cycle the data_xx_r will have data (in_busy[14], ...) wire var_last; // next cycle the data_xx_r will have data (in_busy[14], ...)
// reading/converting DTT // reading/converting DTT
wire start_dtt = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256 wire start_dtt = dtt_in_cntr == 196; // fune tune? ~= 3/4 of 256
reg [7:0] dtt_r_cntr; // reg [7:0] dtt_r_cntr; //
reg dtt_r_page; reg dtt_r_page;
reg dtt_r_re; reg dtt_r_re;
reg dtt_r_regen; reg dtt_r_regen;
reg dtt_start; reg dtt_start;
wire [1:0] dtt_mode = {dtt_r_cntr[7], dtt_r_cntr[6]}; // TODO: or reverse? wire [1:0] dtt_mode = {dtt_r_cntr[7], dtt_r_cntr[6]}; // TODO: or reverse?
wire [8:0] dtt_r_ra = {dtt_r_page,dtt_r_cntr}; wire [8:0] dtt_r_ra = {dtt_r_page,dtt_r_cntr};
wire [35:0] dtt_r_data_w; // high bits are not used wire signed [35:0] dtt_r_data_w; // high bits are not used
wire [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0]; wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0];
reg pre_last_out_r; reg pre_last_out_r;
reg pre_last_in_r; reg pre_last_in_r;
...@@ -173,11 +174,13 @@ module mclt16x16#( ...@@ -173,11 +174,13 @@ module mclt16x16#(
window_r <= window_w; window_r <= window_w;
end end
if (in_busy[9]) pix_wnd_r <= mpixel_d_r * window_r; if (in_busy[9]) pix_wnd_r <= mpixel_d_r * window_r; // 1 MSB is extra
if (in_busy[10]) pix_wnd_r2 <= {2'b00,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 1 -: DTT_IN_WIDTH - 2]}; // pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60
/// if (in_busy[10]) pix_wnd_r2 <= {2'b00,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
if (in_busy[10]) begin if (in_busy[10]) begin
/// if (in_busy[9]) begin /// if (in_busy[9]) begin
pix_wnd_r2 <= {2'b00,pix_wnd_r[PIXEL_WIDTH + WND_WIDTH - 2 -: DTT_IN_WIDTH - 2]};
mpix_use_r <= mpix_use_d; mpix_use_r <= mpix_use_d;
var_first_r <= var_first_d; var_first_r <= var_first_d;
mpix_sgn_r <= mpix_sgn_d; mpix_sgn_r <= mpix_sgn_d;
...@@ -185,10 +188,10 @@ module mclt16x16#( ...@@ -185,10 +188,10 @@ module mclt16x16#(
if (in_busy[11]) begin if (in_busy[11]) begin
data_cc_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + mpix_use_r ? (mpix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}} ; data_cc_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (mpix_use_r ? (mpix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
data_sc_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + mpix_use_r ? (mpix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}} ; data_sc_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (mpix_use_r ? (mpix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
data_cs_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_cs_r) + mpix_use_r ? (mpix_sgn_r[2]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}} ; data_cs_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_cs_r) + (mpix_use_r ? (mpix_sgn_r[2]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
data_ss_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_ss_r) + mpix_use_r ? (mpix_sgn_r[3]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}} ; data_ss_r <= (var_first_r ? {DTT_IN_WIDTH{1'b0}} : data_ss_r) + (mpix_use_r ? (mpix_sgn_r[3]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;
end end
if (var_last) mode_mux <= 0; if (var_last) mode_mux <= 0;
...@@ -304,8 +307,9 @@ D11 - negate for mode 3 (SS) ...@@ -304,8 +307,9 @@ D11 - negate for mode 3 (SS)
) dly_pixel_data_i ( ) dly_pixel_data_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher // .dly (4'h2), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({mpixel_prepage, in_busy[3], mpix_a_w}), // input[0:0] .dly (4'h3), // input[3:0] Delay for external memory latency = 2, reduce for higher
.din ({mpixel_prepage, in_busy[2], mpix_a_w}), // input[0:0]
.dout ({mpixel_page, mpixel_re, mpixel_a}) // output[0:0] .dout ({mpixel_page, mpixel_re, mpixel_a}) // output[0:0]
); );
...@@ -327,7 +331,8 @@ D11 - negate for mode 3 (SS) ...@@ -327,7 +331,8 @@ D11 - negate for mode 3 (SS)
) dly_mpix_use_i ( ) dly_mpix_use_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h6), // input[3:0] /// .dly (4'h6), // input[3:0]
.dly (4'h7), // input[3:0]
.din (mpix_use), // input[0:0] .din (mpix_use), // input[0:0]
.dout (mpix_use_d) // output[0:0] .dout (mpix_use_d) // output[0:0]
); );
...@@ -338,7 +343,8 @@ D11 - negate for mode 3 (SS) ...@@ -338,7 +343,8 @@ D11 - negate for mode 3 (SS)
) dly_mpix_sgn_i ( ) dly_mpix_sgn_i (
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.dly (4'h6), // input[3:0] /// .dly (4'h6), // input[3:0]
.dly (4'h7), // input[3:0]
.din (mpix_sgn_w), // input[0:0] .din (mpix_sgn_w), // input[0:0]
.dout (mpix_sgn_d) // output[0:0] .dout (mpix_sgn_d) // output[0:0]
); );
......
dsp/mclt_test_01.tf
View file @ ed27aded
...@@ -91,7 +91,12 @@ module mclt_test_01 (); ...@@ -91,7 +91,12 @@ module mclt_test_01 ();
reg [3:0] java_wnd_signs[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task reg [3:0] java_wnd_signs[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [7:0] java_fold_index[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task reg [7:0] java_fold_index[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [WND_WIDTH - 1:0] java_tiles_wnd[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task reg [WND_WIDTH - 1:0] java_tiles_wnd[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [WND_WIDTH - 1:0] tiles_wnd[0:1023]; reg [WND_WIDTH - 1:0] tiles_wnd[0:1023];
reg [DTT_IN_WIDTH - 1:0] java_dtt_in[0:1023];
integer i, n, n_out; integer i, n, n_out;
initial begin initial begin
$readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs); $readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs);
...@@ -109,6 +114,12 @@ module mclt_test_01 (); ...@@ -109,6 +114,12 @@ module mclt_test_01 ();
for (i=0; i<256; i=i+1) begin for (i=0; i<256; i=i+1) begin
tiles_wnd['h000 + i] = java_tiles_wnd[i]; tiles_wnd['h000 + i] = java_tiles_wnd[i];
end end
$readmemh("input_data/clt_dtt_in_00_2_x1489_y951.dat",java_dtt_in0);
for (i=0; i<256; i=i+1) begin
java_dtt_in['h000 + i] = java_dtt_in0[i];
end
$readmemh("input_data/tile_02.dat",tile_shift); $readmemh("input_data/tile_02.dat",tile_shift);
shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0]; shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
...@@ -228,7 +239,7 @@ module mclt_test_01 (); ...@@ -228,7 +239,7 @@ module mclt_test_01 ();
end end
integer n1, cntr1, diff1; integer n1, cntr1, diff1;// SuppressThisWarning VEditor : assigned in $readmem() system task
wire [7:0] mpix_a_w = mclt16x16_i.mpix_a_w; wire [7:0] mpix_a_w = mclt16x16_i.mpix_a_w;
wire [7:0] java_fi_w = java_fold_index[cntr1]; wire [7:0] java_fi_w = java_fold_index[cntr1];
initial begin initial begin
...@@ -244,7 +255,7 @@ module mclt_test_01 (); ...@@ -244,7 +255,7 @@ module mclt_test_01 ();
end end
end end
integer n2, cntr2, diff2, diff2a; integer n2, cntr2, diff2, diff2a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r; wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r;
// reg [7:0] java_fi_r; // reg [7:0] java_fi_r;
wire [WND_WIDTH-1:0] java_window_w = java_tiles_wnd[cntr2]; // tiles_wnd[n2 * 256 + cntr2]; wire [WND_WIDTH-1:0] java_window_w = java_tiles_wnd[cntr2]; // tiles_wnd[n2 * 256 + cntr2];
...@@ -262,6 +273,55 @@ module mclt_test_01 (); ...@@ -262,6 +273,55 @@ module mclt_test_01 ();
end end
end end
//Compare window signs
integer n3, cntr3, diff3; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [3:0] mpix_sgn_w = mclt16x16_i.mpix_sgn_w; // SuppressThisWarning VEditor : assigned in $readmem() system task
// wire [3:0] java_sgn_w = java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task
// wire [3:0] java_sgn_w1 = java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [3:0] java_sgn_w = { //java_wnd_signs[java_fold_index[cntr3]]; // SuppressThisWarning VEditor : assigned in $readmem() system task
java_wnd_signs[{2'b11,cntr3[7:2]}][cntr3[1:0]],
java_wnd_signs[{2'b10,cntr3[7:2]}][cntr3[1:0]],
java_wnd_signs[{2'b01,cntr3[7:2]}][cntr3[1:0]],
java_wnd_signs[{2'b00,cntr3[7:2]}][cntr3[1:0]]
};
initial begin
while (RST) @(negedge CLK);
for (n3 = 0; n3 < 4; n3 = n3+1) begin
while (mclt16x16_i.in_cntr != 2) begin
@(negedge CLK);
end
for (cntr3 = 0; cntr3 < 256; cntr3 = cntr3 + 1) begin
#1;
diff3 = mpix_sgn_w - java_sgn_w; // java_fold_index[cntr1];
@(negedge CLK);
end
end
end
//Compare DTT inputs
// reg [DTT_IN_WIDTH - 1:0] java_dtt_in0[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_i.data_dtt_in;
// reg [7:0] java_fi_r;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]; // java_dtt_in[n2 * 256 + cntr2];
initial begin
while (RST) @(negedge CLK);
for (n4 = 0; n4 < 4; n4 = n4+1) begin
while (mclt16x16_i.in_cntr != 16) begin
@(negedge CLK);
end
for (cntr4 = 0; cntr4 < 256; cntr4 = cntr4 + 1) begin
#1;
diff4 = data_dtt_in - java_data_dtt_in;
if (n2 < 1) diff4a = data_dtt_in - java_data_dtt_in; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
mclt16x16 #( mclt16x16 #(
......
mclt_test_01.sav
View file @ ed27aded
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Dec 16 19:54:45 2017 [*] Sun Dec 17 07:54:42 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171215180909701.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171216233340576.fst"
[dumpfile_mtime] "Sat Dec 16 01:09:12 2017" [dumpfile_mtime] "Sun Dec 17 06:33:43 2017"
[dumpfile_size] 940154 [dumpfile_size] 1133363
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
[timestart] 394400 [timestart] 248000
[size] 1814 1171 [size] 1814 1171
[pos] -1 -1 [pos] -1 -1
*-15.197140 538600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-16.313055 499800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_01. [treeopen] mclt_test_01.
[treeopen] mclt_test_01.mclt16x16_i. [treeopen] mclt_test_01.mclt16x16_i.
[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i. [treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i.
[sst_width] 242 [sst_width] 242
[signals_width] 251 [signals_width] 285
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 344 [sst_vpaned_height] 344
@800200 @800200
...@@ -50,6 +50,7 @@ mclt_test_01.pre_last_out ...@@ -50,6 +50,7 @@ mclt_test_01.pre_last_out
mclt_test_01.n1 mclt_test_01.n1
mclt_test_01.cntr1 mclt_test_01.cntr1
@22 @22
mclt_test_01.mpix_a_w[7:0]
mclt_test_01.java_fi_w[7:0] mclt_test_01.java_fi_w[7:0]
@420 @420
[color] 2 [color] 2
...@@ -63,7 +64,36 @@ mclt_test_01.java_window_w[17:0] ...@@ -63,7 +64,36 @@ mclt_test_01.java_window_w[17:0]
mclt_test_01.diff2 mclt_test_01.diff2
mclt_test_01.diff2a mclt_test_01.diff2a
@8420 @8420
[color] 2
mclt_test_01.diff2a mclt_test_01.diff2a
@420
mclt_test_01.n3
mclt_test_01.cntr3
@22
mclt_test_01.mpix_sgn_w[3:0]
@c00022
mclt_test_01.java_sgn_w[3:0]
@28
(0)mclt_test_01.java_sgn_w[3:0]
(1)mclt_test_01.java_sgn_w[3:0]
(2)mclt_test_01.java_sgn_w[3:0]
(3)mclt_test_01.java_sgn_w[3:0]
@1401200
-group_end
@420
[color] 2
mclt_test_01.diff3
mclt_test_01.n4
mclt_test_01.cntr4
@22
mclt_test_01.data_dtt_in[24:0]
mclt_test_01.java_data_dtt_in[24:0]
@8421
mclt_test_01.data_dtt_in[24:0]
mclt_test_01.java_data_dtt_in[24:0]
@420
mclt_test_01.diff4
mclt_test_01.diff4a
@1000200 @1000200
-top -top
@800200 @800200
...@@ -99,6 +129,9 @@ mclt_test_01.mclt16x16_i.mpix_use ...@@ -99,6 +129,9 @@ mclt_test_01.mclt16x16_i.mpix_use
@22 @22
mclt_test_01.mclt16x16_i.window_w[17:0] mclt_test_01.mclt16x16_i.window_w[17:0]
mclt_test_01.mclt16x16_i.window_r[17:0] mclt_test_01.mclt16x16_i.window_r[17:0]
@28
mclt_test_01.mclt16x16_i.mpixel_re
@22
mclt_test_01.mclt16x16_i.mpixel_a[7:0] mclt_test_01.mclt16x16_i.mpixel_a[7:0]
mclt_test_01.mclt16x16_i.mpixel_d[15:0] mclt_test_01.mclt16x16_i.mpixel_d[15:0]
mclt_test_01.mclt16x16_i.mpixel_d_r[15:0] mclt_test_01.mclt16x16_i.mpixel_d_r[15:0]
...@@ -133,7 +166,7 @@ mclt_test_01.mclt16x16_i.i_mclt_fold_rom.data_out_a[17:0] ...@@ -133,7 +166,7 @@ mclt_test_01.mclt16x16_i.i_mclt_fold_rom.data_out_a[17:0]
- -
@1401200 @1401200
-fold_rom -fold_rom
@800200 @c00200
-mclt_wnd_mul -mclt_wnd_mul
@28 @28
mclt_test_01.mclt16x16_i.mclt_wnd_i.en mclt_test_01.mclt16x16_i.mclt_wnd_i.en
...@@ -207,9 +240,8 @@ mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord_out[9:0] ...@@ -207,9 +240,8 @@ mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord_out[9:0]
- -
@1401200 @1401200
-mclt_full_shift_x -mclt_full_shift_x
@1000200
-mclt_wnd_mul -mclt_wnd_mul
@c08023 @c08022
mclt_test_01.mclt16x16_i.window_r[17:0] mclt_test_01.mclt16x16_i.window_r[17:0]
@28 @28
(0)mclt_test_01.mclt16x16_i.window_r[17:0] (0)mclt_test_01.mclt16x16_i.window_r[17:0]
...@@ -230,27 +262,10 @@ mclt_test_01.mclt16x16_i.window_r[17:0] ...@@ -230,27 +262,10 @@ mclt_test_01.mclt16x16_i.window_r[17:0]
(15)mclt_test_01.mclt16x16_i.window_r[17:0] (15)mclt_test_01.mclt16x16_i.window_r[17:0]
(16)mclt_test_01.mclt16x16_i.window_r[17:0] (16)mclt_test_01.mclt16x16_i.window_r[17:0]
(17)mclt_test_01.mclt16x16_i.window_r[17:0] (17)mclt_test_01.mclt16x16_i.window_r[17:0]
@1401201 @1401200
-group_end -group_end
@8022 @8022
mclt_test_01.mclt16x16_i.mpixel_d_r[15:0] mclt_test_01.mclt16x16_i.mpixel_d_r[15:0]
@c00022
mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
@28
(0)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
(1)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
(2)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
(3)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
@1401200
-group_end
@8420
mclt_test_01.mclt16x16_i.data_cc_r[24:0]
mclt_test_01.mclt16x16_i.data_cs_w1[24:0]
mclt_test_01.mclt16x16_i.data_cs_r[24:0]
mclt_test_01.mclt16x16_i.data_sc_r[24:0]
mclt_test_01.mclt16x16_i.data_ss_r[24:0]
mclt_test_01.mclt16x16_i.data_sc_w0[24:0]
mclt_test_01.mclt16x16_i.data_ss_w2[24:0]
@c08420 @c08420
mclt_test_01.mclt16x16_i.pix_wnd_r[33:0] mclt_test_01.mclt16x16_i.pix_wnd_r[33:0]
@28 @28
...@@ -292,12 +307,45 @@ mclt_test_01.mclt16x16_i.pix_wnd_r[33:0] ...@@ -292,12 +307,45 @@ mclt_test_01.mclt16x16_i.pix_wnd_r[33:0]
-group_end -group_end
@8420 @8420
mclt_test_01.mclt16x16_i.pix_wnd_r2[24:0] mclt_test_01.mclt16x16_i.pix_wnd_r2[24:0]
@c00200
-mpix_
@28
mclt_test_01.mclt16x16_i.mpix_use
mclt_test_01.mclt16x16_i.mpix_use_d
@22
mclt_test_01.mclt16x16_i.mpix_sgn_w[3:0]
mclt_test_01.mclt16x16_i.mpix_sgn_d[3:0]
@28 @28
mclt_test_01.mclt16x16_i.var_first_d mclt_test_01.mclt16x16_i.var_first_d
mclt_test_01.mclt16x16_i.var_first_r @1401200
-mpix_
@28
mclt_test_01.mclt16x16_i.mpix_use_r
@c00022
mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
@28
(0)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
(1)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
(2)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
(3)mclt_test_01.mclt16x16_i.mpix_sgn_r[3:0]
@1401200
-group_end
@28
mclt_test_01.mclt16x16_i.var_last mclt_test_01.mclt16x16_i.var_last
@8022 @8022
mclt_test_01.mclt16x16_i.data_cc_r[24:0]
mclt_test_01.mclt16x16_i.data_sc_r[24:0]
mclt_test_01.mclt16x16_i.data_cs_r[24:0]
mclt_test_01.mclt16x16_i.data_ss_r[24:0]
mclt_test_01.mclt16x16_i.data_sc_w0[24:0]
mclt_test_01.mclt16x16_i.data_cs_w1[24:0]
mclt_test_01.mclt16x16_i.data_ss_w2[24:0]
@28
mclt_test_01.mclt16x16_i.var_first_r
@8022
mclt_test_01.mclt16x16_i.mode_mux[1:0] mclt_test_01.mclt16x16_i.mode_mux[1:0]
@22
mclt_test_01.mclt16x16_i.data_dtt_in[24:0]
@8420 @8420
mclt_test_01.mclt16x16_i.data_dtt_in[24:0] mclt_test_01.mclt16x16_i.data_dtt_in[24:0]
@28 @28
......
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