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Elphel
x393
Commits
e6cbe171
Commit
e6cbe171
authored
Feb 02, 2015
by
Andrey Filippov
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Plain Diff
continue on mcntrl393, fixing some bugs too
parent
94f77f4d
Changes
4
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4 changed files
with
593 additions
and
200 deletions
+593
-200
mcntrl393.v
memctrl/mcntrl393.v
+538
-148
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+3
-3
memctrl16.v
memctrl/memctrl16.v
+42
-42
mcont_to_chnbuf_reg.v
util_modules/mcont_to_chnbuf_reg.v
+10
-7
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memctrl/mcntrl393.v
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e6cbe171
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memctrl/mcntrl_ps_pio.v
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e6cbe171
memctrl/memctrl16.v
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e6cbe171
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util_modules/mcont_to_chnbuf_reg.v
View file @
e6cbe171
...
@@ -30,10 +30,10 @@ parameter CHN_NUMBER=0
...
@@ -30,10 +30,10 @@ parameter CHN_NUMBER=0
input
[
3
:
0
]
ext_buf_wchn
,
// ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input
[
3
:
0
]
ext_buf_wchn
,
// ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input
[
63
:
0
]
ext_buf_wdata
,
// valid with ext_buf_wr
input
[
63
:
0
]
ext_buf_wdata
,
// valid with ext_buf_wr
input
seq_done
,
// sequence done
input
seq_done
,
// sequence done
output
reg
buf_done
,
//
sequence done for the specified channel
output
reg
buf_done
,
// @ posedge mclk
sequence done for the specified channel
output
reg
buf_wr_chn
,
output
reg
buf_wr_chn
,
// @ negedge mclk
output
reg
[
6
:
0
]
buf_waddr_chn
,
output
reg
[
6
:
0
]
buf_waddr_chn
,
// @ negedge mclk
output
reg
[
63
:
0
]
buf_wdata_chn
output
reg
[
63
:
0
]
buf_wdata_chn
// @ negedge mclk
)
;
)
;
reg
buf_chn_sel
;
reg
buf_chn_sel
;
always
@
(
posedge
rst
or
negedge
clk
)
begin
always
@
(
posedge
rst
or
negedge
clk
)
begin
...
@@ -42,11 +42,14 @@ parameter CHN_NUMBER=0
...
@@ -42,11 +42,14 @@ parameter CHN_NUMBER=0
if
(
rst
)
buf_wr_chn
<=
0
;
if
(
rst
)
buf_wr_chn
<=
0
;
else
buf_wr_chn
<=
buf_chn_sel
&&
ext_buf_wr
;
else
buf_wr_chn
<=
buf_chn_sel
&&
ext_buf_wr
;
end
always
@
(
posedge
rst
or
posedge
clk
)
begin
if
(
rst
)
buf_done
<=
0
;
if
(
rst
)
buf_done
<=
0
;
else
buf_done
<=
buf_chn_sel
&&
seq_done
;
else
buf_done
<=
buf_chn_sel
&&
seq_done
;
end
end
always
@
(
negedge
clk
)
if
(
buf_chn_sel
&&
ext_buf_wr
)
begin
always
@
(
negedge
clk
)
if
(
buf_chn_sel
&&
ext_buf_wr
)
begin
buf_waddr_chn
<=
ext_buf_waddr
;
buf_waddr_chn
<=
ext_buf_waddr
;
buf_wdata_chn
<=
ext_buf_wdata
;
buf_wdata_chn
<=
ext_buf_wdata
;
...
...
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