Commit e6cbe171 authored by Andrey Filippov's avatar Andrey Filippov

continue on mcntrl393, fixing some bugs too

parent 94f77f4d
This diff is collapsed.
...@@ -22,9 +22,9 @@ ...@@ -22,9 +22,9 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module mcntrl_ps_pio#( module mcntrl_ps_pio#(
parameter MCNTRL_PS_ADDR= 'h100, parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1 parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2, parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0, parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1, parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2 parameter MCNTRL_PS_STATUS_CNTRL= 'h2
......
This diff is collapsed.
...@@ -28,12 +28,12 @@ parameter CHN_NUMBER=0 ...@@ -28,12 +28,12 @@ parameter CHN_NUMBER=0
input ext_buf_wr, input ext_buf_wr,
input [6:0] ext_buf_waddr, // valid with ext_buf_wr input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input [63:0] ext_buf_wdata, // valid with ext_buf_wr input [63:0] ext_buf_wdata, // valid with ext_buf_wr
input seq_done, // sequence done input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel output reg buf_done, // @ posedge mclk sequence done for the specified channel
output reg buf_wr_chn, output reg buf_wr_chn, // @ negedge mclk
output reg [6:0] buf_waddr_chn, output reg [6:0] buf_waddr_chn, // @ negedge mclk
output reg [63:0] buf_wdata_chn output reg [63:0] buf_wdata_chn // @ negedge mclk
); );
reg buf_chn_sel; reg buf_chn_sel;
always @ (posedge rst or negedge clk) begin always @ (posedge rst or negedge clk) begin
...@@ -42,11 +42,14 @@ parameter CHN_NUMBER=0 ...@@ -42,11 +42,14 @@ parameter CHN_NUMBER=0
if (rst) buf_wr_chn <= 0; if (rst) buf_wr_chn <= 0;
else buf_wr_chn <= buf_chn_sel && ext_buf_wr; else buf_wr_chn <= buf_chn_sel && ext_buf_wr;
end
always @ (posedge rst or posedge clk) begin
if (rst) buf_done <= 0; if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done; else buf_done <= buf_chn_sel && seq_done;
end end
always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
buf_waddr_chn <= ext_buf_waddr; buf_waddr_chn <= ext_buf_waddr;
buf_wdata_chn <= ext_buf_wdata; buf_wdata_chn <= ext_buf_wdata;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment