Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Commits
dcc5752f
Commit
dcc5752f
authored
Feb 06, 2015
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
finishing initial mcntrl393.v
parent
ecd4a509
Changes
5
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
369 additions
and
192 deletions
+369
-192
cmd_encod_tiled_mux.v
memctrl/cmd_encod_tiled_mux.v
+111
-86
cmd_encod_tiled_rd.v
memctrl/cmd_encod_tiled_rd.v
+7
-3
mcntrl393.v
memctrl/mcntrl393.v
+200
-42
mcntrl_linear_rw.v
memctrl/mcntrl_linear_rw.v
+10
-10
mcntrl_tiled_rw.v
memctrl/mcntrl_tiled_rw.v
+41
-51
No files found.
memctrl/cmd_encod_tiled_mux.v
View file @
dcc5752f
This diff is collapsed.
Click to expand it.
memctrl/cmd_encod_tiled_rd.v
View file @
dcc5752f
...
...
@@ -34,7 +34,9 @@ module cmd_encod_tiled_rd #(
parameter
COLADDR_NUMBER
=
10
,
// parameter MIN_COL_INC= 3, // minimal number of zero column bits when incrementing row (after bank)
parameter
CMD_PAUSE_BITS
=
10
,
parameter
CMD_DONE_BIT
=
10
// VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter
CMD_DONE_BIT
=
10
,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter
FRAME_WIDTH_BITS
=
13
// Maximal frame width - 8-word (16 bytes) bursts
)
(
input
rst
,
input
clk
,
...
...
@@ -44,7 +46,8 @@ module cmd_encod_tiled_rd #(
input
[
2
:
0
]
start_bank
,
// bank address
input
[
ADDRESS_NUMBER
-
1
:
0
]
start_row
,
// memory row
input
[
COLADDR_NUMBER
-
4
:
0
]
start_col
,
// start memory column in 8-bit bursts
input
[
ADDRESS_NUMBER
+
COLADDR_NUMBER
-
4
:
0
]
rowcol_inc_in
,
// increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
// input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input
[
FRAME_WIDTH_BITS
:
0
]
rowcol_inc_in
,
// increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input
[
5
:
0
]
num_rows_in_m1
,
// number of rows to read minus 1
input
[
5
:
0
]
num_cols_in_m1
,
// number of 16-pixel columns to read (rows first, then columns) - 1
input
keep_open_in
,
// keep banks open (for <=8 banks only
...
...
@@ -85,7 +88,8 @@ module cmd_encod_tiled_rd #(
reg
[
2
:
0
]
bank
;
// memory bank;
reg
[
5
:
0
]
num_rows_m1
;
// number of rows in a tile minus 1
reg
[
5
:
0
]
num_cols128_m1
;
// number of r16-byte columns in a tile -1
reg
[
FULL_ADDR_NUMBER
-
4
:
0
]
rowcol_inc
;
// increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
// reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg
[
FRAME_WIDTH_BITS
:
0
]
rowcol_inc
;
// increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg
keep_open
;
reg
skip_next_page
;
...
...
memctrl/mcntrl393.v
View file @
dcc5752f
This diff is collapsed.
Click to expand it.
memctrl/mcntrl_linear_rw.v
View file @
dcc5752f
...
...
@@ -40,10 +40,11 @@ module mcntrl_linear_rw #(
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter
MCNTRL_SCANLINE_STATUS_REG_ADDR
=
'h4
,
parameter
MCNTRL_SCANLINE_PENDING_CNTR_BITS
=
2
// Number of bits to count pending trasfers, currently 2 is enough, but may increase
parameter
MCNTRL_SCANLINE_PENDING_CNTR_BITS
=
2
,
// Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter
MCNTRL_SCANLINE_WRITE_MODE
=
1'b0
// module is configured to write tiles to external memory (false - read tiles)
)(
input
rst
,
input
mclk
,
...
...
@@ -91,7 +92,6 @@ module mcntrl_linear_rw #(
reg
[
NUM_RC_BURST_BITS
-
1
:
0
]
start_addr_r
;
// 22 bit - to be absorbed by DSP
reg
[
2
:
0
]
bank_reg
[
2
:
0
]
;
wire
[
FRAME_WIDTH_BITS
+
FRAME_HEIGHT_BITS
-
3
:
0
]
mul_rslt_w
;
// wire [2:0] cur_bank;
reg
[
FRAME_WIDTH_BITS
:
0
]
row_left
;
// number of 8-bursts left in the current row
reg
last_in_row
;
reg
[
COLADDR_NUMBER
-
3
:
0
]
mem_page_left
;
// number of 8-bursts left in the pointed memory page
...
...
@@ -103,11 +103,10 @@ module mcntrl_linear_rw #(
wire
calc_valid
;
// calculated registers have valid values
wire
chn_en
;
// enable requests by channle (continue ones in progress)
wire
chn_rst
;
// resets command, including fifo;
// reg [1:0] xfer_page_r;
reg
xfer_reset_page_r
;
reg
[
2
:
0
]
page_cntr
;
wire
cmd_wrmem
;
// 0: read from memory, 1:write to memory
wire
cmd_wrmem
=
MCNTRL_SCANLINE_WRITE_MODE
;
// 0: read from memory, 1:write to memory
wire
[
1
:
0
]
cmd_extra_pages
;
// external module needs more than 1 page
reg
busy_r
;
reg
want_r
;
...
...
@@ -137,7 +136,8 @@ module mcntrl_linear_rw #(
wire
msw_zero
=
!
cmd_data
[
31
:
16
]
;
// MSW all bits are 0 - set carry bit
reg
[
4
:
0
]
mode_reg
;
//mode register: {extra_pages[1:0],write_mode,enable,!reset}
// reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write_mode,enable,!reset}
reg
[
3
:
0
]
mode_reg
;
//mode register: {extra_pages[1:0],write_mode,enable,!reset}
reg
[
NUM_RC_BURST_BITS
-
1
:
0
]
start_addr
;
// (programmed) Frame start (in {row,col8} in burst8, bank ==0
// reg [FRAME_WIDTH_BITS:0] frame_width; // (programmed) 0- max
...
...
@@ -163,7 +163,7 @@ module mcntrl_linear_rw #(
// Sett parameter registers
always
@
(
posedge
rst
or
posedge
mclk
)
begin
if
(
rst
)
mode_reg
<=
0
;
else
if
(
set_mode_w
)
mode_reg
<=
cmd_data
[
4
:
0
]
;
else
if
(
set_mode_w
)
mode_reg
<=
cmd_data
[
3
:
0
]
;
// [
4:0];
if
(
rst
)
start_addr
<=
0
;
else
if
(
set_start_addr_w
)
start_addr
<=
cmd_data
[
NUM_RC_BURST_BITS
-
1
:
0
]
;
...
...
@@ -213,8 +213,8 @@ module mcntrl_linear_rw #(
assign
line_unfinished
=
line_unfinished_r
[
1
]
;
assign
chn_en
=
&
mode_reg
[
1
:
0
]
;
// enable requests by channle (continue ones in progress)
assign
chn_rst
=
~
mode_reg
[
0
]
;
// resets command, including fifo;
assign
cmd_
wrmem
=
mode_reg
[
2
]
;
// 0: read from memory, 1:write to memory
assign
cmd_extra_pages
=
mode_reg
[
4
:
3
]
;
// external module needs more than 1 page
assign
cmd_
extra_pages
=
mode_reg
[
3
:
2
]
;
// external module needs more than 1 page
// assign cmd_wrmem = mode_reg[4];// 0: read from memory, 1:write to memory
assign
status_data
=
{
1'b0
,
busy_r
};
// TODO: Add second bit?
assign
pgm_param_w
=
cmd_we
;
...
...
@@ -266,8 +266,8 @@ module mcntrl_linear_rw #(
else
if
(
chn_rst
||
xfer_grant
)
want_r
<=
0
;
else
if
(
pre_want
&&
(
page_cntr
>{
1'b0
,
cmd_extra_pages
}
))
want_r
<=
1
;
if
(
rst
)
page_cntr
<=
0
;
else
if
(
frame_start
)
page_cntr
<=
cmd_wrmem
?
0
:
4
;
if
(
rst
)
page_cntr
<=
0
;
else
if
(
frame_start
)
page_cntr
<=
cmd_wrmem
?
0
:
4
;
else
if
(
xfer_start_r
[
0
]
&&
!
next_page
)
page_cntr
<=
page_cntr
+
1
;
else
if
(
!
xfer_start_r
[
0
]
&&
next_page
)
page_cntr
<=
page_cntr
-
1
;
...
...
memctrl/mcntrl_tiled_rw.v
View file @
dcc5752f
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment