Commit dcc5752f authored by Andrey Filippov's avatar Andrey Filippov

finishing initial mcntrl393.v

parent ecd4a509
......@@ -24,201 +24,224 @@
module cmd_encod_tiled_mux #(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10
parameter COLADDR_NUMBER= 10,
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
// parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6 // number of bits to specify maximal tile (height-1) (6 -> 64)
) (
input clk,
`ifdef def_tiled_chn0
input [2:0] bank0, // bank address
input [ADDRESS_NUMBER-1:0] row0, // memory row
input [COLADDR_NUMBER-4:0] col0, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc0, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows0, // number of rows to read minus 1
input [5:0] num_cols0, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc0, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows0, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols0, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open0, // keep banks open (for <=8 banks only
input partial0, // first of the two halves of a split tile (caused by memory page crossing)
input start0, // start generating commands
`endif
`ifdef def_tiled_chn1
input [2:0] bank1, // bank address
input [ADDRESS_NUMBER-1:0] row1, // memory row
input [COLADDR_NUMBER-4:0] col1, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc1, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows1, // number of rows to read minus 1
input [5:0] num_cols1, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc1, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows1, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open1, // keep banks open (for <=8 banks only
input partial1, // first of the two halves of a split tile (caused by memory page crossing)
input start1, // start generating commands
`endif
`ifdef def_tiled_chn2
input [2:0] bank2, // bank address
input [ADDRESS_NUMBER-1:0] row2, // memory row
input [COLADDR_NUMBER-4:0] col2, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc2, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows2, // number of rows to read minus 1
input [5:0] num_cols2, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc2, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows2, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols2, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open2, // keep banks open (for <=8 banks only
input partial2, // first of the two halves of a split tile (caused by memory page crossing)
input start2, // start generating commands
`endif
`ifdef def_tiled_chn3
input [2:0] bank3, // bank address
input [ADDRESS_NUMBER-1:0] row3, // memory row
input [COLADDR_NUMBER-4:0] col3, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc3, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows3, // number of rows to read minus 1
input [5:0] num_cols3, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc3, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows3, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols3, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open3, // keep banks open (for <=8 banks only
input partial3, // first of the two halves of a split tile (caused by memory page crossing)
input start3, // start generating commands
`endif
`ifdef def_tiled_chn4
input [2:0] bank4, // bank address
input [ADDRESS_NUMBER-1:0] row4, // memory row
input [COLADDR_NUMBER-4:0] col4, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc4, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows4, // number of rows to read minus 1
input [5:0] num_cols4, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open4, // keep banks open (for <=8 banks only
input [FRAME_WIDTH_BITS:0] rowcol_inc4, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows4, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols4, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open4, // keep banks open (for <=8 banks only
input partial4, // first of the two halves of a split tile (caused by memory page crossing)
input start4, // start generating commands
`endif
`ifdef def_tiled_chn5
input [2:0] bank5, // bank address
input [ADDRESS_NUMBER-1:0] row5, // memory row
input [COLADDR_NUMBER-4:0] col5, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc5, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows5, // number of rows to read minus 1
input [5:0] num_cols5, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc5, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows5, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols5, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open5, // keep banks open (for <=8 banks only
input partial5, // first of the two halves of a split tile (caused by memory page crossing)
input start5, // start generating commands
`endif
`ifdef def_tiled_chn6
input [2:0] bank6, // bank address
input [ADDRESS_NUMBER-1:0] row6, // memory row
input [COLADDR_NUMBER-4:0] col6, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc6, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows6, // number of rows to read minus 1
input [5:0] num_cols6, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc6, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows6, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols6, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open6, // keep banks open (for <=8 banks only
input partial6, // first of the two halves of a split tile (caused by memory page crossing)
input start6, // start generating commands
`endif
`ifdef def_tiled_chn7
input [2:0] bank7, // bank address
input [ADDRESS_NUMBER-1:0] row7, // memory row
input [COLADDR_NUMBER-4:0] col7, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc7, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows7, // number of rows to read minus 1
input [5:0] num_cols7, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc7, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows7, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols7, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open7, // keep banks open (for <=8 banks only
input partial7, // first of the two halves of a split tile (caused by memory page crossing)
input start7, // start generating commands
`endif
`ifdef def_tiled_chn8
input [2:0] bank8, // bank address
input [ADDRESS_NUMBER-1:0] row8, // memory row
input [COLADDR_NUMBER-4:0] col8, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc8, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows8, // number of rows to read minus 1
input [5:0] num_cols8, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc8, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows8, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols8, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open8, // keep banks open (for <=8 banks only
input partial8, // first of the two halves of a split tile (caused by memory page crossing)
input start8, // start generating commands
`endif
`ifdef def_tiled_chn9
input [2:0] bank9, // bank address
input [ADDRESS_NUMBER-1:0] row9, // memory row
input [COLADDR_NUMBER-4:0] col9, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc9, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows9, // number of rows to read minus 1
input [5:0] num_cols9, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc9, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows9, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols9, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open9, // keep banks open (for <=8 banks only
input start9, // start generating commands
input partial9, // first of the two halves of a split tile (caused by memory page crossing)
input start9, // start generating commands
`endif
`ifdef def_tiled_chn10
input [2:0] bank10, // bank address
input [ADDRESS_NUMBER-1:0] row10, // memory row
input [COLADDR_NUMBER-4:0] col10, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc10, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows10, // number of rows to read minus 1
input [5:0] num_cols10, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc10, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows10, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols10, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open10, // keep banks open (for <=8 banks only
input start10, // start generating commands
input partial10, // first of the two halves of a split tile (caused by memory page crossing)
input start10, // start generating commands
`endif
`ifdef def_tiled_chn11
input [2:0] bank11, // bank address
input [ADDRESS_NUMBER-1:0] row11, // memory row
input [COLADDR_NUMBER-4:0] col11, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc11, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows11, // number of rows to read minus 1
input [5:0] num_cols11, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc11, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows11, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols11, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open11, // keep banks open (for <=8 banks only
input start11, // start generating commands
input partial11, // first of the two halves of a split tile (caused by memory page crossing)
input start11, // start generating commands
`endif
`ifdef def_tiled_chn12
input [2:0] bank12, // bank address
input [ADDRESS_NUMBER-1:0] row12, // memory row
input [COLADDR_NUMBER-4:0] col12, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc12, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows12, // number of rows to read minus 1
input [5:0] num_cols12, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc12, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows12, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols12, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open12, // keep banks open (for <=8 banks only
input start12, // start generating commands
input partial12, // first of the two halves of a split tile (caused by memory page crossing)
input start12, // start generating commands
`endif
`ifdef def_tiled_chn13
input [2:0] bank13, // bank address
input [ADDRESS_NUMBER-1:0] row13, // memory row
input [COLADDR_NUMBER-4:0] col13, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc13, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows13, // number of rows to read minus 1
input [5:0] num_cols13, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc13, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows13, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols13, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open13, // keep banks open (for <=8 banks only
input start13, // start generating commands
input partial13, // first of the two halves of a split tile (caused by memory page crossing)
input start13, // start generating commands
`endif
`ifdef def_tiled_chn14
input [2:0] bank14, // bank address
input [ADDRESS_NUMBER-1:0] row14, // memory row
input [COLADDR_NUMBER-4:0] col14, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc14, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows14, // number of rows to read minus 1
input [5:0] num_cols14, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc14, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows14, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols14, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open14, // keep banks open (for <=8 banks only
input start14, // start generating commands
input partial14, // first of the two halves of a split tile (caused by memory page crossing)
input start14, // start generating commands
`endif
`ifdef def_tiled_chn15
input [2:0] bank15, // bank address
input [ADDRESS_NUMBER-1:0] row15, // memory row
input [COLADDR_NUMBER-4:0] col15, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc15, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows15, // number of rows to read minus 1
input [5:0] num_cols15, // number of 16-pixel columns to read (rows first, then columns) - 1
input [FRAME_WIDTH_BITS:0] rowcol_inc15, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [MAX_TILE_WIDTH-1:0] num_rows15, // number of rows to read minus 1
input [MAX_TILE_HEIGHT-1:0] num_cols15, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open15, // keep banks open (for <=8 banks only
input partial15, // first of the two halves of a split tile (caused by memory page crossing)
input start15, // start generating commands
`endif
output [2:0] bank, // bank address
output [ADDRESS_NUMBER-1:0] row, // memory row
output [COLADDR_NUMBER-4:0] col, // start memory column in 8-bit bursts
output [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
output [5:0] num_rows, // number of rows to read minus 1
output [5:0] num_cols, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // keep banks open (for <=8 banks only
output [FRAME_WIDTH_BITS:0] rowcol_inc, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
output [MAX_TILE_WIDTH-1:0] num_rows, // number of rows to read minus 1
output [MAX_TILE_HEIGHT-1:0] num_cols, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // keep banks open (for <=8 banks only
output partial, // first of the two halves of a split tile (caused by memory page crossing)
output start_rd, // start generating commands in cmd_encod_linear_rd
output start_wr // start generating commands in cmd_encod_linear_wr
);
reg [2:0] bank_r; // bank address
reg [ADDRESS_NUMBER-1:0] row_r; // memory row
reg [COLADDR_NUMBER-4:0] col_r; // start memory column in 8-bit bursts
reg [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_r; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
reg [5:0] num_rows_r; // number of rows to read minus 1
reg [5:0] num_cols_r; // number of 16-pixel columns to read (rows first_r; then columns) - 1
reg keep_open_r; // keep banks open (for <=8 banks only
reg [FRAME_WIDTH_BITS:0] rowcol_inc_r; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
reg [MAX_TILE_WIDTH-1:0] num_rows_r; // number of rows to read minus 1
reg [MAX_TILE_HEIGHT-1:0] num_cols_r; // number of 16-pixel columns to read (rows first_r; then columns) - 1
reg keep_open_r; // keep banks open (for <=8 banks only
reg partial_r; // partial tile
reg start_rd_r; // start generating commands in cmd_encod_linear_rd
reg start_wr_r; // start generating commands in cmd_encod_linear_wr
wire [2:0] bank_w; // bank address
wire [ADDRESS_NUMBER-1:0] row_w; // memory row
wire [COLADDR_NUMBER-4:0] col_w; // start memory column in 8-bit bursts
wire [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_w; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
wire [5:0] num_rows_w; // number of rows to read minus 1
wire [5:0] num_cols_w; // number of 16-pixel columns to read (rows first_r; then columns) - 1
wire keep_open_w; // keep banks open (for <=8 banks only
wire [FRAME_WIDTH_BITS:0] rowcol_inc_w; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
wire [MAX_TILE_WIDTH-1:0] num_rows_w; // number of rows to read minus 1
wire [MAX_TILE_HEIGHT-1:0] num_cols_w; // number of 16-pixel columns to read (rows first_r; then columns) - 1
wire keep_open_w; // keep banks open (for <=8 banks only
wire partial_w; // partila tile (first half)
wire start_rd_w; // start generating commands in cmd_encod_linear_rd
wire start_wr_w; // start generating commands in cmd_encod_linear_wr
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+6+1+2;
localparam PAR_WIDTH=(3)+(ADDRESS_NUMBER)+(COLADDR_NUMBER-3)+(FRAME_WIDTH_BITS+1)+(MAX_TILE_WIDTH)+(MAX_TILE_HEIGHT)+(1)+(1)+(2);
localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0;
assign bank = bank_r;
assign row = row_r;
......@@ -227,6 +250,7 @@ module cmd_encod_tiled_mux #(
assign num_rows = num_rows_r; // number of rows to read minus 1
assign num_cols = num_cols_r; // number of 16-pixel columns to read (rows first_r; then columns) - 1
assign keep_open = keep_open_r; // keep banks open (for <=8 banks only
assign partial = partial_r; // partial tile
assign start_rd = start_rd_r;
assign start_wr = start_wr_r;
localparam [15:0] CHN_RD_MEM={
......@@ -312,54 +336,54 @@ module cmd_encod_tiled_mux #(
`endif
assign {bank_w, row_w, col_w, rowcol_inc_w, num_rows_w, num_cols_w, keep_open_w, start_rd_w, start_wr_w} = 0
assign {bank_w, row_w, col_w, rowcol_inc_w, num_rows_w, num_cols_w, keep_open_w, partial_w, start_rd_w, start_wr_w} = 0
`ifdef def_tiled_chn0
| (start0?{bank0, row0, col0, rowcol_inc0, num_rows0, num_cols0, keep_open0, CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
| (start0?{bank0, row0, col0, rowcol_inc0, num_rows0, num_cols0, keep_open0, partial0, CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn1
| (start1?{bank1, row1, col1, rowcol_inc1, num_rows1, num_cols1, keep_open1, CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
| (start1?{bank1, row1, col1, rowcol_inc1, num_rows1, num_cols1, keep_open1, partial1, CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn2
| (start2?{bank2, row2, col2, rowcol_inc2, num_rows2, num_cols2, keep_open2, CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
| (start2?{bank2, row2, col2, rowcol_inc2, num_rows2, num_cols2, keep_open2, partial2, CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn3
| (start3?{bank3, row3, col3, rowcol_inc3, num_rows3, num_cols3, keep_open3, CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
| (start3?{bank3, row3, col3, rowcol_inc3, num_rows3, num_cols3, keep_open3, partial3, CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn4
| (start4?{bank4, row4, col4, rowcol_inc4, num_rows4, num_cols4, keep_open4, CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
| (start4?{bank4, row4, col4, rowcol_inc4, num_rows4, num_cols4, keep_open4, partial4, CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn5
| (start5?{bank5, row5, col5, rowcol_inc5, num_rows5, num_cols5, keep_open5, CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
| (start5?{bank5, row5, col5, rowcol_inc5, num_rows5, num_cols5, keep_open5, partial5, CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn6
| (start6?{bank6, row6, col6, rowcol_inc6, num_rows6, num_cols6, keep_open6, CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
| (start6?{bank6, row6, col6, rowcol_inc6, num_rows6, num_cols6, keep_open6, partial6, CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn7
| (start7?{bank7, row7, col7, rowcol_inc7, num_rows7, num_cols7, keep_open7, CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
| (start7?{bank7, row7, col7, rowcol_inc7, num_rows7, num_cols7, keep_open7, partial7, CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn8
| (start8?{bank8, row8, col8, rowcol_inc8, num_rows8, num_cols8, keep_open8, CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
| (start8?{bank8, row8, col8, rowcol_inc8, num_rows8, num_cols8, keep_open8, partial8, CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn9
| (start9?{bank9, row9, col9, rowcol_inc9, num_rows9, num_cols9, keep_open9, CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
| (start9?{bank9, row9, col9, rowcol_inc9, num_rows9, num_cols9, keep_open9, partial9, CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn10
| (start10?{bank10, row10, col10, rowcol_inc10, num_rows10, num_cols10, keep_open10, CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
| (start10?{bank10, row10, col10, rowcol_inc10, num_rows10, num_cols10, keep_open10, partial10, CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn11
| (start11?{bank11, row11, col11, rowcol_inc11, num_rows11, num_cols11, keep_open11, CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
| (start11?{bank11, row11, col11, rowcol_inc11, num_rows11, num_cols11, keep_open11, partial11, CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn12
| (start12?{bank12, row12, col12, rowcol_inc12, num_rows12, num_cols12, keep_open12, CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
| (start12?{bank12, row12, col12, rowcol_inc12, num_rows12, num_cols12, keep_open12, partial12, CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn13
| (start13?{bank13, row13, col13, rowcol_inc13, num_rows13, num_cols13, keep_open13, CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
| (start13?{bank13, row13, col13, rowcol_inc13, num_rows13, num_cols13, keep_open13, partial13, CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn14
| (start14?{bank14, row14, col14, rowcol_inc14, num_rows14, num_cols14, keep_open14, CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
| (start14?{bank14, row14, col14, rowcol_inc14, num_rows14, num_cols14, keep_open14, partial14, CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn15
| (start15?{bank15, row15, col15, rowcol_inc15, num_rows15, num_cols15, keep_open15, CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
| (start15?{bank15, row15, col15, rowcol_inc15, num_rows15, num_cols15, keep_open15, partial15, CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
`endif
;
always @ (posedge clk) begin
......@@ -371,6 +395,7 @@ module cmd_encod_tiled_mux #(
num_rows_r <= num_rows_w;
num_cols_r <= num_cols_w;
keep_open_r <= keep_open_w;
partial_r <= partial_w;
end
start_rd_r <= start_rd_w;
start_wr_r <= start_wr_w;
......
......@@ -34,7 +34,9 @@ module cmd_encod_tiled_rd #(
parameter COLADDR_NUMBER= 10,
// parameter MIN_COL_INC= 3, // minimal number of zero column bits when incrementing row (after bank)
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
) (
input rst,
input clk,
......@@ -44,7 +46,8 @@ module cmd_encod_tiled_rd #(
input [2:0] start_bank, // bank address
input [ADDRESS_NUMBER-1:0] start_row, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
// input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [FRAME_WIDTH_BITS:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows_in_m1, // number of rows to read minus 1
input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open_in, // keep banks open (for <=8 banks only
......@@ -85,7 +88,8 @@ module cmd_encod_tiled_rd #(
reg [2:0] bank; // memory bank;
reg [5:0] num_rows_m1; // number of rows in a tile minus 1
reg [5:0] num_cols128_m1; // number of r16-byte columns in a tile -1
reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
// reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg [FRAME_WIDTH_BITS:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg keep_open;
reg skip_next_page;
......
......@@ -177,11 +177,32 @@ module mcntrl393 #(
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2 // Number of bits to count pending trasfers, currently 2 is enough, but may increase
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
) (
input rst_in,
......@@ -246,6 +267,16 @@ module mcntrl393 #(
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn3, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn3, // suspend transfers (from external line number comparator)
// Channel 4 (tiled tes)
input frame_start_chn4, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn4, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn4, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done_chn4, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn4, // suspend transfers (from external line number comparator)
// DDR3 interface
output SDRST, // DDR3 reset (active low)
......@@ -319,7 +350,6 @@ module mcntrl393 #(
// wire rpage_nxt_chn2;
wire buf_wr_chn2;
wire buf_wpage_nxt_chn2;
// wire [6:0] buf_waddr_chn2;
wire [63:0] buf_wdata_chn2;
wire want_rq3;
......@@ -331,20 +361,21 @@ module mcntrl393 #(
wire seq_done3;
wire rpage_nxt_chn3;
wire buf_rd_chn3;
// wire [6:0] buf_raddr_chn3;
wire [63:0] buf_rdata_chn3;
wire want_rq4;
wire need_rq4;
wire channel_pgm_en4;
wire [31:0] seq_data4;
wire seq_wr4;
wire seq_set4;
// wire seq_tiled_start_rd;
wire [31:0] seq_data4x; // may be shared with other channel
wire seq_wr4x; // may be shared with other channel
wire seq_set4x; // may be shared with other channel
wire seq_done4;
wire rpage_nxt_chn4;
wire buf_wr_chn4;
wire buf_wpage_nxt_chn4;
// wire [6:0] buf_waddr_chn4;
wire [63:0] buf_wdata_chn4;
// Command tree - insert register layer if needed
......@@ -356,6 +387,8 @@ module mcntrl393 #(
wire cmd_scanline_chn2_stb;
wire [7:0] cmd_scanline_chn3_ad;
wire cmd_scanline_chn3_stb;
wire [7:0] cmd_tiled_chn4_ad;
wire cmd_tiled_chn4_stb;
// Status tree:
......@@ -375,6 +408,10 @@ module mcntrl393 #(
wire status_scanline_chn3_rq; // PS scanline channel3 (memory read) channels status request
wire status_scanline_chn3_start; // PS scanline channel3 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn4_ad; // PS tiled channel4 (memory read) status byte-wide address/data
wire status_tiled_chn4_rq; // PS tiled channel4 (memory read) channels status request
wire status_tiled_chn4_start; // PS tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
reg select_cmd0;
reg select_buf0;
......@@ -433,6 +470,30 @@ module mcntrl393 #(
// wire [1:0] xfer_page3; // "internal" buffer page
wire xfer_reset_page3; // "internal" buffer page reset, @posedge mclk
wire [2:0] tiled_rd_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rd_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rd_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rd_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rd_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rd_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rd_keep_open; // start generating commands
wire tiled_rd_xfer_partial; // start generating commands
wire tiled_rd_start; // start generating commands
wire [2:0] tiled_rd_chn4_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rd_chn4_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rd_chn4_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rd_chn4_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rd_chn4_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rd_chn4_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rd_chn4_keep_open; // start generating commands
wire tiled_rd_chn4_xfer_partial; // start generating commands
wire tiled_rd_chn4_start; // start generating commands
wire xfer_reset_page4_pos; // "internal" buffer page reset, @posedge mclk
reg xfer_reset_page4_neg; // "internal" buffer page reset, @negedge mclk
// Command tree - insert register layer(s) if needed, now just direct assignments
......@@ -444,6 +505,8 @@ module mcntrl393 #(
assign cmd_scanline_chn2_stb=cmd_stb;
assign cmd_scanline_chn3_ad= cmd_ad;
assign cmd_scanline_chn3_stb=cmd_stb;
assign cmd_tiled_chn4_ad= cmd_ad;
assign cmd_tiled_chn4_stb= cmd_stb;
......@@ -460,6 +523,7 @@ module mcntrl393 #(
assign page_ready_chn2=seq_done2;
assign page_ready_chn3=seq_done3;
assign page_ready_chn4=rpage_nxt_chn4;
always @ (axi_rst or axi_clk) begin
if (axi_rst) select_cmd0 <= 0;
......@@ -507,9 +571,9 @@ module mcntrl393 #(
.db_in3 (status_scanline_chn3_ad), // input[7:0]
.rq_in3 (status_scanline_chn3_rq), // input
.start_in3 (status_scanline_chn3_start), // output
.db_in4 (8'b0), // input[7:0]
.rq_in4 (1'b0), // input
.start_in4 (), // output
.db_in4 (status_tiled_chn4_ad), // input[7:0]
.rq_in4 (status_tiled_chn4_rq), // input
.start_in4 (status_tiled_chn4_start), // output
.db_in5 (8'b0), // input[7:0]
.rq_in5 (1'b0), // input
.start_in5 (), // output
......@@ -548,38 +612,114 @@ module mcntrl393 #(
.rq_out (status_rq), // output
.start_out (status_start) // input
);
//status_ps_pio_start
/* Instance template for module cmd_encod_tiled_mux */
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.MCNTRL_TILED_WRITE_MODE (1'b0)
) mcntrl_tiled_rw_chn4_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn4_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn4_stb), // input
.status_ad (status_tiled_chn4_ad), // output[7:0]
.status_rq (status_tiled_chn4_rq), // output
.status_start (status_tiled_chn4_start), // input
.frame_start (frame_start_chn4), // input
.next_page (next_page_chn4), // input
.frame_done (frame_done_chn4), // output
.line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input
.xfer_want (want_rq4), // output
.xfer_need (need_rq4), // output
.xfer_grant (channel_pgm_en4), // input
.xfer_start (tiled_rd_chn4_start), // output
.xfer_bank (tiled_rd_chn4_bank), // output[2:0]
.xfer_row (tiled_rd_chn4_row), // output[14:0]
.xfer_col (tiled_rd_chn4_col), // output[6:0]
.rowcol_inc (tiled_rd_chn4_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rd_chn4_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rd_chn4_num_cols_m1), // output[5:0]
.keep_open (tiled_rd_chn4_keep_open), // output
.xfer_partial (tiled_rd_chn4_xfer_partial), // output
.xfer_page_done (seq_done4), // input
.xfer_page_rst (xfer_reset_page4_pos) // output
);
cmd_encod_tiled_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER)
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT)
) cmd_encod_tiled_mux_i (
.clk (mclk), // input
.bank4(), // input[2:0]
.row4(), // input[14:0]
.col4(), // input[6:0]
.rowcol_inc4(), // input[21:0]
.num_rows4(), // input[5:0]
.num_cols4(), // input[5:0]
.keep_open4(), // input
.start4(), // input
.bank(), // output[2:0]
.row(), // output[14:0]
.col(), // output[6:0]
.rowcol_inc(), // output[21:0]
.num_rows(), // output[5:0]
.num_cols(), // output[5:0]
.keep_open(), // output
.start_rd(), // output
.start_wr() // output
.bank4 (tiled_rd_chn4_bank), // input[2:0]
.row4 (tiled_rd_chn4_row), // input[14:0]
.col4 (tiled_rd_chn4_col), // input[6:0]
.rowcol_inc4 (tiled_rd_chn4_rowcol_inc), // input[13:0]
.num_rows4 (tiled_rd_chn4_num_rows_m1), // input[5:0]
.num_cols4 (tiled_rd_chn4_num_cols_m1), // input[5:0]
.keep_open4 (tiled_rd_chn4_keep_open), // input
.partial4 (tiled_rd_chn4_xfer_partial), // input
.start4 (tiled_rd_chn4_start), // input
.bank (tiled_rd_bank), // output[2:0]
.row (tiled_rd_row), // output[14:0]
.col (tiled_rd_col), // output[6:0]
.rowcol_inc (tiled_rd_rowcol_inc), // output[13:0]
.num_rows (tiled_rd_num_rows_m1), // output[5:0]
.num_cols (tiled_rd_num_cols_m1), // output[5:0]
.keep_open (tiled_rd_keep_open), // output
.partial (tiled_rd_xfer_partial), // output
.start_rd (tiled_rd_start), // output
.start_wr () // output
);
cmd_encod_tiled_rd #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),