Commit da2d549d authored by Andrey Filippov's avatar Andrey Filippov
Browse files

removed extra debug signals, fixed tools settings after vdt update

parent cbed019c

.project

+8 −8
Original line number Diff line number Diff line
@@ -62,42 +62,42 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150905203536090.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150905202638924.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150905202638924.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150905202638924.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150905202638924.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150905202638924.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150905180655479.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150905202128057.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150905181423920.log</location>

			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150905202638924.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

.settings/com.elphel.vdt.FPGA_project.prefs

+2 −1
Original line number Diff line number Diff line
@@ -2,5 +2,6 @@ FPGA_project_0_SimulationTopFile=x393_testbench02.tf 
FPGA_project_1_SimulationTopModule=x393_testbench02

FPGA_project_2_ImplementationTopFile=x393.v

FPGA_project_4_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->

FPGA_project_5_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->

eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoBitstream.prefs

+2 −1
Original line number Diff line number Diff line
@@ -3,5 +3,6 @@ VivadoBitstream_105_force=true 
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->

VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->

VivadoBitstream_124_force=true

com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->

VivadoBitstream_125_force=true

com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->

eclipse.preferences.version=1

fpga_version.vh

+1 −1
Original line number Diff line number Diff line 
    parameter FPGA_VERSION =          32'h03930015;
 
 No newline at end of file
 
    parameter FPGA_VERSION =          32'h03930016;
 
 No newline at end of file

sensor/sens_histogram.v

+5 −5
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ module sens_histogram #( 
    input   [7:0] cmd_ad,      // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 

    input         cmd_stb,      // strobe (with first byte) for the command a/d

    input         monochrome    // tie to 0 to reduce hardware

    ,output debug_mclk

//    ,output debug_mclk

`ifdef DEBUG_RING       

    ,output                       debug_do, // output to the debug ring

     input                        debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
@@ -137,7 +137,7 @@ module sens_histogram #( 
    reg           hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)

    reg           wait_readout;   // only used in NOBUF mode, in outher modes readout is expected to be always finished in time

    

    reg           debug_vert_woi_r;

//    reg           debug_vert_woi_r;

    

    reg    [15:0] debug_line_cntr;

    reg    [15:0] debug_lines;
@@ -226,7 +226,7 @@ module sens_histogram #( 
        if (!en ||(pre_first_line && !hact))  vert_woi <= 0;

        else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;

        

        debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;

//        debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;

        

//        hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active

        hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
@@ -391,7 +391,7 @@ module sens_histogram #( 
    );

`endif





/*

    pulse_cross_clock pulse_cross_clock_debug_mclk_i (

        .rst         (prst), // input

        .src_clk     (pclk), // input
@@ -402,7 +402,7 @@ module sens_histogram #( 
        .out_pulse   (debug_mclk),    // output

        .busy() // output

    );



*/

    

    cmd_deser #(

        .ADDR        (HISTOGRAM_ADDR),