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Commit cfdcac60 authored by Andrey Filippov's avatar Andrey Filippov
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modifying histograms module to avoid use of the double pixel frequency clock

parent 59774283
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Showing with 1377 additions and 71 deletions
includes/x393_simulation_parameters.vh
View file @ cfdcac60
......@@ -61,7 +61,7 @@
parameter HISTOGRAM_LEFT = 0, // 2; // left
parameter HISTOGRAM_TOP = 8, // 2, // top
parameter HISTOGRAM_WIDTH = 6, // width
parameter HISTOGRAM_WIDTH = 22, // 6, // width
parameter HISTOGRAM_HEIGHT = 6, // height
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
......
sensor/sens_histogram.v
View file @ cfdcac60
......@@ -35,7 +35,6 @@ module sens_histogram #(
`endif
)(
// input rst,
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
......@@ -55,16 +54,12 @@ module sens_histogram #(
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
input monochrome // tie to 0 to reduce hardware
// ,output debug_mclk
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
input debug_di // input from the debug ring
`endif
);
`ifdef DEBUG_RING
// assign debug_do = debug_di;
`endif
localparam PXD_2X_LATENCY = 2;
reg hist_bank_pclk;
......@@ -140,11 +135,10 @@ module sens_histogram #(
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
// reg debug_vert_woi_r;
`ifdef DEBUG_RING
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
`endif
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
......@@ -179,16 +173,14 @@ module sens_histogram #(
reg monochrome_pclk;
reg monochrome_2x;
// assign debug_mclk = hist_done_mclk;
// assign debug_mclk = set_width_height_w;
`ifdef DEBUG_RING
always @ (posedge pclk) begin
if (sof) debug_line_cntr <= 0;
else if (line_start_w) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
end
`endif
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
......@@ -215,7 +207,6 @@ module sens_histogram #(
end
// process WOI
// wire eol = !hact && hact_d[0];
always @ (posedge pclk) begin
hact_d <= {hact_d[0],hact};
if (!en) pre_first_line <= 0;
......@@ -229,9 +220,6 @@ module sens_histogram #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
// debug_vert_woi_r <= vcntr_zero_w && vert_woi; // vert_woi;
// hist_done <= vcntr_zero_w && vert_woi && line_start_w; // hist done never asserted, line_start_w - active
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0;
......@@ -253,8 +241,6 @@ module sens_histogram #(
else if (hcntr_zero_w && left_margin) hcntr <= width_m1;
else if (left_margin || hor_woi) hcntr <= hcntr - 1;
// if (hor_woi) hist_d <= hist_di;
if (!en) hist_bank_pclk <= 0;
else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;
// hist_xfer_busy to extend en
......@@ -279,13 +265,11 @@ module sens_histogram #(
else if (!hact) bayer_pclk[0] <= XOR_HIST_BAYER[0];
else bayer_pclk[0] <= ~bayer_pclk[0];
//line_start_w
end
always @(posedge pclk2x) begin
monochrome_2x <= monochrome;
hist_en_pclk2x <= hist_en;
// hist_rst_pclk2x <= hist_rst;
pxd_ra_start <= left[3:0];
if (!hist_en_pclk2x || hlstart || !(hor_woi_2x || (|woi))) pclk_sync <= 0;
......@@ -306,8 +290,6 @@ module sens_histogram #(
hist_addr_d2 <= hist_addr_d;
same_addr1 <= monochrome_2x && woi[0] && woi[1] && (hist_addr_d == hist_addr); // reduce hardware if hard-wire to gnd
same_addr2 <= woi[0] && woi[2] && (hist_addr_d2 == hist_addr);
// if (same_addr) to_inc <= inc_r;
// else to_inc <= hist_new;
if (same_addr1) to_inc <= inc_r; // only used in monochrome mode
else if (same_addr2) to_inc <= inc_sat;
else to_inc <= hist_new;
......@@ -317,7 +299,6 @@ module sens_histogram #(
else inc_sat <= {14'b0,inc_r[17:0]};
end
hist_rwen <= (woi[0] & ~pclk_sync) || (woi[2] & pclk_sync);
// hist_regen <= {hist_regen[1:0], woi[0] & ~pclk_sync};
hist_regen <= {hist_regen[0], woi[0] & ~pclk_sync};
hist_we <= woi[2] & pclk_sync;
......@@ -326,35 +307,25 @@ module sens_histogram #(
inc_r <= to_inc + 1;
// if (HISTOGRAM_RAM_MODE != "BUF18") inc_r <= inc_w;
// else if (inc_w[18]) inc_r <= 32'h3fff; // maximal value
// else inc_r <= {14'b0,inc_w[17:0]};
end
// after hist_out was off, require inactive grant before sending rq
reg en_rq_start;
always @ (posedge mclk) begin
en_mclk <= en;
monochrome_pclk <= monochrome;
// monochrome_pclk <= monochrome;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
hist_out_d <= hist_out;
// reset address each time new transfer is started
// if (!en_mclk || (hist_out && !hist_out_d)) hist_raddr <= 0;
if (!hist_out) hist_raddr <= 0;
else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
// if (!en_mclk) hist_rq_r <= 0;
// else if (hist_out && !hist_re) hist_rq_r <= 1;
// hist_rq_r <= en_mclk && hist_out && !(&hist_raddr);
// prevent starting rq if grant is still on (back-to-back)
if (!hist_out) en_rq_start <= 0;
else if (!hist_grant) en_rq_start <= 1;
// hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && ((|hist_raddr[9:0]) || !hist_grant);
hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
if (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;
......@@ -372,6 +343,7 @@ module sens_histogram #(
else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1;
else if (hist_xfer_done) wait_readout <= 0;
monochrome_pclk <= monochrome;
end
`ifdef DEBUG_RING
......@@ -386,27 +358,12 @@ module sens_histogram #(
.debug_di (debug_di), // input
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
// .rd_data ({height_m1[15:0], vcntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.rd_data ({debug_lines[15:0], debug_line_cntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
//debug_lines <= debug_line_cntr
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
`endif
/*
pulse_cross_clock pulse_cross_clock_debug_mclk_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (vert_woi && !debug_vert_woi_r), // line_start_w), // input vcntr_zero_w
// .in_pulse (vcntr_zero_w && !debug_vert_woi_r), // line_start_w), // input
.in_pulse (vcntr_zero_w && vert_woi && !debug_vert_woi_r), // line_start_w), // input
.out_pulse (debug_mclk), // output
.busy() // output
);
*/
cmd_deser #(
.ADDR (HISTOGRAM_ADDR),
.ADDR_MASK (HISTOGRAM_ADDR_MASK),
......@@ -474,13 +431,6 @@ module sens_histogram #(
.out_pulse (hist_xfer_done), // output
.busy() // output
);
/*
clk_to_clk2x clk_to_clk2x_i (
.clk (pclk), // input
.clk2x (pclk2x), // input
.clk_sync (pclk_sync) // output
);
*/
//TODO: make it double cycle in timing
// select between 18-bit wide histogram data using a single BRAM or 2 BRAMs having full 32 bits
......
sensor/sens_histogram_snglclk.v 0 → 100644
View file @ cfdcac60
/*******************************************************************************
* Module: sens_histogram_snglclk
* Date:2015-10-21
* Author: Andrey Filippov
* Description: Calculates per-color histogram over the specified rectangular region.
* Modified from the original sens_histogram to avoid using double
* frequency clock
*
* Copyright (c) 2015 Elphel, Inc.
* sens_histogram_snglclk.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_histogram_snglclk.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sens_histogram_snglclk #(
parameter HISTOGRAM_RAM_MODE = "BUF32", // valid: "NOBUF" (32-bits, no buffering - now is replaced by BUF32), "BUF18", "BUF32"
parameter HISTOGRAM_ADDR = 'h33c,
parameter HISTOGRAM_ADDR_MASK = 'h7fe,
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00// 11 // invert bayer setting
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 // SuppressThisWarning VEditor - not used
`endif
)(
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
// input pclk2x,
input sof,
input eof,
input hact,
input [7:0] hist_di, // 8-bit pixel data
input mclk,
input hist_en, // @mclk - gracefully enable/disable histogram
input hist_rst, // @mclk - immediately disable if true
output hist_rq,
input hist_grant,
output [31:0] hist_do,
output reg hist_dv,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb // strobe (with first byte) for the command a/d
// , input monochrome // NOT supported in this implementation - use software to sum
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load // SuppressThisWarning VEditor - not used
input debug_di // input from the debug ring
`endif
);
localparam HIST_WIDTH = (HISTOGRAM_RAM_MODE == "BUF18") ? 18 : 32;
reg hist_bank_pclk;
reg [8:0] hist_rwaddr_even; // {bayer[1], pixel}
reg [8:0] hist_rwaddr_odd; // {bayer[1], pixel}
reg hist_bank_mclk;
wire set_left_top_w;
wire set_width_height_w;
wire [1:0] pio_addr;
wire [31:0] pio_data;
wire pio_stb;
reg [31:0] lt_mclk; // left+top @ posedge mclk
reg [31:0] wh_mclk; // width+height @ posedge mclk
reg [15:0] width_m1; // @posedge pclk
reg [15:0] height_m1; // @posedge pclk
reg [15:0] left; // @posedge pclk
reg [15:0] top; // @posedge pclk
reg hist_en_pclk; // @pclk - gracefully enable/disable histogram
reg hist_rst_pclk; // @pclk - immediately disable if true
reg en;
reg en_new; // @ pclk - enable new frame
reg en_mclk;
wire set_left_top_pclk;
wire set_width_height_pclk;
// reg pclk_sync; // CE for pclk2x, ~=pclk
reg odd_pix;
reg [1:0] bayer_pclk;
reg [1:0] hact_d;
reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle
wire hist_done_mclk;
reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window
// reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
reg [6:0] hor_woi; // vertically in window and delayed
reg [15:0] vcntr; // vertical (line) counter
reg [15:0] hcntr; // horizontal (pixel) counter
wire vcntr_zero_w; // vertical counter is zero
wire hcntr_zero_w; // horizontal counter is zero
reg hist_out; // some data yet to be sent out
reg hist_out_d;
reg [2:0] hist_re;
reg [1:0] hist_re_even_odd;
reg [9:0] hist_raddr;
reg hist_rq_r;
wire hist_xfer_done_mclk; //@ mclk
wire hist_xfer_done; // @pclk
reg hist_xfer_busy; // @pclk, during histogram readout , immediately after woi (no gaps)
reg wait_readout; // only used in NOBUF mode, in outher modes readout is expected to be always finished in time
`ifdef DEBUG_RING
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
`endif
assign set_left_top_w = pio_stb && (pio_addr == HISTOGRAM_LEFT_TOP );
assign set_width_height_w = pio_stb && (pio_addr == HISTOGRAM_WIDTH_HEIGHT );
assign vcntr_zero_w = !(|vcntr);
assign hcntr_zero_w = !(|hcntr);
assign hist_rq = hist_rq_r;
assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en;
wire line_start_w = hact && !hact_d[0]; // // tested active
reg pre_first_line;
reg frame_active; // until done
`ifdef DEBUG_RING
always @ (posedge pclk) begin
if (sof) debug_line_cntr <= 0;
else if (line_start_w) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
end
`endif
/*
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
else pxd_wa <= pxd_wa + 1;
if (!hact) pxd_wa_woi <= -PXD_2X_LATENCY;
else pxd_wa_woi <= pxd_wa_woi + 1;
if (hist_en_pclk && hact) pxd_ram[pxd_wa] <= hist_di;
if (hist_en_pclk && hact) bayer_ram[pxd_wa] <= bayer_pclk;
if (hist_en_pclk && hact_d[1]) woi_ram[pxd_wa_woi] <= hor_woi; // PXD_2X_LATENCY;
end
*/
always @ (posedge mclk) begin
if (set_left_top_w) lt_mclk <= pio_data;
if (set_width_height_w) wh_mclk <= pio_data;
end
always @ (posedge pclk) begin
if (set_left_top_pclk) {top,left} <= lt_mclk[31:0];
if (set_width_height_pclk) {height_m1,width_m1} <= wh_mclk[31:0];
end
// process WOI
always @ (posedge pclk) begin
hact_d <= {hact_d[0],hact};
if (!en) pre_first_line <= 0;
else if (sof && en_new) pre_first_line <= 1;
else if (hact) pre_first_line <= 0;
if (!en) top_margin <= 0;
else if (sof && en_new) top_margin <= 1;
else if (vcntr_zero_w & line_start_w) top_margin <= 0;
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
if (!en || hist_done) frame_active <= 0;
else if (sof && en_new) frame_active <= 1;
if ((pre_first_line && !hact) || !frame_active) vcntr <= top;
else if (line_start_w) vcntr <= vcntr_zero_w ? height_m1 : (vcntr - 1);
if (!frame_active) left_margin <= 0;
else if (!hact_d[0]) left_margin <= 1;
else if (hcntr_zero_w) left_margin <= 0;
// !hact_d[0] to limit by right margin if window is set wrong
if (!vert_woi || wait_readout || !hact_d[0]) hor_woi[0] <= 0; // postpone WOI if reading out/erasing histogram (no-buffer mode)
else if (hcntr_zero_w) hor_woi[0] <= left_margin && vert_woi;
hor_woi[6:1] <= hor_woi[5:0];
if (!hact_d[0]) hcntr <= left;
else if (hcntr_zero_w && left_margin) hcntr <= width_m1;
else if (left_margin || hor_woi[0]) hcntr <= hcntr - 1;
if (!en) hist_bank_pclk <= 0;
else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;
// hist_xfer_busy to extend en
if (!en) hist_xfer_busy <= 0;
else if (hist_xfer_done) hist_xfer_busy <= 0;
else if (vcntr_zero_w && vert_woi) hist_xfer_busy <= 1;
hist_en_pclk <= hist_en;
hist_rst_pclk <= hist_rst;
if (hist_rst_pclk) en <= 0;
else if (hist_en_pclk) en <= 1;
else if (!top_margin && !vert_woi && !hist_xfer_busy) en <= 0;
en_new <= !hist_rst_pclk && hist_en_pclk;
if (!hact && hact_d[0]) bayer_pclk[1] <= !bayer_pclk[1];
else if (pre_first_line && !hact) bayer_pclk[1] <= XOR_HIST_BAYER[1];
if (!hact) bayer_pclk[0] <= XOR_HIST_BAYER[0];
else bayer_pclk[0] <= ~bayer_pclk[0];
end
// assign hlstart = hcntr_zero_w && left_margin && hact_d[0];
reg [6:0] memen_even;
reg [6:0] memen_odd;
wire set_ra_even = memen_even[0];
wire regen_even = memen_even[2];
wire set_wa_even = memen_even[5];
wire we_even = memen_even[6];
wire set_ra_odd = memen_odd[0];
wire regen_odd = memen_odd[2];
wire set_wa_odd = memen_odd[5];
wire we_odd = memen_odd[6];
reg rwen_even; // re or we
reg rwen_odd; // re or we
wire [7:0] px_d0; // px delayed to match hor_woi (2 cycles)
wire [7:0] px_d2; // px delayed by 2 cycles from px_d0
wire [7:0] px_d4; // px delayed by 2 cycles from px_d2
wire [7:0] px_d5; // px delayed by 1 cycle from px_d4
reg [HIST_WIDTH -1 :0] r0;
reg [HIST_WIDTH -1 :0] r1;
reg r1_sat; // only used in 18-bit mode
reg [HIST_WIDTH -1 :0] r2;
reg [HIST_WIDTH -1 :0] r3;
wire [HIST_WIDTH -1 :0] hist_new_even; // data (to increment) read from the histogram memory, even pixels
wire [HIST_WIDTH -1 :0] hist_new_odd; // data (to increment) read from the histogram memory, odd pixels
reg [3:0] r_load; // load r0-r1-r2-r3 registers
reg r0_sel; // select odd/even for r0 (other option possible)
reg eq_prev_prev; // pixel equals one before previous of the same color
wire eq_prev_prev_d2; // eq_prev_prev delayed by 2 clocks to select r1 source
reg eq_prev; // pixel equals previous of the same color
wire eq_prev_d3; // eq_prev delayed by 3 clocks to select r1 source
wire start_hor_woi = hcntr_zero_w && left_margin && vert_woi;
// hist_di is 2 cycles ahead of hor_woi
always @(posedge pclk) begin
if (!hist_en_pclk || !(|hor_woi)) odd_pix <= 0;
else odd_pix <= ~odd_pix;
if (!hist_en_pclk || !((XOR_HIST_BAYER[0] ^ left[0])? hor_woi[1] : hor_woi[0])) memen_even[0] <= 0;
else memen_even[0] <= ~memen_even[0];
memen_even[6:1] <= memen_even[5:0];
if (!hist_en_pclk || !((XOR_HIST_BAYER[0] ^ left[0])? hor_woi[0] : hor_woi[1])) memen_odd[0] <= 0;
else memen_odd[0] <= ~memen_odd[0];
memen_odd[6:1] <= memen_odd[5:0];
if (hor_woi[1:0] == 2'b01) hist_rwaddr_even[8] <= bayer_pclk[1];
if (hor_woi[1:0] == 2'b01) hist_rwaddr_odd[8] <= bayer_pclk[1];
if (set_ra_even) hist_rwaddr_even[7:0] <= px_d0;
else if (set_wa_even) hist_rwaddr_even[7:0] <= px_d5;
if (set_ra_odd) hist_rwaddr_odd[7:0] <= px_d0;
else if (set_wa_odd) hist_rwaddr_odd[7:0] <= px_d5;
rwen_even <= memen_even[0] || memen_even[5];
rwen_odd <= memen_odd[0] || memen_odd[5];
r_load <= {r_load[2:0], regen_even | regen_odd};
r0_sel <= regen_odd;
eq_prev_prev <= hor_woi[4] && (px_d4 == px_d0);
eq_prev <= hor_woi[2] && (px_d2 == px_d0);
if (r_load[0]) r0 <= eq_prev_prev_d2 ? r3 : (r0_sel ? hist_new_odd : hist_new_even);
if (r_load[1]) r1 <= eq_prev_d3 ? r2 : r0;
if (r_load[1]) r1_sat <= eq_prev_d3 ? (&r2) : (&r0);
if (r_load[2]) r2 <= ((HISTOGRAM_RAM_MODE != "BUF18") || !r1_sat) ? (r1 + 1) : r1;
if (r_load[3]) r3 <= r2;
end
// after hist_out was off, require inactive grant before sending rq
reg en_rq_start;
always @ (posedge mclk) begin
en_mclk <= en;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
hist_out_d <= hist_out;
// reset address each time new transfer is started
if (!hist_out) hist_raddr <= 0;
else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
// prevent starting rq if grant is still on (back-to-back)
if (!hist_out) en_rq_start <= 0;
else if (!hist_grant) en_rq_start <= 1;
hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
if (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;
else if (hist_grant) hist_re[0] <= 1;
hist_re[2:1] <= hist_re[1:0];
// reg [2:0] hist_re_even_odd;
if (!hist_out || (&hist_raddr[7:1])) hist_re_even_odd[0] <= 0;
else if (hist_re[0]) hist_re_even_odd[0] <= ~hist_re_even_odd[0];
else if (hist_grant) hist_re_even_odd[0] <= 1; // hist_re[0] == 0 here
if (!en_mclk) hist_bank_mclk <= 0;
else if (hist_xfer_done_mclk && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_mclk <= !hist_bank_mclk;
hist_dv <= hist_re[2];
end
always @ (posedge pclk) begin
if (!en) wait_readout <= 0;
else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1;
else if (hist_xfer_done) wait_readout <= 0;
end
`ifdef DEBUG_RING
debug_slave #(
.SHIFT_WIDTH (64),
.READ_WIDTH (64),
.WRITE_WIDTH (32),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_slave_i (
.mclk (mclk), // input
.mrst (mrst), // input
.debug_di (debug_di), // input
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
.rd_data ({debug_lines[15:0], debug_line_cntr[15:0], width_m1[15:0], hcntr[15:0]}), // input[31:0]
.wr_data (), // output[31:0] - not used
.stb () // output - not used
);
`endif
cmd_deser #(
.ADDR (HISTOGRAM_ADDR),
.ADDR_MASK (HISTOGRAM_ADDR_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (2),
.DATA_WIDTH (32),
.ADDR1 (0),
.ADDR_MASK1 (0),
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_histogram_i (
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (pio_addr), // output[15:0]
.data (pio_data), // output[31:0]
.we (pio_stb) // output
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly0_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h2), // input[3:0]
.din (hist_di), // input[0:0]
.dout (px_d0) // output[0:0]
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly2_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h1), // input[3:0]
.din (px_d0), // input[0:0]
.dout (px_d2) // output[0:0]
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly4_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h1), // input[3:0]
.din (px_d2), // input[0:0]
.dout (px_d4) // output[0:0]
);
dly_16 #(
.WIDTH(8)
) dly_16_px_dly5_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h0), // input[3:0]
.din (px_d4), // input[0:0]
.dout (px_d5) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_eq_prev_prev_d2_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h1), // input[3:0]
.din (eq_prev_prev), // input[0:0]
.dout (eq_prev_prev_d2) // output[0:0]
);
dly_16 #(
.WIDTH(1)
) dly_16_eq_prev_d3_i (
.clk (pclk), // input
.rst (prst), // input
.dly (4'h2), // input[3:0]
.din (eq_prev), // input[0:0]
.dout (eq_prev_d3) // output[0:0]
);
pulse_cross_clock pulse_cross_clock_lt_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_left_top_w), // input
.out_pulse (set_left_top_pclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_wh_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (set_width_height_w), // input
.out_pulse (set_width_height_pclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hist_done_i (
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (hist_done), // input
.out_pulse (hist_done_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hist_xfer_done_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (hist_xfer_done_mclk), // input
.out_pulse (hist_xfer_done), // output
.busy() // output
);
//TODO: make it double cycle in timing
// select between 18-bit wide histogram data using a single BRAM or 2 BRAMs having full 32 bits
generate
if ((HISTOGRAM_RAM_MODE=="BUF32") || (HISTOGRAM_RAM_MODE=="NOBUF"))// impossible to use a two RAMB18E1 32-bit wide
sens_hist_ram_snglclk_32 sens_hist_ram_snglclk_32_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2), // input[31:0]
.data_out_a_even (hist_new_even), // output[31:0]
.data_out_a_odd (hist_new_odd), // output[31:0]
.en_a_even (rwen_even), // input
.en_a_odd (rwen_odd), // input
.regen_a_even (regen_even), // input
.regen_a_odd (regen_odd), // input
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9:1]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_b (hist_re_even_odd[0]) // input
);
else if (HISTOGRAM_RAM_MODE=="BUF18")
sens_hist_ram_snglclk_18 sens_hist_ram_snglclk_18_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2[17:0]), // input[31:0]
.data_out_a_even (hist_new_even[17:0]), // output[31:0]
.data_out_a_odd (hist_new_odd[17:0]), // output[31:0]
.en_a_even (rwen_even), // input
.en_a_odd (rwen_odd), // input
.regen_a_even (regen_even), // input
.regen_a_odd (regen_odd), // input
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9:1]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_b (hist_re_even_odd[0]) // input
);
endgenerate
endmodule
module sens_hist_ram_snglclk_32(
input pclk,
input [9:0] addr_a_even,
input [9:0] addr_a_odd,
input [31:0] data_in_a,
output [31:0] data_out_a_even,
output [31:0] data_out_a_odd,
input en_a_even,
input en_a_odd,
input regen_a_even,
input regen_a_odd,
input we_a_even,
input we_a_odd,
input mclk,
input [9:0] addr_b,
output reg [31:0] data_out_b,
input re_b
);
reg [1:0] re_b_r;
wire [31:0] data_out_b_w_even;
wire [31:0] data_out_b_w_odd;
always @(posedge mclk) begin
re_b_r <= {re_b_r[0], re_b};
data_out_b <= re_b_r[1] ? data_out_b_w_even : data_out_b_w_odd;
end
ramt_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(5),
.LOG2WIDTH_B(5),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_even_i (
.clk_a (pclk), // input
.addr_a (addr_a_even), // input[10:0]
.en_a (en_a_even), // input
.regen_a (regen_a_even), // input
.we_a (we_a_even), // input
.data_out_a (data_out_a_even), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_b), // input FIXME: read (and write!) only when needed odd/even
.regen_b (re_b_r[0]), // input FIXME: read only when needed odd/even
.we_b (1'b1), // input
.data_out_b (data_out_b_w_even), // output[15:0]
.data_in_b (32'b0) // input[15:0]
);
ramt_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(5),
.LOG2WIDTH_B(5),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_odd_i (
.clk_a (pclk), // input
.addr_a (addr_a_odd), // input[10:0]
.en_a (en_a_odd), // input
.regen_a (regen_a_odd), // input
.we_a (we_a_odd), // input
.data_out_a (data_out_a_odd), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_b_r[0]), // input
.regen_b (re_b_r[1]), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_odd), // output[15:0]
.data_in_b (32'b0) // input[15:0]
);
endmodule
module sens_hist_ram_snglclk_18(
input pclk,
input [9:0] addr_a_even,
input [9:0] addr_a_odd,
input [17:0] data_in_a,
output [17:0] data_out_a_even,
output [17:0] data_out_a_odd,
input en_a_even,
input en_a_odd,
input regen_a_even,
input regen_a_odd,
input we_a_even,
input we_a_odd,
input mclk,
input [9:0] addr_b,
output reg [31:0] data_out_b,
input re_b
);
reg [1:0] re_b_r;
wire [17:0] data_out_b_w_even;
wire [17:0] data_out_b_w_odd;
always @(posedge mclk) begin
re_b_r <= {re_b_r[0], re_b};
data_out_b <= {14'b0,(re_b_r[1] ? data_out_b_w_even : data_out_b_w_odd)};
end
ram18tp_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(4),
.LOG2WIDTH_B(4),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_even_i (
.clk_a (pclk), // input
.addr_a (addr_a_even), // input[10:0]
.en_a (en_a_even), // input
.regen_a (regen_a_even), // input
.we_a (we_a_even), // input
.data_out_a (data_out_a_even), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_b), // input
.regen_b (re_b_r[0]), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_even), // output[15:0]
.data_in_b (18'b0) // input[15:0]
);
ram18tp_var_w_var_r #(
.REGISTERS_A(1),
.REGISTERS_B(1),
.LOG2WIDTH_A(4),
.LOG2WIDTH_B(4),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("READ_FIRST")
) ramt_var_w_var_r_odd_i (
.clk_a (pclk), // input
.addr_a (addr_a_odd), // input[10:0]
.en_a (en_a_odd), // input
.regen_a (regen_a_odd), // input
.we_a (we_a_odd), // input
.data_out_a (data_out_a_odd), // output[15:0]
.data_in_a (data_in_a), // input[15:0]
.clk_b (mclk), // input
.addr_b (addr_b), // input[10:0]
.en_b (re_b_r[0]), // input
.regen_b (re_b_r[1]), // input
.we_b (1'b1), // input
.data_out_b (data_out_b_w_odd), // output[15:0]
.data_in_b (18'b0) // input[15:0]
);
endmodule
module sens_histogram_snglclk_dummy(
output hist_rq,
output [31:0] hist_do,
output hist_dv
`ifdef DEBUG_RING
, output debug_do,
input debug_di
`endif
);
assign hist_rq = 0;
assign hist_do = 0;
assign hist_dv = 0;
`ifdef DEBUG_RING
assign debug_do = debug_di;
`endif
endmodule
\ No newline at end of file
sensor/sensor_channel.v
View file @ cfdcac60
......@@ -993,6 +993,40 @@ module sensor_channel#(
.bayer_out (gamma_bayer) // output [1:0]
);
// Debugging - adding a parallel to 0:0 module
wire hist_rq_debug;
wire [31:0] hist_do_debug;
wire hist_dv_debug;
sens_histogram_snglclk #(
.HISTOGRAM_RAM_MODE ("BUF32"),
// .HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.HISTOGRAM_ADDR (HISTOGRAM_ADDR0),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_snglclk_chn0_0_i (
.mrst (mrst), // input
.prst (prsts), // input
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.mclk (mclk), // input
.hist_en (hist_en[0]), // input
.hist_rst (!hist_nrst[0]), // input
.hist_rq (hist_rq_debug), // output
.hist_grant (hist_gr[0]), // input
.hist_do (hist_do_debug), // output[31:0]
.hist_dv (hist_dv_debug), // output reg
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
);
// TODO: Use generate to generate 1-4 histogram modules
generate
if (HISTOGRAM_ADDR0 >=0)
......
wrap/ram18t_var_w_var_r.v 0 → 100644
View file @ cfdcac60
/*******************************************************************************
* Module: ram18t_var_w_var_r
* Date:2015-05-29
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Does not use parity bits to increase total data width, width down to 1 are valid.
*
* Copyright (c) 2015 Elphel, Inc.
* ram18t_var_w_var_r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ram18t_var_w_var_r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ram18t_var_w_var_r
#(
parameter integer REGISTERS_A = 0, // 1 - registered output
parameter integer REGISTERS_B = 0, // 1 - registered output
parameter integer LOG2WIDTH_A = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_B = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram36_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [13-LOG2WIDTH_A:0] addr_a, // address port A
input en_a, // enable port A (read and write)
input regen_a, // output register enable port A
input we_a, // write port enable port A
output [(1 << LOG2WIDTH_A)-1:0] data_out_a,// data out port A
input [(1 << LOG2WIDTH_A)-1:0] data_in_a, // data in port A
input clk_b, // clock for port BA
input [13-LOG2WIDTH_B:0] addr_b, // address port B
input en_b, // read enable port B
input regen_b, // output register enable port B
input we_b, // write port enable port B
output [(1 << LOG2WIDTH_B)-1:0] data_out_b,// data out port B
input [(1 << LOG2WIDTH_B)-1:0] data_in_b // data in port B
);
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
localparam WIDTH_B = 1 << LOG2WIDTH_B;
wire [15:0] data_out16_a;
assign data_out_a=data_out16_a[WIDTH_A-1:0];
wire [15:0] data_out16_b;
assign data_out_b=data_out16_b[WIDTH_B-1:0];
wire [WIDTH_A+15:0] data_in_ext_a = {16'b0,data_in_a[WIDTH_A-1:0]};
wire [15:0] data_in16_a = data_in_ext_a[15:0];
wire [WIDTH_B+15:0] data_in_ext_b = {16'b0,data_in_b[WIDTH_B-1:0]};
wire [15:0] data_in16_b = data_in_ext_b[15:0];
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS_A), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS_B), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A (WRITE_MODE_A), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B (WRITE_MODE_B), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB18E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out16_a), // Port A data/LSB data[15:0], output
.DOPADOP (), // Port A parity/LSB parity[1:0], output
.DIADI (data_in16_a), // Port A data/LSB data[15:0], input
.DIPADIP (2'b0), // Port A parity/LSB parity[1:0], input
.ADDRARDADDR ({addr_a,{LOG2WIDTH_A{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (clk_a), // Port A (read port in SDP) clock, input
.ENARDEN (en_a), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen_a), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA ({2{we_a}}), // Port A (read port in SDP) Write Enable[1:0], input
// Port B
.DOBDO (data_out16_b), // Port B data/MSB data[31:0], output
.DOPBDOP (), // Port B parity/MSB parity[3:0], output
.DIBDI (data_in16_b), // Port B data/MSB data[31:0], input
.DIPBDIP (2'b0), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (read port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (clk_b), // Port B (write port in SDP) clock, input
.ENBWREN (en_b), // Port B (write port in SDP) Enable, input
.REGCEB (regen_b), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE ({4{we_b}}) // Port B (write port in SDP) Write Enable[3:0], input
);
endmodule
wrap/ram18tp_var_w_var_r.v 0 → 100644
View file @ cfdcac60
/*******************************************************************************
* Module: ram18tp_var_w_var_r
* Date:2015-10-21
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB18E1. Same R/W widths in each port.
* Uses parity bits to increase total data width. Widths down to 9 are valid.
*
* Copyright (c) 2015 Elphel, Inc.
* ram18tp_var_w_var_r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ram18tp_var_w_var_r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ram18tp_var_w_var_r
#(
parameter integer REGISTERS_A = 0, // 1 - registered output
parameter integer REGISTERS_B = 0, // 1 - registered output
parameter integer LOG2WIDTH_A = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_B = 4, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter WRITE_MODE_A = "NO_CHANGE", //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
parameter WRITE_MODE_B = "NO_CHANGE" //Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)(
input clk_a, // clock for port A
input [13-LOG2WIDTH_A:0] addr_a, // address port A
input en_a, // enable port A (read and write)
input regen_a, // output register enable port A
input we_a, // write port enable port A
output [(9 << (LOG2WIDTH_A-3))-1:0] data_out_a,// data out port A
input [(9 << (LOG2WIDTH_A-3))-1:0] data_in_a, // data in port A
input clk_b, // clock for port BA
input [13-LOG2WIDTH_B:0] addr_b, // address port B
input en_b, // read enable port B
input regen_b, // output register enable port B
input we_b, // write port enable port B
output [(9 << (LOG2WIDTH_B-3))-1:0] data_out_b,// data out port B
input [(9 << (LOG2WIDTH_B-3))-1:0] data_in_b // data in port B
);
localparam PWIDTH_A = (LOG2WIDTH_A > 2)? (9 << (LOG2WIDTH_A - 3)): (1 << LOG2WIDTH_A);
localparam PWIDTH_B = (LOG2WIDTH_B > 2)? (9 << (LOG2WIDTH_B - 3)): (1 << LOG2WIDTH_B);
localparam WIDTH_A = 1 << LOG2WIDTH_A;
localparam WIDTH_AP = 1 << (LOG2WIDTH_A-3);
localparam WIDTH_B = 1 << LOG2WIDTH_B;
localparam WIDTH_BP = 1 << (LOG2WIDTH_B-3);
wire [15:0] data_out16_a;
wire [ 1:0] datap_out2_a;
assign data_out_a={datap_out2_a[WIDTH_AP-1:0], data_out16_a[WIDTH_A-1:0]};
wire [15:0] data_out16_b;
wire [ 1:0] datap_out2_b;
assign data_out_b={datap_out2_b[WIDTH_BP-1:0], data_out16_b[WIDTH_B-1:0]};
wire [WIDTH_A+15:0] data_in_ext_a = {16'b0,data_in_a[WIDTH_A-1:0]};
wire [15:0] data_in16_a = data_in_ext_a[15:0];
wire [WIDTH_AP+1:0] datap_in_ext_a = {2'b0,data_in_a[WIDTH_A+:WIDTH_AP]};
wire [1:0] datap_in2_a= datap_in_ext_a[1:0];
wire [WIDTH_B+15:0] data_in_ext_b = {16'b0,data_in_b[WIDTH_B-1:0]};
wire [15:0] data_in16_b = data_in_ext_b[15:0];
wire [WIDTH_BP+1:0] datap_in_ext_b = {2'b0,data_in_b[WIDTH_B+:WIDTH_BP]};
wire [1:0] datap_in2_b= datap_in_ext_b[1:0];
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS_A), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS_B), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (PWIDTH_A), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_B), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A (WRITE_MODE_A), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B (WRITE_MODE_B), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB18E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out16_a), // Port A data/LSB data[15:0], output
.DOPADOP (datap_out2_a), // Port A parity/LSB parity[1:0], output
.DIADI (data_in16_a), // Port A data/LSB data[15:0], input
.DIPADIP (datap_in2_a), // Port A parity/LSB parity[1:0], input
.ADDRARDADDR ({addr_a,{LOG2WIDTH_A{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (clk_a), // Port A (read port in SDP) clock, input
.ENARDEN (en_a), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen_a), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA ({2{we_a}}), // Port A (read port in SDP) Write Enable[1:0], input
// Port B
.DOBDO (data_out16_b), // Port B data/MSB data[31:0], output
.DOPBDOP (datap_out2_b), // Port B parity/MSB parity[3:0], output
.DIBDI (data_in16_b), // Port B data/MSB data[31:0], input
.DIPBDIP (datap_in2_b), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({addr_b,{LOG2WIDTH_B{1'b1}}}), // Port B (read port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (clk_b), // Port B (write port in SDP) clock, input
.ENBWREN (en_b), // Port B (write port in SDP) Enable, input
.REGCEB (regen_b), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE ({4{we_b}}) // Port B (write port in SDP) Write Enable[3:0], input
);
endmodule
x393_testbench03.sav
View file @ cfdcac60
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Oct 21 03:45:23 2015
[*] Thu Oct 22 02:28:16 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151020195643294.fst"
[dumpfile_mtime] "Wed Oct 21 02:34:57 2015"
[dumpfile_size] 269754303
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151021192628858.fst"
[dumpfile_mtime] "Thu Oct 22 01:43:50 2015"
[dumpfile_size] 66340427
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 93798600
[timestart] 75068830
[size] 1823 1180
[pos] 1917 0
*-16.380077 94047388 178682388 184032388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-14.020046 75115830 178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -30,7 +30,6 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
......@@ -41,6 +40,7 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
......@@ -49,8 +49,8 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 280
[signals_width] 262
[sst_width] 437
[signals_width] 322
[sst_expanded] 1
[sst_vpaned_height] 670
@820
......@@ -883,9 +883,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-group_end
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.calc_valid
@29
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_run
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_delayed
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_mod
......@@ -1551,6 +1549,8 @@ x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.seq_wr
-mcntr_linear_rw_chn1
@28
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_start
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_done
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.frame_finished
@800022
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.page_cntr[2:0]
@28
......@@ -1565,16 +1565,259 @@ x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_grant
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_reject_r
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.skip_run
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.cmd_wrmem
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.next_page
@22
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.pending_xfers[1:0]
@28
x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_done
@800200
-membridge
@28
x393_testbench03.x393_i.membridge_i.start_mclk
@200
-
@1000200
-membridge
-mcntr_linear_rw_chn1
@200
-
@800200
-sens_hist_sngl0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.cmd_ad[7:0]
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.cmd_stb
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en_new
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en_rq_start
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_d3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_prev
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_prev_d2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.frame_active
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hact
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hact_d[1:0]
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hcntr[15:0]
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hcntr_zero_w
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.height_m1[15:0]
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_bank_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_bank_pclk
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_do[31:0]
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x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_done_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_en
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_en_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_grant
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_new_even[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_new_odd[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_out_d
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re_even_odd[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rst_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_busy
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_done_mclk
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.left[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.left_margin
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.line_start_w
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.lt_mclk[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.mclk
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
@1001200
-group_end
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.odd_pix
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pio_addr[1:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pio_data[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pio_stb
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pre_first_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.prst
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_di[7:0]
@23
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d0[7:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d2[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d4[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d5[7:0]
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_odd[8:0]
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r0[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r0_sel
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r1[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r1_sat
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r2[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r3[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r_load[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.regen_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.regen_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.rwen_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.rwen_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_left_top_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_left_top_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_ra_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_ra_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_wa_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_wa_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_width_height_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_width_height_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.sof
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.top[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.top_margin
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vcntr[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vcntr_zero_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vert_woi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.wait_readout
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.we_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.we_odd
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.wh_mclk[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.width_m1[15:0]
@1000200
-sens_hist_sngl0
@800200
-histogram_chn0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_di[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr_zero_w
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pulse_cross_clock_hlstart_start_i.in_pulse
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hlstart
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi_2x
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_2x[7:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.bayer_pclk[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
@1001200
-group_end
@1000200
-histogram_chn0
@200
-
[pattern_trace] 1
[pattern_trace] 0
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