Debugging hardware, added functionality to detect cache-related problems

.project

@@ -52,7 +52,7 @@
 		<link>
 			<name>ise_logs/ISExst.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/ise_logs/ISExst-20150228145735970.log</location>
+			<location>/home/andrey/git/x393/ise_logs/ISExst-20150505133407662.log</location>
 		</link>
 		<link>
 			<name>ise_state/x393-synth.tgz</name>
@@ -62,77 +62,77 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150505101739146.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150506104713443.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150505101739146.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150506104713443.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150505101930202.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150506105443622.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150505101739146.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150506104713443.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150505101930202.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150506105443622.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-place.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-place-20150505101930202.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-place-20150506105443622.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-route-20150505101930202.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-route-20150506105443622.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150505101739146.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150506104713443.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

axi/membridge.v

@@ -30,6 +30,7 @@ module  membridge#(
     parameter MEMBRIDGE_START64=                  'h4, // start address relative to lo_addr
     parameter MEMBRIDGE_LEN64=                    'h5, // full length of transfer in 64-bit words
     parameter MEMBRIDGE_WIDTH64=                  'h6, // frame width in 64-bit words (partial last page in each line)
+    parameter MEMBRIDGE_MODE=                     'h7, // frame width in 64-bit words (partial last page in each line)
     parameter MEMBRIDGE_STATUS_REG=               'h3b,
     parameter FRAME_HEIGHT_BITS=                   16,   // Maximal frame height bits
     parameter FRAME_WIDTH_BITS=                    13
@@ -118,10 +119,12 @@ module  membridge#(
     output         afi_rdissuecap1en
     
 );
+    localparam BUFWR_WE_WIDTH = 4; //2; // 4;
+    localparam SAFE_RD_BITS =   3; //2; // 3;
     // Some constant signals:
     
     assign afi_awlock =        2'h0;
-    assign afi_awcache =       4'h3;
+//    assign afi_awcache =       4'h3;
     assign afi_awprot =        3'h0;
     assign afi_awsize =        3'h3;
     assign afi_awburst =       2'h1;
@@ -130,7 +133,7 @@ module  membridge#(
     assign afi_wrissuecap1en = 1'b0;
 
     assign afi_arlock =        2'h0;
-    assign afi_arcache =       4'h3;
+//    assign afi_arcache =       4'h3;
     assign afi_arprot =        3'h0;
     assign afi_arsize =        3'h3;
     assign afi_arburst =       2'h1;
@@ -150,9 +153,14 @@ module  membridge#(
     wire set_size64_w;
     wire set_start64_w;
     wire set_len64_w;
+    wire set_mode_w;
     wire set_width64_w;
-    
-    
+    reg  [4:0] mode_reg_mclk;
+    reg  [4:0] mode_reg;
+    wire       cache_debug;
+    assign cache_debug=mode_reg[4];
+    assign afi_awcache =       mode_reg[3:0]; // 4'h3;
+    assign afi_arcache =       mode_reg[3:0]; // 4'h3;
     assign set_ctrl_w =         cmd_we && (cmd_a== MEMBRIDGE_CTRL);
     assign set_lo_addr64_w =    cmd_we && (cmd_a== MEMBRIDGE_LO_ADDR64);
     assign set_size64_w =       cmd_we && (cmd_a== MEMBRIDGE_SIZE64);
@@ -160,6 +168,7 @@ module  membridge#(
     assign set_len64_w =        cmd_we && (cmd_a== MEMBRIDGE_LEN64);
     assign set_width64_w =      cmd_we && (cmd_a== MEMBRIDGE_WIDTH64);
     assign set_status_w =       cmd_we && (cmd_a== MEMBRIDGE_STATUS_CNTRL);
+    assign set_mode_w =         cmd_we && (cmd_a== MEMBRIDGE_MODE);
     reg [28:0] lo_addr64_mclk;
     reg [28:0] size64_mclk;
     reg [28:0] start64_mclk;
@@ -205,6 +214,10 @@ module  membridge#(
         
         if   (rst) start_mclk <= 0;
         else       start_mclk <= set_ctrl_w & cmd_data[1];
+
+        if      (rst)        mode_reg_mclk <= 5'h03;
+        else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
+
 `ifdef MEMBRIDGE_DEBUG_READ
         if   (rst) debug_aw_mclk <= 0;
         else       debug_aw_mclk <= set_ctrl_w & cmd_data[2];
@@ -214,6 +227,8 @@ module  membridge#(
 
         if   (rst) debug_disable_set_mclk <= 0;
         else       debug_disable_set_mclk <= set_ctrl_w & cmd_data[4];
+        
+        
 `endif
 
     end
@@ -264,9 +279,8 @@ module  membridge#(
         size64          <= size64_mclk;
         start64         <= start64_mclk;
         len64           <= len64_mclk;
-//        width64         <= width64_mclk;
+        mode_reg        <= mode_reg_mclk;
         last_in_line64  <= width64_minus1_mclk;
-//        last_in_line64  <= width64_mclk[FRAME_WIDTH_BITS:0]-1;
         wr_mode         <= cmd_wrmem;
         rdwr_reset_addr <= rdwr_reset_addr_mclk;
         last_addr1k     <= size64[28:4] - 1;
@@ -294,6 +308,8 @@ module  membridge#(
         if      (rst)      wr_id <= 0;
         else if (wr_start) wr_id <= wr_id +1;
         
+        
+
     end
     // mclk -> hclk
     pulse_cross_clock start_i          (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(start_mclk), .out_pulse(start_hclk),.busy());
@@ -498,7 +514,7 @@ module  membridge#(
     wire                       bufwr_we_w; // TODO: assign
     
     reg                  [2:0] bufrd_rd;
-    reg                  [1:0] bufwr_we;
+    reg   [BUFWR_WE_WIDTH-1:0] bufwr_we;
     reg                        buf_rdwr; // equiv to  bufrd_rd[0] || bufwr_we)
     wire                       is_last_in_line;
     wire                       is_last_in_page;
@@ -545,7 +561,7 @@ module  membridge#(
         debug_bufrd_rd<= {debug_bufrd_rd[3:0], bufrd_rd_w };
 `endif        
         buf_rdwr <= bufrd_rd_w || bufwr_we_w;
-        bufwr_we <= {bufwr_we[0],bufwr_we_w};
+        bufwr_we <= {bufwr_we[BUFWR_WE_WIDTH-2:0],bufwr_we_w};
         
     end
     assign afi_wvalid=bufrd_rd[2];
@@ -592,7 +608,7 @@ module  membridge#(
         if (rst) afi_rd_safe_not_empty <= 0;
          // allow 1 cycle latency, no continuous reads when FIFO is low (like in the very end of the transfer)
          // Adjust '2' in afi_rcount[6:2] ? 
-        else     afi_rd_safe_not_empty <= rdwr_en && ( afi_rcount[7] || (|afi_rcount[6:2]) || (!(|bufwr_we) && afi_rvalid));
+        else     afi_rd_safe_not_empty <= rdwr_en && ( afi_rcount[7] || (|afi_rcount[6:SAFE_RD_BITS]) || (!(|bufwr_we) && !bufwr_we_w && afi_rvalid));
 
         if (rst) afi_ra_safe_not_full <= 0;
         else     afi_ra_safe_not_full <= rdwr_en && ( !afi_racount[2] && !(&afi_racount[1:0]));
@@ -616,7 +632,8 @@ module  membridge#(
     always @ (posedge hclk) begin
         write_page_r    <= write_page;
         buf_in_line64_r <= buf_in_line64[6:0];
-        rdata_r <= afi_rdata;
+//        rdata_r <= afi_rdata;
+        rdata_r <= cache_debug?{wr_id[3:0],2'b0,write_page_r[1:0],afi_rcount[7:0],afi_rdata[47:0]}:afi_rdata[63:0]; // debugging
     end    
         
     cmd_deser #(

includes/x393_parameters.vh

@@ -32,7 +32,10 @@
     parameter MCONTR_BUF4_RD_ADDR =     'h1400, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
     parameter MCONTR_BUF4_WR_ADDR =     'h1400, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
     parameter CONTROL_ADDR =            'h2000, // AXI write address of control write registers
-    parameter CONTROL_ADDR_MASK =    'h3c00, // AXI write address of control registers
+    parameter CONTROL_ADDR_MASK =       'h3c00, // AXI write mask of control registers
+    parameter CONTROL_RBACK_ADDR =      'h2000, // AXI read address of control registers readback
+    parameter CONTROL_RBACK_ADDR_MASK = 'h3c00, // AXI mask of control registers readback addresses
+    parameter CONTROL_RBACK_DEPTH=          10, // 
     parameter STATUS_ADDR =             'h2400, // AXI write address of status read registers
     parameter STATUS_ADDR_MASK =        'h3c00, // AXI write address of status registers
     parameter AXI_WR_ADDR_BITS =            14,
@@ -260,6 +263,7 @@
     parameter MEMBRIDGE_START64=                  'h4, // start address relative to lo_addr
     parameter MEMBRIDGE_LEN64=                    'h5, // full length of transfer in 64-bit words
     parameter MEMBRIDGE_WIDTH64=                  'h6, // frame width in 64-bit words (partial last page in each line)
+    parameter MEMBRIDGE_MODE=                     'h7, // frame width in 64-bit words (partial last page in each line)
     parameter MEMBRIDGE_STATUS_REG=               'h3b,
     
     parameter RSEL=                               1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)

includes/x393_tasks01.vh

@@ -30,6 +30,13 @@
         end
     endtask   
 
+    task   read_contol_register;
+        input [29:0] reg_addr;
+        begin
+            read_and_wait_w(CONTROL_RBACK_ADDR+reg_addr);
+        end
+    endtask   
+
     task wait_read_queue_empty;
         begin
         wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?   

includes/x393_tasks_mcntrl_timing.vh

@@ -94,6 +94,30 @@
      end
     endtask
 
+    task axi_get_delays; // set all individual delays
+     integer i;
+     begin
+         $display("axi_get_delays @ %t",$time);
+     
+        for (i=0;i<10;i=i+1) begin
+            read_contol_register(LD_DLY_LANE0_ODELAY + i);
+        end
+        for (i=0;i<9;i=i+1) begin
+            read_contol_register(LD_DLY_LANE0_IDELAY + i);
+        end
+        for (i=0;i<10;i=i+1) begin
+            read_contol_register(LD_DLY_LANE1_ODELAY + i);
+        end
+        for (i=0;i<9;i=i+1) begin
+            read_contol_register(LD_DLY_LANE1_IDELAY + i);
+        end
+        for (i=0;i<32;i=i+1) begin
+            read_contol_register(LD_DLY_CMDA + i);
+        end
+        read_contol_register(LD_DLY_PHASE);
+     end
+    endtask
+
 
     task axi_set_dq_idelay; // sets same delay to all dq idelay
         input [7:0] delay;

memctrl/mcntrl393.v

@@ -258,7 +258,7 @@ module  mcntrl393 #(
     input                        axird_regen, //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
 //   wire  [31:0]   axird_bram_rdata;  //      .data_out(rdata[31:0]),       // data out
     output              [31:0]   axird_rdata,  // combinatorial multiplexed (add external register layer, modify axibram_read?)     .data_out(rdata[31:0]),       // data out
-    output                       axird_selected, // axird_rdata contains cvalid data from this module 
+    output                       axird_selected, // axird_rdata contains valid data from this module 
 //   wire  [31:0]   port0_rdata;  //
 //   wire  [31:0]   status_rdata;  //
 

py393/vrlg.py

@@ -132,12 +132,14 @@ WSEL = int
 MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
 LD_DLY_LANE1_IDELAY = int
 MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
+CONTROL_RBACK_ADDR_MASK = int
 MCNTRL_TILED_CHN4_ADDR = int
 WINDOW_Y0__RAW = str
 DLY_LD__RAW = str
 MCNTRL_TEST01_CHN3_MODE__RAW = str
 DFLT_INV_CLK_DIV__RAW = str
 NUM_CYCLES_12__TYPE = str
+DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
 IBUF_LOW_PWR__RAW = str
 DLY_LANE1_ODELAY__RAW = str
 DLY_DQ_IDELAY__TYPE = str
@@ -223,6 +225,7 @@ CLKFBOUT_DIV_AXIHP = int
 NUM_CYCLES_13__TYPE = str
 AXI_RD_ADDR_BITS__RAW = str
 MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
+CONTROL_RBACK_ADDR__RAW = str
 MCONTR_WR_MASK__RAW = str
 MCNTRL_TILED_WINDOW_STARTXY = int
 MCONTR_TOP_0BIT_MCONTR_EN = int
@@ -264,7 +267,7 @@ NUM_CYCLES_11__TYPE = str
 MCNTRL_SCANLINE_STARTADDR__TYPE = str
 WBUF_DLY_DFLT__RAW = str
 DQSTRI_FIRST = int
-LD_DLY_CMDA__TYPE = str
+CONTROL_RBACK_DEPTH__RAW = str
 DLY_CMDA_ODELAY__TYPE = str
 LD_DLY_CMDA = int
 DLY_SET__RAW = str
@@ -287,10 +290,10 @@ TILED_STARTX__RAW = str
 WRITE_BLOCK_OFFSET__TYPE = str
 STATUS_ADDR_MASK = int
 MCNTRL_TEST01_ADDR__TYPE = str
-AXI_WR_ADDR_BITS = int
+LD_DLY_CMDA__TYPE = str
 TEST01_NEXT_PAGE = int
 CLKFBOUT_MULT__RAW = str
-MAX_TILE_HEIGHT__RAW = str
+CONTROL_RBACK_ADDR__TYPE = str
 MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
 IBUF_LOW_PWR = str
 CONTROL_ADDR = int
@@ -346,6 +349,7 @@ DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
 TILE_HEIGHT__RAW = str
 FRAME_WIDTH_BITS = int
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
+MEMBRIDGE_MODE__RAW = str
 MEMBRIDGE_STATUS_CNTRL = int
 SLEW_CMDA__TYPE = str
 MCONTR_RD_MASK__TYPE = str
@@ -365,12 +369,14 @@ WBUF_DLY_DFLT = int
 MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
 DQTRI_FIRST = int
 MCONTR_BUF2_WR_ADDR = int
-DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
+AXI_WR_ADDR_BITS = int
+CONTROL_RBACK_DEPTH = int
 MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
 SCANLINE_EXTRA_PAGES__TYPE = str
 PHASE_WIDTH__RAW = str
 MEMBRIDGE_START64 = int
 MEMBRIDGE_SIZE64__RAW = str
+MAX_TILE_HEIGHT__RAW = str
 DFLT_DQS_PATTERN = int
 DLY_LANE0_DQS_WLV_IDELAY__RAW = str
 MCNTRL_TEST01_CHN2_MODE__TYPE = str
@@ -477,13 +483,14 @@ MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
 TEST01_START_FRAME = int
 DQTRI_FIRST__TYPE = str
 MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
-T_RFC__RAW = str
+CONTROL_RBACK_DEPTH__TYPE = str
 DLY_CMDA__TYPE = str
 CLKFBOUT_MULT__TYPE = str
 WBUF_DLY_DFLT__TYPE = str
 MCONTR_PHY_0BIT_CMDA_EN__RAW = str
 STATUS_SEQ_SHFT__RAW = str
 DLY_DM_ODELAY__TYPE = str
+MCNTRL_TEST01_CHN4_MODE__RAW = str
 MCONTR_PHY_0BIT_DCI_RST__RAW = str
 REFCLK_FREQUENCY__RAW = str
 MCONTR_RD_MASK__RAW = str
@@ -495,6 +502,7 @@ MCONTR_PHY_0BIT_DLY_RST__RAW = str
 SCANLINE_STARTY__RAW = str
 FRAME_FULL_WIDTH__TYPE = str
 WRITE_BLOCK_OFFSET = int
+MEMBRIDGE_MODE__TYPE = str
 COLADDR_NUMBER__TYPE = str
 MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
 TEST01_SUSPEND__TYPE = str
@@ -553,7 +561,7 @@ NUM_CYCLES_06__RAW = str
 MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
 NUM_XFER_BITS__RAW = str
 MCNTRL_TILED_WINDOW_STARTXY__RAW = str
-CLKFBOUT_MULT_AXIHP = int
+CONTROL_RBACK_ADDR = int
 DLY_CMDA_ODELAY = long
 MCONTR_TOP_0BIT_ADDR = int
 MEMBRIDGE_LO_ADDR64__TYPE = str
@@ -562,7 +570,7 @@ MCONTR_ARBIT_ADDR_MASK = int
 NUM_CYCLES_05__RAW = str
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
 MCNTRL_PS_CMD = int
-MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
+MEMBRIDGE_MODE = int
 STATUS_2LSB_SHFT__RAW = str
 WBUF_DLY_WLV__RAW = str
 MCONTR_TOP_0BIT_REFRESH_EN = int
@@ -618,6 +626,7 @@ MCNTRL_PS_STATUS_CNTRL__TYPE = str
 MCONTR_PHY_16BIT_ADDR = int
 REF_JITTER1__TYPE = str
 MCNTRL_SCANLINE_MODE__TYPE = str
+STATUS_ADDR_MASK__RAW = str
 MCONTR_PHY_16BIT_PATTERNS_TRI = int
 DLY_CMDA__RAW = str
 MEMBRIDGE_MASK = int
@@ -634,6 +643,7 @@ SDCLK_PHASE__TYPE = str
 SCANLINE_STARTY__TYPE = str
 REFRESH_OFFSET__RAW = str
 MCNTRL_TEST01_CHN2_MODE = int
+MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
 MCNTRL_TEST01_CHN1_MODE__RAW = str
 MCONTR_BUF4_RD_ADDR__TYPE = str
 LD_DLY_LANE0_ODELAY__TYPE = str
@@ -676,7 +686,7 @@ MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
 MCONTR_ARBIT_ADDR_MASK__RAW = str
 DFLT_WBUF_DELAY = int
 DLY_DQ_ODELAY = long
-STATUS_ADDR_MASK__RAW = str
+CONTROL_RBACK_ADDR_MASK__RAW = str
 MCNTRL_SCANLINE_CHN3_ADDR = int
 DLY_SET__TYPE = str
 MCONTR_TOP_16BIT_ADDR = int
@@ -763,6 +773,7 @@ NEWPAR__RAW = str
 MCLK_PHASE__RAW = str
 MCONTR_TOP_16BIT_REFRESH_PERIOD = int
 T_REFI = int
+CONTROL_RBACK_ADDR_MASK__TYPE = str
 MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
 WSEL__TYPE = str
 STATUS_SEQ_SHFT__TYPE = str
@@ -801,9 +812,10 @@ TILED_KEEP_OPEN__TYPE = str
 CONTROL_ADDR_MASK__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR__RAW = str
 HIGH_PERFORMANCE_MODE__RAW = str
-MCNTRL_TEST01_CHN4_MODE__RAW = str
+T_RFC__RAW = str
 DFLT_DQM_PATTERN__TYPE = str
 STATUS_ADDR__TYPE = str
+CLKFBOUT_MULT_AXIHP = int
 CLK_DIV_PHASE__TYPE = str
 MCONTR_PHY_0BIT_CMDA_EN = int
 MCNTRL_SCANLINE_CHN3_ADDR__RAW = str

py393/x393_axi_control_status.py

@@ -154,10 +154,33 @@ class X393AxiControlStatus(object):
     def write_contol_register(self, reg_addr, data):
         """
         Write 32-bit word to the control register
-        <addr> - register address relative to the control register address space
-        <data> - 32-bit data to write
+        @param addr - register address relative to the control register address space
+        @param data - 32-bit data to write
         """
         self.x393_mem.axi_write_single_w(vrlg.CONTROL_ADDR+reg_addr, data)
+
+    def read_contol_register(self, reg_addr=None, quiet=1):
+        """
+        Read 32-bit word from the control register (written by the software or the command sequencer)
+        @param  addr - register address relative to the control register address space
+        @param quiet - reduce output
+        @return control register value
+        """
+        if reg_addr is None:
+            rslt=[self.x393_mem.axi_read_addr_w(vrlg.CONTROL_RBACK_ADDR+reg_addr) for reg_addr in range(1024)]
+            if quiet < 2:
+                for reg_addr in range(1024):
+                    if (reg_addr & 0x0f) == 0:
+                        print("\n0x%03x:"%(reg_addr),end=" ")
+                    print("%08x"%(rslt[reg_addr]),end=" ")
+                print()    
+            return rslt
+        rslt=self.x393_mem.axi_read_addr_w(vrlg.CONTROL_RBACK_ADDR+reg_addr)
+        if quiet < 1:
+            print("control register 0x%x(0x%x) --> 0x%x"%(reg_addr,vrlg.CONTROL_RBACK_ADDR+reg_addr,rslt))
+        return rslt
+
+    
     def test_read_status(self, rpt): # was read_and_wait_status
         """
         Read word from the status register 0 and calculate part of the run busy

py393/x393_mcntrl_membridge.py

@@ -185,6 +185,7 @@ class X393McntrlMembridge(object):
                          start64,                       # input [28:0] start64;  # relative start adderss of the transfer (set to 0 when writing lo_addr64)
                          lo_addr64 =       None,        # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words 
                          size64 =          None,        # input [28:0] size64;    # size of the system memory range in 64-bit words
+                         cache = 0x3,
                          quiet=1):
         '''
         Set up membridge parameters for data transfer
@@ -193,6 +194,8 @@ class X393McntrlMembridge(object):
         @param start64 relative start address of the transfer (normally 0)
         @param lo_addr64 low address of the system memory range, in 64-bit words 
         @param size64  size of the system memory range in 64-bit words
+        @param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
+               bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
         @quiet - reduce output (>=1 - silent)
         '''
         if lo_addr64 is None:
@@ -207,6 +210,7 @@ class X393McntrlMembridge(object):
         self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64,    start64);    
         self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64,      len64);    
         self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64,    width64);    
+        self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE,       cache);    
 
     def membridge_start(self,
                         cont=False,
@@ -243,6 +247,7 @@ class X393McntrlMembridge(object):
                       lo_addr64 =         None,                     # input [28:0] lo_addr64;        # low address of the system memory range, in 64-bit words 
                       size64 =            None,                     # input [28:0] size64;           # size of the system memory range in 64-bit words
                       cont =              False,                    # input        continue;         # 0 start from start64, 1 - continue from where it was
+                      cache =             0x3,
                       wait_ready =        False,
                       quiet=1):
         '''
@@ -258,6 +263,8 @@ class X393McntrlMembridge(object):
         @param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits 
         @param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
         @param cont True: continue from  the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
+        @param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
+               bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
         @param wait_ready poll status to see if the command finished
         @param quiet Reduce output
         '''
@@ -288,10 +295,10 @@ class X393McntrlMembridge(object):
         if quiet <2:
             print("====== test_afi_rw: write=%s, frame_start=0x%x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d"%(
                                       str(write_ddr3),  frame_start_addr, window_full_width,   window_width, window_height, window_left, window_top));
-            print("len64=0x%x,  width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x"%(
+            print("len64=0x%x,  width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x, cache=0x%x"%(
                   (window_width << 1)*window_height,
                   (window_width << 1),
-                  start64, lo_addr64, size64))
+                  start64, lo_addr64, size64,cache))
         mode=   func_encode_mode_scanline(
                     0, # extra_pages,
                     write_ddr3, # write_mem,
@@ -314,7 +321,9 @@ class X393McntrlMembridge(object):
             (window_width << 1),               # (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, # width64,
             start64,
             lo_addr64,
-            size64)
+            size64,
+            cache,
+            quiet)
         self.membridge_start (cont)         
 # just wait done (default timeout = 10 sec)
         if wait_ready:

py393/x393_mcntrl_tests.py

@@ -366,15 +366,30 @@ class X393McntrlTests(object):
                             window_top):   # input [15:0]           window_top;
         """
         Test scanline read (frame size/row increment is set in parameters) 
-        <channel> channel number to use. Valid values: 1, 3
-        <extra_pages>    2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
-        <show_data>      print read data
-        <window_width>   13-bit window width in 8-bursts (16 bytes)
-        <window_height>  16 bit window height
-        <window_left>,   13-bit window left margin in 8-bursts (16 bytes)
-        <window_top>     16-bit window top margin
-        Returns read data as list
+        @param channel channel number to use. Valid values: 1, 3
+        @param extra_pages    2-bit number of extra pages that need to stay (not to be overwritten) in the buffer
+        @param show_data      print read data
+        @param window_width   13-bit window width in 8-bursts (16 bytes)
+        @param window_height  16 bit window height
+        @param window_left,   13-bit window left margin in 8-bursts (16 bytes)
+        @param window_top     16-bit window top margin
+        @return read data as list
         """
+        if show_data==2:
+            result=self.test_scanline_read (channel = channel,       # input            [3:0] channel;
+                                            extra_pages = extra_pages,   # input            [1:0] extra_pages;
+                                            show_data = 0,     # input                  extra_pages;
+                                            window_width = window_width,  # input [15:0]           window_width;
+                                            window_height = window_height, # input [15:0]           window_height;
+                                            window_left = window_left,   # input [15:0]           window_left;
+                                            window_top = window_top)
+            for line_no,line in enumerate(result):
+                print("%03x:"%(line_no),end=" ")
+                for i in range(len(line)//2):
+                    d = line[2*i] + (line[2*i+1] << 32)
+                    print("%16x"%(d),end=" ")
+                print()    
+            return result
         
         result=[] # will be a 2-d array
     
@@ -445,6 +460,7 @@ class X393McntrlTests(object):
             self.x393_axi_tasks.write_contol_register(test_mode_address,            vrlg.TEST01_NEXT_PAGE)
         return result    
 
+  
     def test_tiled_write(self,          #
                          channel,       # input            [3:0] channel;
                          byte32,        # input                  byte32;

x393.v

@@ -134,12 +134,18 @@ module  x393 #(
 //   wire  [31:0]   port0_rdata;  //
    wire  [31:0]   status_rdata;  //
    wire           status_selected;
+   wire  [31:0]   readback_rdata;  //
+   wire           readback_selected;
    wire  [31:0]   mcntrl_axird_rdata; // read data from the memory controller 
 
-   wire           mcntrl_axird_selected; // memory controoler has valid data output on mcntrl_axird_rdata 
+
+   
+   wire           mcntrl_axird_selected; // memory controller has valid data output on mcntrl_axird_rdata 
    reg            status_selected_ren;         // status_selected (set at axird_start_burst) delayed when ren is active
+   reg            readback_selected_ren;
    reg            mcntrl_axird_selected_ren;   // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active
    reg            status_selected_regen;       // status_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
+   reg            readback_selected_regen;
    reg            mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
 
    wire           mclk; // global clock, memory controller, command/status network (currently 200MHz)
@@ -251,7 +257,9 @@ module  x393 #(
    assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
    assign axird_dev_busy = 1'b0; // always for now
 // Use this later    
-   assign axird_rdata= ({32{status_selected_regen}} & status_rdata[31:0]) | ({32{mcntrl_axird_selected_regen}} & mcntrl_axird_rdata[31:0]);
+   assign axird_rdata= ({32{status_selected_regen}} & status_rdata[31:0]) |
+                       ({32{readback_selected_regen}} & readback_rdata[31:0]) |
+                       ({32{mcntrl_axird_selected_regen}} & mcntrl_axird_rdata[31:0]);
    
 //Debug with this (to show 'x)   
 //   assign axird_rdata= status_selected_regen?status_rdata[31:0] : (mcntrl_axird_selected_regen? mcntrl_axird_rdata[31:0]:'bx);
@@ -296,6 +304,12 @@ module  x393 #(
         if      (axi_rst)     status_selected_regen <= 1'b0;
         else if (axird_regen) status_selected_regen <= status_selected_ren;
 
+        if      (axi_rst)     readback_selected_ren <= 1'b0;
+        else if (axird_ren)   readback_selected_ren <= readback_selected;
+        
+        if      (axi_rst)     readback_selected_regen <= 1'b0;
+        else if (axird_regen) readback_selected_regen <= readback_selected_ren;
+
         if      (axi_rst)     mcntrl_axird_selected_ren <= 1'b0;
         else if (axird_ren)   mcntrl_axird_selected_ren <=  mcntrl_axird_selected;
         
@@ -456,6 +470,30 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .ad_stb       (cmd_root_stb) // output
     );
     
+    // Mirror control register data for readback (registers can be written both from the PS and from the command sequencer)
+    cmd_readback #(
+        .AXI_WR_ADDR_BITS        (AXI_WR_ADDR_BITS),
+        .AXI_RD_ADDR_BITS        (AXI_RD_ADDR_BITS),
+        .CONTROL_RBACK_DEPTH     (CONTROL_RBACK_DEPTH),
+        .CONTROL_ADDR            (CONTROL_ADDR),
+        .CONTROL_ADDR_MASK       (CONTROL_ADDR_MASK),
+        .CONTROL_RBACK_ADDR      (CONTROL_RBACK_ADDR),
+        .CONTROL_RBACK_ADDR_MASK (CONTROL_RBACK_ADDR_MASK)
+    ) cmd_readback_i (
+        .rst                     (axi_rst), // input
+        .mclk                    (mclk), // input
+        .axi_clk                 (axird_bram_rclk), // input
+        .par_waddr               (par_waddr), // input[13:0] 
+        .par_data                (par_data), // input[31:0] 
+        .ad_stb                  (cmd_root_stb), // input
+        .axird_pre_araddr        (axird_pre_araddr), // input[13:0] 
+        .axird_start_burst       (axird_start_burst), // input
+        .axird_raddr             (axird_raddr[CONTROL_RBACK_DEPTH-1:0]), // input[9:0] 
+        .axird_ren               (axird_ren), // input
+        .axird_rdata             (readback_rdata), // output[31:0] 
+        .axird_selected          (readback_selected) // output
+    );
+
     status_read #(
         .STATUS_ADDR      (STATUS_ADDR),
         .STATUS_ADDR_MASK (STATUS_ADDR_MASK),
@@ -772,6 +810,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .MEMBRIDGE_START64      (MEMBRIDGE_START64),
         .MEMBRIDGE_LEN64        (MEMBRIDGE_LEN64),
         .MEMBRIDGE_WIDTH64      (MEMBRIDGE_WIDTH64),
+        .MEMBRIDGE_MODE         (MEMBRIDGE_MODE),
         .MEMBRIDGE_STATUS_REG   (MEMBRIDGE_STATUS_REG),
         .FRAME_HEIGHT_BITS      (FRAME_HEIGHT_BITS),
         .FRAME_WIDTH_BITS       (FRAME_WIDTH_BITS)

x393_testbench01.sav

 [*]
 [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
-[*] Tue May  5 16:05:00 2015
+[*] Wed May  6 00:35:07 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150505094007974.lxt"
-[dumpfile_mtime] "Tue May  5 15:45:33 2015"
-[dumpfile_size] 282012275
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150505182137719.lxt"
+[dumpfile_mtime] "Wed May  6 00:29:43 2015"
+[dumpfile_size] 496570537
 [savefile] "/home/andrey/git/x393/x393_testbench01.sav"
-[timestart] 18656300
+[timestart] 38860800
 [size] 1823 1180
 [pos] 1919 0
-*-16.063198 18590000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-16.063198 39110000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench01.
 [treeopen] x393_testbench01.ddr3_i.
 [treeopen] x393_testbench01.simul_axi_hp_wr_i.
 [treeopen] x393_testbench01.x393_i.
 [treeopen] x393_testbench01.x393_i.axibram_write_i.
+[treeopen] x393_testbench01.x393_i.cmd_mux_i.
 [treeopen] x393_testbench01.x393_i.membridge_i.
 [sst_width] 363
 [signals_width] 446
 [sst_expanded] 1
 [sst_vpaned_height] 550
-@800200
+@820
+x393_testbench01.TEST_TITLE[639:0]
+@c00200
 -DDR3
 @28
 x393_testbench01.SDRST[0]
@@ -37,7 +40,7 @@ x393_testbench01.DQSL[0]
 x393_testbench01.DQSU[0]
 @22
 x393_testbench01.SDD[15:0]
-@1000200
+@1401200
 -DDR3
 @800200
 -top
@@ -60,7 +63,7 @@ x393_testbench01.PS_REG_DOUT[31:0]
 x393_testbench01.PS_RDATA[31:0]
 @1000200
 -PS
-@800200
+@c00200
 -simul_afi_wr
 @22
 x393_testbench01.simul_axi_hp_wr_i.write_left[3:0]
@@ -190,7 +193,7 @@ x393_testbench01.simul_axi_hp_wr_i.wstrb[7:0]
 x393_testbench01.simul_axi_hp_wr_i.wstrb_out[7:0]
 @28
 x393_testbench01.simul_axi_hp_wr_i.wvalid[0]
-@1000200
+@1401200
 -simul_afi_wr
 @c00200
 -simul_afi_rd
@@ -299,9 +302,25 @@ x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_read[0]
 x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_write[0]
 @1401200
 -simul_afi_rd
-@c00200
+@800200
 -membridge
 @28
+x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
+x393_testbench01.x393_i.membridge_i.afi_rready[0]
+x393_testbench01.x393_i.membridge_i.afi_rd_safe_not_empty[0]
+@22
+x393_testbench01.x393_i.membridge_i.afi_rcount[7:0]
+@28
+x393_testbench01.x393_i.membridge_i.bufwr_we_w[0]
+@23
+x393_testbench01.x393_i.membridge_i.bufwr_we[3:0]
+@800200
+-x393_testbench01.x393_i.membridge_i.bufwr_we
+@1001200
+-group_end
+@200
+-
+@28
 x393_testbench01.x393_i.membridge_i.rdwr_en[0]
 x393_testbench01.x393_i.membridge_i.read_busy[0]
 x393_testbench01.x393_i.membridge_i.write_busy[0]
@@ -337,11 +356,8 @@ x393_testbench01.x393_i.membridge_i.afi_arlen[3:0]
 x393_testbench01.x393_i.membridge_i.afi_arvalid[0]
 x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
 x393_testbench01.x393_i.membridge_i.afi_rready[0]
-@800028
-x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]
-@28
-(0)x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]
-(1)x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]
+@800200
+-x393_testbench01.x393_i.membridge_i.bufwr_we
 @1001200
 -group_end
 @28
@@ -541,11 +557,8 @@ x393_testbench01.x393_i.membridge_i.buf_wpage_nxt[0]
 x393_testbench01.x393_i.membridge_i.buf_wr[0]
 x393_testbench01.x393_i.membridge_i.bufrd_rd[2:0]
 x393_testbench01.x393_i.membridge_i.bufrd_rd_w[0]
-@800028
-x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]
-@28
-(0)x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]
-(1)x393_testbench01.x393_i.membridge_i.bufwr_we[1:0]
+@800200
+-x393_testbench01.x393_i.membridge_i.bufwr_we
 @1001200
 -group_end
 @28
@@ -689,6 +702,7 @@ x393_testbench01.x393_i.membridge_i.status_generate_i.wd[7:0]
 x393_testbench01.x393_i.membridge_i.status_generate_i.we[0]
 @1401200
 -membridge_status
+@1000200
 -membridge
 @200
 -
@@ -735,8 +749,6 @@ x393_testbench01.GLOBAL_WRITE_ID[11:0]
 -
 @1401200
 -wait_stat_cond
-@200
--
 @c00200
 -SAXIHP0
 @28
@@ -951,11 +963,14 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_start_wr_r[0]
 x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.xfer_want[0]
 @1401200
 -linear_rw_chn1
-@200
--
-@800200
+@c00200
 -axibram_write
 @28
+x393_testbench01.x393_i.axibram_write_i.bvalid[0]
+x393_testbench01.x393_i.axibram_write_i.bready[0]
+x393_testbench01.x393_i.axibram_write_i.bresp_re[0]
+x393_testbench01.x393_i.axibram_write_i.wresp_i.we[0]
+x393_testbench01.x393_i.axibram_write_i.wresp_i.re[0]
 x393_testbench01.x393_i.axibram_write_i.bram_wclk[0]
 x393_testbench01.x393_i.axibram_write_i.bram_wen[0]
 @22
@@ -965,7 +980,6 @@ x393_testbench01.x393_i.axibram_write_i.bvalid[0]
 x393_testbench01.x393_i.axibram_write_i.bram_we_w[0]
 x393_testbench01.x393_i.axibram_write_i.bresp_re[0]
 x393_testbench01.x393_i.axibram_write_i.wlast[0]
-@29
 x393_testbench01.x393_i.axibram_write_i.wlast_out[0]
 @22
 x393_testbench01.x393_i.axibram_write_i.awlen_out[3:0]
@@ -1062,7 +1076,140 @@ x393_testbench01.x393_i.axibram_write_i.wstb[3:0]
 x393_testbench01.x393_i.axibram_write_i.wstb_out[3:0]
 @28
 x393_testbench01.x393_i.axibram_write_i.wvalid[0]
-@1000200
+@1401200
 -axibram_write
+@c00200
+-amd_mux
+@22
+x393_testbench01.x393_i.cmd_mux_i.par_waddr[13:0]
+x393_testbench01.x393_i.cmd_mux_i.par_data[31:0]
+x393_testbench01.x393_i.cmd_mux_i.byte_ad[7:0]
+@28
+x393_testbench01.x393_i.cmd_mux_i.ad_stb[0]
+@200
+-
+@28
+x393_testbench01.x393_i.cmd_mux_i.ad_stb[0]
+x393_testbench01.x393_i.cmd_mux_i.ad_stb_r[0]
+x393_testbench01.x393_i.cmd_mux_i.axi_clk[0]
+x393_testbench01.x393_i.cmd_mux_i.busy[0]
+x393_testbench01.x393_i.cmd_mux_i.busy_r[0]
+@22
+x393_testbench01.x393_i.cmd_mux_i.byte_ad[7:0]
+@28
+x393_testbench01.x393_i.cmd_mux_i.can_start_w[0]
+x393_testbench01.x393_i.cmd_mux_i.cmdseq_full_r[0]
+x393_testbench01.x393_i.cmd_mux_i.cseq_ackn[0]
+@22
+x393_testbench01.x393_i.cmd_mux_i.cseq_waddr[13:0]
+x393_testbench01.x393_i.cmd_mux_i.cseq_waddr_r[13:0]
+x393_testbench01.x393_i.cmd_mux_i.cseq_wdata[31:0]
+x393_testbench01.x393_i.cmd_mux_i.cseq_wdata_r[31:0]
+@28
+x393_testbench01.x393_i.cmd_mux_i.cseq_wr_en[0]
+x393_testbench01.x393_i.cmd_mux_i.fifo_half_empty[0]
+x393_testbench01.x393_i.cmd_mux_i.fifo_nempty[0]
+x393_testbench01.x393_i.cmd_mux_i.mclk[0]
+@22
+x393_testbench01.x393_i.cmd_mux_i.par_ad[47:0]
+x393_testbench01.x393_i.cmd_mux_i.par_data[31:0]
+x393_testbench01.x393_i.cmd_mux_i.par_waddr[13:0]
+x393_testbench01.x393_i.cmd_mux_i.pre_waddr[13:0]
+@28
+x393_testbench01.x393_i.cmd_mux_i.rst[0]
+x393_testbench01.x393_i.cmd_mux_i.selected[0]
+x393_testbench01.x393_i.cmd_mux_i.selected_w[0]
+@22
+x393_testbench01.x393_i.cmd_mux_i.seq_busy_r[4:0]
+x393_testbench01.x393_i.cmd_mux_i.seq_length[3:0]
+x393_testbench01.x393_i.cmd_mux_i.seq_length_rom_a[3:0]
+@28
+x393_testbench01.x393_i.cmd_mux_i.ss[0]
+x393_testbench01.x393_i.cmd_mux_i.start_axi_w[0]
+x393_testbench01.x393_i.cmd_mux_i.start_w[0]
+x393_testbench01.x393_i.cmd_mux_i.start_wburst[0]
+@22
+x393_testbench01.x393_i.cmd_mux_i.waddr[13:0]
+x393_testbench01.x393_i.cmd_mux_i.waddr_fifo_out[13:0]
+x393_testbench01.x393_i.cmd_mux_i.wdata[31:0]
+x393_testbench01.x393_i.cmd_mux_i.wdata_fifo_out[31:0]
+@28
+x393_testbench01.x393_i.cmd_mux_i.wr_en[0]
+@1401200
+-amd_mux
+@c00200
+-status_read
+@22
+x393_testbench01.x393_i.status_read_i.ad[7:0]
+@28
+x393_testbench01.x393_i.status_read_i.axi_clk[0]
+@22
+x393_testbench01.x393_i.status_read_i.axi_status_rdata[31:0]
+x393_testbench01.x393_i.status_read_i.axi_status_rdata_r[31:0]
+x393_testbench01.x393_i.status_read_i.axird_pre_araddr[13:0]
+x393_testbench01.x393_i.status_read_i.axird_raddr[7:0]
+x393_testbench01.x393_i.status_read_i.axird_rdata[31:0]
+@28
+x393_testbench01.x393_i.status_read_i.axird_regen[0]
+x393_testbench01.x393_i.status_read_i.axird_ren[0]
+x393_testbench01.x393_i.status_read_i.axird_selected[0]
+x393_testbench01.x393_i.status_read_i.axird_start_burst[0]
+x393_testbench01.x393_i.status_read_i.clk[0]
+@22
+x393_testbench01.x393_i.status_read_i.dstb[3:0]
+@28
+x393_testbench01.x393_i.status_read_i.rd[0]
+x393_testbench01.x393_i.status_read_i.regen[0]
+x393_testbench01.x393_i.status_read_i.rq[0]
+x393_testbench01.x393_i.status_read_i.rq_r[0]
+x393_testbench01.x393_i.status_read_i.rst[0]
+x393_testbench01.x393_i.status_read_i.select_d[0]
+x393_testbench01.x393_i.status_read_i.select_r[0]
+x393_testbench01.x393_i.status_read_i.select_w[0]
+x393_testbench01.x393_i.status_read_i.start[0]
+@22
+x393_testbench01.x393_i.status_read_i.waddr[7:0]
+x393_testbench01.x393_i.status_read_i.wdata[31:0]
+@28
+x393_testbench01.x393_i.status_read_i.we[0]
+@1401200
+-status_read
+@200
+-
+@c00200
+-readback
+@28
+x393_testbench01.x393_i.cmd_readback_i.ad_stb[0]
+x393_testbench01.x393_i.cmd_readback_i.axi_clk[0]
+@22
+x393_testbench01.x393_i.cmd_readback_i.axi_rback_rdata[31:0]
+x393_testbench01.x393_i.cmd_readback_i.axi_rback_rdata_r[31:0]
+x393_testbench01.x393_i.cmd_readback_i.axird_pre_araddr[13:0]
+x393_testbench01.x393_i.cmd_readback_i.axird_raddr[9:0]
+x393_testbench01.x393_i.cmd_readback_i.axird_rdata[31:0]
+@28
+x393_testbench01.x393_i.cmd_readback_i.axird_regen[0]
+x393_testbench01.x393_i.cmd_readback_i.axird_ren[0]
+x393_testbench01.x393_i.cmd_readback_i.axird_selected[0]
+x393_testbench01.x393_i.cmd_readback_i.axird_start_burst[0]
+x393_testbench01.x393_i.cmd_readback_i.mclk[0]
+@22
+x393_testbench01.x393_i.cmd_readback_i.par_data[31:0]
+x393_testbench01.x393_i.cmd_readback_i.par_waddr[13:0]
+@28
+x393_testbench01.x393_i.cmd_readback_i.rd[0]
+x393_testbench01.x393_i.cmd_readback_i.regen[0]
+x393_testbench01.x393_i.cmd_readback_i.rst[0]
+x393_testbench01.x393_i.cmd_readback_i.select_d[0]
+x393_testbench01.x393_i.cmd_readback_i.select_r[0]
+x393_testbench01.x393_i.cmd_readback_i.select_w[0]
+@22
+x393_testbench01.x393_i.cmd_readback_i.waddr[9:0]
+x393_testbench01.x393_i.cmd_readback_i.wdata[31:0]
+@28
+x393_testbench01.x393_i.cmd_readback_i.we[0]
+x393_testbench01.x393_i.cmd_readback_i.we_w[0]
+@1401200
+-readback
 [pattern_trace] 1
 [pattern_trace] 0

x393_testbench01.tf

@@ -25,6 +25,7 @@
 //`define DEBUG_FIFO 1
 `undef WAIT_MRS
 `define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
+`define READBACK_DELAYS 1
 `define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
 // Disabled already passed test to speedup simulation
 //`define TEST_WRITE_LEVELLING 1
@@ -321,6 +322,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
     
     wait_phase_shifter_ready;
     read_all_status;
+    
 // enable output for address/commands to DDR chip    
     enable_cmda(1);
     repeat (16) @(posedge CLK) ;
@@ -588,6 +590,13 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
        
 `endif
 
+`ifdef READBACK_DELAYS    
+  TEST_TITLE = "READBACK";
+  $display("===================== TEST_%s =========================",TEST_TITLE);
+    axi_get_delays;
+`endif    
+
+
   TEST_TITLE = "ALL_DONE";
   $display("===================== TEST_%s =========================",TEST_TITLE);
   #20000;
@@ -596,8 +605,8 @@ end
 // protect from never end
   initial begin
 //       #30000;
-//     #200000;
-     #60000;
+     #200000;
+//     #60000;
     $display("finish testbench 2");
   $finish;
   end