testing read memory as rectangular tiles

includes/x393_parameters.vh

@@ -214,7 +214,7 @@
                                                       // Start XY can be used when read command to start from the middle
                                                       // TODO: Add number of blocks to R/W? (blocks can be different) - total length?
                                                       // Read back current address (for debugging)?
-    parameter MCNTRL_TILED_TILE_WH=         'h7,   // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
+    parameter MCNTRL_TILED_TILE_WHS=         'h7,   // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
     parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
     parameter MCNTRL_TILED_PENDING_CNTR_BITS=2,    // Number of bits to count pending trasfers, currently 2 is enough, but may increase
                                                    // if memory controller will allow programming several sequences in advance to

memctrl/cmd_encod_linear_rd.v

@@ -20,16 +20,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
 `timescale 1ns/1ps
-/*
-Minimal ACTIVATE period =4 Tcm or 10ns, so maksimal no-miss rate is Tck=1.25 ns (800 MHz)
-Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns
-Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column
-Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
-Can read less if just one column
- TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary
- 
- 
-*/
+
 module  cmd_encod_linear_rd #(
 //    parameter BASEADDR = 0,
     parameter ADDRESS_NUMBER=       15,

memctrl/mcntrl393.v

@@ -199,7 +199,7 @@ module  mcntrl393 #(
                                                       // Start XY can be used when read command to start from the middle
                                                       // TODO: Add number of blocks to R/W? (blocks can be different) - total length?
                                                       // Read back current address (for debugging)?
-    parameter MCNTRL_TILED_TILE_WH=         'h7,   // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
+    parameter MCNTRL_TILED_TILE_WHS=         'h7,   // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
     parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
     parameter MCNTRL_TILED_PENDING_CNTR_BITS=2,    // Number of bits to count pending trasfers, currently 2 is enough, but may increase
                                                    // if memory controller will allow programming several sequences in advance to
@@ -570,7 +570,7 @@ module  mcntrl393 #(
         else if (axird_start_burst) select_buf4 <= select_buf4_w;
 
         if      (axi_rst)           axird_selected_r <= 0;
-        else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf1_w ||select_buf2_w;
+        else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf2_w ||select_buf4_w;
     end
     always @ (posedge axi_clk) begin
         if (axiwr_wen) buf_wdata  <= axiwr_data;
@@ -657,7 +657,7 @@ module  mcntrl393 #(
         .MCNTRL_TILED_WINDOW_WH        (MCNTRL_TILED_WINDOW_WH),
         .MCNTRL_TILED_WINDOW_X0Y0      (MCNTRL_TILED_WINDOW_X0Y0),
         .MCNTRL_TILED_WINDOW_STARTXY   (MCNTRL_TILED_WINDOW_STARTXY),
-        .MCNTRL_TILED_TILE_WH          (MCNTRL_TILED_TILE_WH),
+        .MCNTRL_TILED_TILE_WHS          (MCNTRL_TILED_TILE_WHS),
         .MCNTRL_TILED_STATUS_REG_ADDR  (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
         .MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
         .MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),

memctrl/mcntrl393_test01.v

@@ -142,7 +142,7 @@ module  mcntrl393_test01#(
         
         if      (rst)                page_chn4 <= 0;
         else if (frame_start_chn4_r) page_chn4 <= 0;
-        else if (page_ready_chn4)    page_chn4 <= page_chn2 + 1;
+        else if (page_ready_chn4)    page_chn4 <= page_chn4 + 1;
 
         if      (rst)            suspend_chn2_r <= 0;
         else if (set_chh2_mode)  suspend_chn2_r <= cmd_suspend_w;

util_modules/fifo_2regs.v

+/*******************************************************************************
+ * Module: fifo_2regs
+ * Date:2015-02-17  
+ * Author: andrey     
+ * Description: Simple two-register FIFO, no over/under check,
+ * behaves correctly only for correct inputs
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * fifo_2regs.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  fifo_2regs.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  fifo_2regs #(
+    parameter WIDTH =16)
+     (
+     input              rst,
+     input              clk,
+     input  [WIDTH-1:0] din,
+     input              wr,
+     input              rd,
+     input              srst,
+     output [WIDTH-1:0] dout
+);
+    reg              full_out;
+    reg              full_in;
+    reg  [WIDTH-1:0] reg_out;
+    reg  [WIDTH-1:0] reg_in;
+    
+    assign dout=reg_out;
+    always @ (posedge rst or posedge clk) begin
+        if      (rst)      full_out <=0;
+        else if (srst)     full_out <=0;
+        else if (wr || rd) full_out <= !(!wr && rd && !full_in);
+        
+        if      (rst)      full_in <=0;
+        else if (srst)     full_in <=0;
+        else if (wr ^rd)   full_in <= wr && (full_out || full_in);
+    end
+    always @ (posedge clk) begin
+        if (wr)                      reg_in <=  din;
+        
+        if (wr && (!full_out || rd)) reg_out <=  din;
+        else if (rd)                 reg_out <=  reg_in;
+    end
+
+endmodule
+

x393.v

@@ -219,7 +219,7 @@ module  x393 #(
                                                       // Start XY can be used when read command to start from the middle
                                                       // TODO: Add number of blocks to R/W? (blocks can be different) - total length?
                                                       // Read back current address (for debugging)?
-    parameter MCNTRL_TILED_TILE_WH=         'h7,   // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
+    parameter MCNTRL_TILED_TILE_WHS=         'h7,   // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
     parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
     parameter MCNTRL_TILED_PENDING_CNTR_BITS=2,    // Number of bits to count pending trasfers, currently 2 is enough, but may increase
                                                    // if memory controller will allow programming several sequences in advance to
@@ -729,7 +729,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .MCNTRL_TILED_WINDOW_WH            (MCNTRL_TILED_WINDOW_WH),
         .MCNTRL_TILED_WINDOW_X0Y0          (MCNTRL_TILED_WINDOW_X0Y0),
         .MCNTRL_TILED_WINDOW_STARTXY       (MCNTRL_TILED_WINDOW_STARTXY),
-        .MCNTRL_TILED_TILE_WH              (MCNTRL_TILED_TILE_WH),
+        .MCNTRL_TILED_TILE_WHS             (MCNTRL_TILED_TILE_WHS),
         .MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
         .MCNTRL_TILED_PENDING_CNTR_BITS    (MCNTRL_TILED_PENDING_CNTR_BITS),
         .MCNTRL_TILED_FRAME_PAGE_RESET     (MCNTRL_TILED_FRAME_PAGE_RESET),