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Commit cd7cb395 authored by Andrey Filippov's avatar Andrey Filippov
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testing read memory as rectangular tiles

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includes/x393_parameters.vh
View file @ cd7cb395
......@@ -214,7 +214,7 @@
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
......
memctrl/cmd_encod_linear_rd.v
View file @ cd7cb395
......@@ -20,16 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*
Minimal ACTIVATE period =4 Tcm or 10ns, so maksimal no-miss rate is Tck=1.25 ns (800 MHz)
Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns
Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column
Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
Can read less if just one column
TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary
*/
module cmd_encod_linear_rd #(
// parameter BASEADDR = 0,
parameter ADDRESS_NUMBER= 15,
......
memctrl/cmd_encod_tiled_rd.v
View file @ cd7cb395
......@@ -27,6 +27,17 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*
Minimal ACTIVATE period =4 Tcm or 10ns, so maximal no-miss rate is Tck=1.25 ns (800 MHz)
Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns
Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column
Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns)
Can read less if just one column
TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary
number fo rows>1!
*/
module cmd_encod_tiled_rd #(
// parameter BASEADDR = 0,
......@@ -78,7 +89,7 @@ module cmd_encod_tiled_rd #(
localparam LOOP_FIRST= 5; // address of the first word in a loop
localparam LOOP_LAST= 6; // address of the last word in a loop
localparam CMD_NOP= 0; // 3-bit normal memory RCW commands (positive logic)
localparam CMD_READ= 3;
localparam CMD_READ= 2;
// localparam CMD_PRECHARGE=5;
localparam CMD_ACTIVATE= 4;
// localparam AUTOPRECHARGE_BIT=COLADDR_NUMBER;
......@@ -94,7 +105,7 @@ module cmd_encod_tiled_rd #(
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d;
reg gen_run_d; // to output "done"?
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
reg [ROM_WIDTH-1:0] rom_r;
......@@ -114,40 +125,52 @@ module cmd_encod_tiled_rd #(
reg start_d; // start, delayed by 1 clocks
wire last_row;
reg [FULL_ADDR_NUMBER-1:0] row_col_bank; // RA,CA, BA - valid @pre_act;
reg [FULL_ADDR_NUMBER-1:0] row_col_bank_inc; // incremented RA,CA, BA - valid @pre_act_d;
reg [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
/// reg [FULL_ADDR_NUMBER-1:0] row_col_bank_inc; // incremented RA,CA, BA - valid @pre_act_d;
// reg [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
wire [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
// reg [COLADDR_NUMBER-1:0] pre_col_bank;// CA, BA - valid @ pre_read;
wire enable_act;
// wire enable_autopre;
reg enable_autopre;
reg pre_act_d;
reg other_row; // other than first row (valid/changed @pre_act)
// reg pre_act_d;
// reg other_row; // other than first row (valid/changed @pre_act)
wire [2:0] next_bank_w;
wire [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] next_rowcol_w; // next row/col when bank rolls over (in 8-bursts)
reg loop_continue;
reg last_col_d; // delay by 1 pre_act cycles;
wire [FULL_ADDR_NUMBER-1:0] row_col_bank_next_w; // RA,CA, BA - valid @pre_act;
assign row_col_bank_next_w= last_row?
{top_rc,bank}: // can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile)
(&row_col_bank[2:0]? // bank==7
{next_rowcol_w,3'b0}:
{row_col_bank[FULL_ADDR_NUMBER-1:3],next_bank_w});
assign pre_done=rom_r[ENC_PRE_DONE] && gen_run;
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b0}; // disable bit 1 if activate is disabled (not the first column)
assign rom_cmd= rom_r[ENC_CMD_SHIFT+:2] & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
assign rom_skip= rom_r[ENC_PAUSE_SHIFT+:2];
assign full_cmd= rom_cmd[1]?CMD_ACTIVATE:(rom_cmd[0]?CMD_READ:CMD_NOP);
assign last_row= (scan_row==num_rows_m1);
assign enable_act= first_col || !keep_open; // TODO: do not forget to zero addresses too (or they will become pause/done)
assign next_bank_w= bank+1;
assign next_bank_w= row_col_bank[2:0]+1; //bank+1;
assign next_rowcol_w=row_col_bank[FULL_ADDR_NUMBER-1:3]+rowcol_inc;
assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
// assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
// assign pre_act= gen_run_d && rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
assign pre_act= gen_run && rom_cmd[1]; //1 cycle before optional ACTIVATE
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
else if (start) gen_run<= 1;
// else if (start) gen_run<= 1;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
......@@ -162,25 +185,33 @@ module cmd_encod_tiled_rd #(
else start_d <= start;
if (rst) top_rc <= 0;
else if (start_d) top_rc <= {row,col};
else if (start_d) top_rc <= {row,col}+1;
else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
/*
if (rst) pre_act_d <= 0;
else if (start_d) pre_act_d <= 0;
/// else if (start_d) pre_act_d <= 0;
else pre_act_d <= pre_act;
if (rst) other_row <= 0;
else if (pre_act) other_row <= ~last_row;
*/
if (rst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank};
else if (pre_act_d && ~other_row) row_col_bank <= {top_rc,bank};
else if (pre_act_d) row_col_bank <= row_col_bank_inc;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
//TODO: maybe better to move 1 cicle later everything?
// else if (start) row_col_bank <= {start_row,start_col,start_bank}; // TODO: Use start_col,... and start, not start_d?
// else if (pre_act_d && ~other_row) row_col_bank <= {top_rc,bank};
// else if (pre_act_d && last_row) row_col_bank <= {top_rc,bank};
// else if (pre_act_d) row_col_bank <= row_col_bank_inc;
// else if (pre_act && last_row) row_col_bank <= {top_rc,bank};
// else if (pre_act) row_col_bank <= row_col_bank_inc;
if (rst) row_col_bank_inc<=0;
else row_col_bank_inc<=(&row_col_bank_inc[2:0]!=0)?
{row_col_bank_inc[FULL_ADDR_NUMBER-1:3],next_bank_w}:
{next_rowcol_w,row_col_bank_inc[2:0]};
else if (pre_act) row_col_bank <= row_col_bank_next_w;
/// if (rst) row_col_bank_inc<=0;
/// else row_col_bank_inc<=(&row_col_bank_inc[2:0]!=0)?
/// {row_col_bank_inc[FULL_ADDR_NUMBER-1:3],next_bank_w}:
/// {next_rowcol_w,row_col_bank_inc[2:0]};
if (rst) scan_row <= 0;
else if (start_d) scan_row <= 0;
......@@ -206,15 +237,22 @@ module cmd_encod_tiled_rd #(
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col_d || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
//pre_col_bank
/*
if (rst) pre_col_bank<=0;
else if (start_d) pre_col_bank<= {col,bank};
else if (pre_act) pre_col_bank<= row_col_bank[COLADDR_NUMBER-1:0];
if (rst) col_bank<=0;
else if (start_d) col_bank<= {col,bank};
else if (pre_read) col_bank<= row_col_bank[COLADDR_NUMBER-1:0];
else if (pre_read) col_bank<= pre_col_bank; //row_col_bank[COLADDR_NUMBER-1:0];
*/
if (rst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
else if (!start && !gen_run) gen_addr <= 0;
// else if (!start && !gen_run) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
end
......@@ -232,16 +270,16 @@ module cmd_encod_tiled_rd #(
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
......@@ -256,7 +294,7 @@ module cmd_encod_tiled_rd #(
else enc_wr <= gen_run || gen_run_d;
if (rst) enc_done <= 0;
else enc_done <= enc_wr || !gen_run_d;
else enc_done <= enc_wr && !gen_run_d;
if (rst) enc_cmd <= 0;
else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
......@@ -282,7 +320,7 @@ module cmd_encod_tiled_rd #(
3'b0}, // [14:0] addr; // 15-bit row/column adderss
rom_cmd[1]?
row_col_bank[2:0]:
col_bank[2:0], // bank (here OK to be any)
col_bank[2:0], //
full_cmd[2:0], // rcw; // RAS/CAS/WE, positive logic
1'b0, // odt_en; // enable ODT
1'b0, // cke; // disable CKE
......@@ -296,6 +334,17 @@ module cmd_encod_tiled_rd #(
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT] && !skip_next_page); // buf_rst; // connect to external buffer (but only if not paused)
end
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
.rd(pre_read), // input
.srst(start_d), // input
.dout(col_bank) // output[15:0]
);
// move to include?, Yes, after fixing problem with paths
// move to include?
......
memctrl/mcntrl393.v
View file @ cd7cb395
......@@ -199,7 +199,7 @@ module mcntrl393 #(
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
......@@ -570,7 +570,7 @@ module mcntrl393 #(
else if (axird_start_burst) select_buf4 <= select_buf4_w;
if (axi_rst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf1_w ||select_buf2_w;
else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf2_w ||select_buf4_w;
end
always @ (posedge axi_clk) begin
if (axiwr_wen) buf_wdata <= axiwr_data;
......@@ -657,7 +657,7 @@ module mcntrl393 #(
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
......
memctrl/mcntrl393_test01.v
View file @ cd7cb395
......@@ -142,7 +142,7 @@ module mcntrl393_test01#(
if (rst) page_chn4 <= 0;
else if (frame_start_chn4_r) page_chn4 <= 0;
else if (page_ready_chn4) page_chn4 <= page_chn2 + 1;
else if (page_ready_chn4) page_chn4 <= page_chn4 + 1;
if (rst) suspend_chn2_r <= 0;
else if (set_chh2_mode) suspend_chn2_r <= cmd_suspend_w;
......
memctrl/mcntrl_tiled_rw.v
View file @ cd7cb395
......@@ -40,7 +40,8 @@ module mcntrl_tiled_rw#(
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low byte - 6-bit tile width in 8-bursts, second byte - tile height (0 - > 64),
// 3-rd byte - vertical step (to control tile vertical overlap)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
......@@ -75,7 +76,7 @@ module mcntrl_tiled_rw#(
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
output [FRAME_WIDTH_BITS:0] rowcol_inc, // increment row+col (after bank) for the new scan line in 8-bursts (externally pad with 0)
output [MAX_TILE_WIDTH-1:0] num_rows_m1, // number of rows to read minus 1
output [MAX_TILE_HEIGHT-1:0] num_cols_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
output [MAX_TILE_HEIGHT-1:0] num_cols_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // (programmable bit)keep banks open (for <=8 banks only
output xfer_partial, // partial tile (first of 2) , sequencer will not generate page_next at the end of block
input xfer_page_done, // transfer to/from the buffer finished (partial transfers should not generate), use rpage_nxt_chn@mclk
......@@ -84,7 +85,7 @@ module mcntrl_tiled_rw#(
//MAX_TILE_WIDTH
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
localparam PAR_MOD_LATENCY= 7; // TODO: Find actual worst-case latency for:
localparam PAR_MOD_LATENCY= 9; // TODO: Find actual worst-case latency for:
reg [FRAME_WIDTH_BITS-1:0] curr_x; // (calculated) start of transfer x (relative to window left)
reg [FRAME_HEIGHT_BITS-1:0] curr_y; // (calculated) start of transfer y (relative to window top)
reg [FRAME_HEIGHT_BITS:0] next_y; // (calculated) next row number
......@@ -130,7 +131,8 @@ module mcntrl_tiled_rw#(
reg last_block;
reg [MCNTRL_TILED_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers (to genearate frame done)
reg [NUM_RC_BURST_BITS-1:0] row_col_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r [1:0];
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r0;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r1;
wire pre_want;
wire [1:0] status_data;
wire [3:0] cmd_a;
......@@ -144,18 +146,20 @@ module mcntrl_tiled_rw#(
wire set_window_wh_w;
wire set_window_x0y0_w;
wire set_window_start_w;
wire set_tile_wh_w;
wire set_tile_whs_w;
wire lsw13_zero=!(|cmd_data[FRAME_WIDTH_BITS-1:0]); // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
// wire msw13_zero=!(|cmd_data[FRAME_WIDTH_BITS+15:16]); // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
wire tile_width_zero= !(|cmd_data[MAX_TILE_WIDTH-1:0]);
wire tile_height_zero=!(|cmd_data[MAX_TILE_HEIGHT+15:16]);
wire tile_width_zero= !(|cmd_data[ 0+:MAX_TILE_WIDTH]);
wire tile_height_zero=!(|cmd_data[ 8+:MAX_TILE_HEIGHT]);
wire tile_vstep_zero= !(|cmd_data[16+:MAX_TILE_HEIGHT]);
// reg [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
reg [4:0] mode_reg;//mode register: {keep_open,extra_pages[1:0],enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT:0] tile_vstep; // vertical step between rows of tiles
reg [MAX_TILE_WIDTH:0] num_cols_r; // full number of columns to transfer (not minus 1)
wire [MAX_TILE_WIDTH:0] num_cols_m1_w; // full number of columns to transfer minus 1 with extra bit
......@@ -165,6 +169,7 @@ module mcntrl_tiled_rw#(
// otherwise (smaller widths) round up to the nearest power of 2
reg [FRAME_WIDTH_BITS:0] window_width; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_height; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_m_tile_height; // (window height-tile height
reg [FRAME_WIDTH_BITS-1:0] window_x0; // (programmed) window left
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
......@@ -178,7 +183,7 @@ module mcntrl_tiled_rw#(
assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_WH);
assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_X0Y0);
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
assign set_tile_wh_w = cmd_we && (cmd_a== MCNTRL_TILED_TILE_WH);
assign set_tile_whs_w = cmd_we && (cmd_a== MCNTRL_TILED_TILE_WHS);
//
// Set parameter registers
always @(posedge rst or posedge mclk) begin
......@@ -202,9 +207,11 @@ module mcntrl_tiled_rw#(
if (rst) begin
tile_cols <= 0;
tile_rows <= 0;
end else if (set_tile_wh_w) begin
tile_cols <= {tile_width_zero, cmd_data[MAX_TILE_WIDTH-1:0]};
tile_rows <= {tile_height_zero, cmd_data[MAX_TILE_HEIGHT+15:16]};
tile_vstep <= 0;
end else if (set_tile_whs_w) begin
tile_cols <= {tile_width_zero, cmd_data[ 0+:MAX_TILE_WIDTH]};
tile_rows <= {tile_height_zero, cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_vstep <= {tile_vstep_zero, cmd_data[16+:MAX_TILE_HEIGHT]};
end
if (rst) begin
......@@ -230,13 +237,16 @@ module mcntrl_tiled_rw#(
assign frame_done= frame_done_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
assign last_row_w= next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors
// assign last_row_w= next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors
assign last_row_w= next_y > window_m_tile_height; // (next_y==window_height) is faster, but will not forgive software errors
//window_m_tile_height
assign xfer_want= want_r;
assign xfer_need= need_r;
assign xfer_bank= bank_reg[2]; // TODO: just a single reg layer
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished=line_unfinished_r[1];
// assign line_unfinished=line_unfinished_r[1];
assign line_unfinished=line_unfinished_r1;
assign chn_en = &mode_reg[1:0]; // enable requests by channle (continue ones in progress)
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
......@@ -266,11 +276,27 @@ module mcntrl_tiled_rw#(
if (recalc_r[0]) begin
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
next_y <= curr_y + tile_rows;
// next_y <= curr_y + tile_rows;
next_y <= curr_y + tile_vstep;
row_left <= window_width - curr_x; // 14 bits - 13 bits
end
// cycle 2
if (recalc_r[1]) begin
// registers to be absorbed in DSP block
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2 // if (recalc_r[2]) begin
frame_full_width_r <= frame_full_width; //(cycle 2) // if (recalc_r[2]) begin
start_addr_r <= start_addr; // // if (recalc_r[2]) begin
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3; if (recalc_r[3]) begin
line_start_addr <= start_addr_r+mul_rslt; // lat=4 if (recalc_r[4]) begin
// TODO: Verify MPY/register timing above
if (recalc_r[5]) begin // cycle 6
row_col_r <= line_start_addr+frame_x;
// line_start_page_left <= {COLADDR_NUMBER-3{1'b0}} - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
if (recalc_r[6]) begin // cycle 7
// mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];
......@@ -279,8 +305,8 @@ module mcntrl_tiled_rw#(
tile_cols:
row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
end
// cycle 3
if (recalc_r[2]) begin
if (recalc_r[7]) begin // cycle 8
xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_tile;
num_cols_r<= continued_tile?
{EXTRA_BITS,leftover_cols}:
......@@ -291,25 +317,11 @@ module mcntrl_tiled_rw#(
// VDT bug? next line gives a warning
// xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
// cycle 4
if (recalc_r[3]) begin
if (recalc_r[8]) begin // cycle 9
last_in_row <= last_in_row_w;
end
// registers to be absorbed in DSP block
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2 // if (recalc_r[2]) begin
frame_full_width_r <= frame_full_width; //(cycle 2) // if (recalc_r[2]) begin
start_addr_r <= start_addr; // // if (recalc_r[2]) begin
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3; if (recalc_r[3]) begin
line_start_addr <= start_addr_r+mul_rslt; // lat=4 if (recalc_r[4]) begin
// TODO: Verify MPY/register timing above
if (recalc_r[5]) begin
row_col_r <= line_start_addr+frame_x;
// line_start_page_left <= {COLADDR_NUMBER-3{1'b0}} - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
window_m_tile_height <= window_height - tile_rows;
end
// now have row start address, bank and row_left ;
......@@ -325,7 +337,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) recalc_r<=0;
else if (chn_rst) recalc_r<=0;
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
// else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_start_r[0] & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
......@@ -369,7 +382,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) last_block <= 0;
else if (chn_rst || !busy_r) last_block <= 0;
else if (last_row_w && last_in_row_w) last_block <= 1;
// else if (last_row_w && last_in_row_w) last_block <= 1;
else if (xfer_start_r[0]) last_block <= last_row_w && last_in_row_w;
// start_not_partial is not generated when partial (first of 2, caused by a tile crossing memory page) transfer is requested
// here we need to cout all requests - partial or not
......@@ -384,6 +398,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else frame_done_r <= busy_r && last_block && xfer_page_done && (pending_xfers==0);
//line_unfinished_r cmd_wrmem
/*
if (rst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
......@@ -394,6 +409,18 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[1] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[1] <= line_unfinished_r[0];
*/
if (rst) line_unfinished_r0 <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r0 <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r0 <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (rst) line_unfinished_r1 <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r1 <= window_y0+start_y;
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r1 <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r1 <= line_unfinished_r0;
end
......
util_modules/fifo_2regs.v 0 → 100644
View file @ cd7cb395
/*******************************************************************************
* Module: fifo_2regs
* Date:2015-02-17
* Author: andrey
* Description: Simple two-register FIFO, no over/under check,
* behaves correctly only for correct inputs
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* fifo_2regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fifo_2regs.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module fifo_2regs #(
parameter WIDTH =16)
(
input rst,
input clk,
input [WIDTH-1:0] din,
input wr,
input rd,
input srst,
output [WIDTH-1:0] dout
);
reg full_out;
reg full_in;
reg [WIDTH-1:0] reg_out;
reg [WIDTH-1:0] reg_in;
assign dout=reg_out;
always @ (posedge rst or posedge clk) begin
if (rst) full_out <=0;
else if (srst) full_out <=0;
else if (wr || rd) full_out <= !(!wr && rd && !full_in);
if (rst) full_in <=0;
else if (srst) full_in <=0;
else if (wr ^rd) full_in <= wr && (full_out || full_in);
end
always @ (posedge clk) begin
if (wr) reg_in <= din;
if (wr && (!full_out || rd)) reg_out <= din;
else if (rd) reg_out <= reg_in;
end
endmodule
x393.v
View file @ cd7cb395
......@@ -219,7 +219,7 @@ module x393 #(
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
......@@ -729,7 +729,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
......
x393_testbench01.sav
View file @ cd7cb395
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Tue Feb 17 01:52:35 2015
[*] Wed Feb 18 07:37:00 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150216153037852.lxt"
[dumpfile_mtime] "Mon Feb 16 22:50:05 2015"
[dumpfile_size] 1073751632
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150218002858125.lxt"
[dumpfile_mtime] "Wed Feb 18 07:36:06 2015"
[dumpfile_size] 380535673
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 52831600
[size] 1823 1173
[timestart] 55744200
[size] 1823 1180
[pos] 1927 0
*-14.698502 52944323 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-16.698502 56050000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
......@@ -27,11 +27,11 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 264
[signals_width] 445
[sst_width] 260
[signals_width] 369
[sst_expanded] 1
[sst_vpaned_height] 383
@800200
@c00200
-top_simulation
@28
x393_testbench01.CLK[0]
......@@ -150,10 +150,7 @@ x393_testbench01.wait_status_condition.status_control_address[29:0]
x393_testbench01.wait_status_condition.status_mode[1:0]
@1401200
-WAIT_STATUS_CONDITION
@1000200
-top_simulation
@200
-
@c00200
-axi
@28
......@@ -891,9 +888,7 @@ x393_testbench01.x393_i.SDA[14:0]
x393_testbench01.x393_i.SDBA[2:0]
@28
x393_testbench01.x393_i.SDRAS[0]
@29
x393_testbench01.x393_i.SDCAS[0]
@28
x393_testbench01.x393_i.SDWE[0]
x393_testbench01.x393_i.DQSL[0]
x393_testbench01.x393_i.DQSU[0]
......@@ -1330,6 +1325,419 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
-mcntrl393_test01
@22
x393_testbench01.ii[31:0]
@800200
-gtiled_ch4
@28
x393_testbench01.x393_i.mcntrl393_i.select_buf4[0]
@22
x393_testbench01.x393_i.mcntrl393_i.buf4_data[31:0]
x393_testbench01.x393_i.mcntrl393_i.axird_rdata[31:0]
x393_testbench01.x393_i.mcntrl_axird_rdata[31:0]
@28
x393_testbench01.x393_i.mcntrl_axird_selected[0]
@c00201
-ch4_4
@22
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.data_in[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ext_data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ext_raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ext_rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ext_regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.waddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.we[0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.wpage_set[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.ram_512x64w_1kx32r_i.waddr[8:0]
@1401201
-ch4_4
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pre_want[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_x[12:0]
@800022
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(5)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(6)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(7)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(8)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.rpage_nxt_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.line_unfinished_chn4[15:0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn4[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_col_r[21:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_y0[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished_r0[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished_r1[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pre_want[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width_r[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_y0[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_rows[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_height[16:0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_partial[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.keep_open[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.chn_rst_d[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.cmd_wrmem[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.continued_tile[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.curr_y[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_done_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_full_width_r[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.i[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.leftover_cols[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.lim_by_tile_width[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_start_page_left[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.line_unfinished[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mem_page_left[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mode_reg[4:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.msw_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.mul_rslt_w[26:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_page[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_m1_w[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_cols_r[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.num_rows_m1_w[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.page_cntr[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.pre_want[0]
@800022
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(4)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(5)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(6)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(7)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
(8)x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
@1001200
-group_end
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.remainder_tile_width[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.row_left[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rowcol_inc[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_start_addr_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_tile_whs_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.set_window_x0y0_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_addr_r[21:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_not_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.start_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.suspend[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_cols[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_height_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_rows[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_vstep_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.tile_width_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_y0[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_limited_by_mem_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_limited_by_mem_page_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_need[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_page_rst_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_row[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0]
@1000200
-gtiled_ch4
@c00200
-encod_tiled
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols128_m1[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.skip_next_page[0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_read[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rom_r[9:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rom_cmd[1:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_row[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.top_rc[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank_next_w[24:0]
@c00022
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(1)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(2)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(3)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(4)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(5)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(6)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(7)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(8)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(9)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(10)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(11)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(12)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(13)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(14)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(15)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(16)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(17)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(18)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(19)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(20)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(21)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(22)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(23)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
(24)x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
@1401200
-group_end
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.next_bank_w[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_wr[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_done[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.col_bank[9:0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.col_bank[9:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enable_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enable_autopre[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.first_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.full_cmd[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_run_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.keep_open_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_row[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.loop_continue[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.next_bank_w[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.next_rowcol_w[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols128_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_rows_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_read[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rom_cmd[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rom_r[9:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rom_skip[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row_col_bank[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rowcol_inc_in[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.scan_col[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.scan_row[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.top_rc[21:0]
@1401200
-encod_tiled
@200
-
@c00200
......@@ -1532,7 +1940,7 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rd_i.start_col[6:0]
@1401200
-read_block_scanline
@800200
@c00200
-linear_ch3
@200
-
......@@ -1733,9 +2141,9 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_linear_rw_chn3_i.xfer_want[0]
@1000200
@1401200
-linear_ch3
@800200
@c00200
-cmd1_buf
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel[0]
......@@ -1769,7 +2177,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.wc
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.web[3:0]
@1000200
@1401200
-cmd1_buf
@200
-
......
x393_testbench01.tf
View file @ cd7cb395
......@@ -33,9 +33,10 @@
`define TEST_SCANLINE_WRITE 1
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_SCANLINE_READ 1
`define TEST_SCANLINE_READ_SHOW 1
//`define TEST_SCANLINE_READ 1
`define TEST_READ_SHOW 1
`define TEST_TILED_READ 1
module x393_testbench01 #(
......@@ -198,24 +199,41 @@ module x393_testbench01 #(
localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)
// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
// localparam SCANLINE_WINDOW_WH= 'h0009000b; // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
localparam SCANLINE_WINDOW_W= 'h005b; //'h000b; // 176: 13-bit window width (0->'h4000)
localparam SCANLINE_WINDOW_H= 'h0009; // 9: 16-bit frame height (0->'h10000)
localparam WINDOW_WIDTH= 'h000b; //'h005b; //'h000b; // 176: 13-bit window width (0->'h4000)
localparam WINDOW_HEIGHT= 'h000a; // 9: 16-bit window height (0->'h10000)
// localparam SCANLINE_X0Y0= 'h00050003; // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
localparam SCANLINE_X0= 'h005c; // 'h7c; // 'h0003; // X0=3*16=48 - 13-bit window left
localparam SCANLINE_Y0= 'h0005; // Y0=5: 16-bit window top
localparam WINDOW_X0= 'h005c; // 'h7c; // 'h0003; // X0=3*16=48 - 13-bit window left
localparam WINDOW_Y0= 'h0005; // Y0=5: 16-bit window top
// localparam SCANLINE_STARTXY= 'h0; // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
localparam SCANLINE_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam SCANLINE_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] SCANLINE_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam TILED_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam TILED_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] TILED_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam TILED_KEEP_OPEN= 1'b0; // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)
localparam TILE_WIDTH= 'h03; // 6-bit tile width (1..'h40)
localparam TILE_HEIGHT= 'h06; // 6-bit tile height (1..'h40)
localparam TILE_VSTEP= 'h04; // 6-bit tile vertical step, with no overlap it is equal to TILE_HEIGHT (1..'h40)
localparam TEST01_START_FRAME= 1;
localparam TEST01_NEXT_PAGE= 2;
localparam TEST01_SUSPEND= 4;
//NUM_XFER_BITS=6
localparam SCANLINE_PAGES_PER_ROW= (SCANLINE_WINDOW_W>>NUM_XFER_BITS)+((SCANLINE_WINDOW_W[NUM_XFER_BITS-1:0]==0)?0:1);
localparam SCANLINE_PAGES_PER_ROW= (WINDOW_WIDTH>>NUM_XFER_BITS)+((WINDOW_WIDTH[NUM_XFER_BITS-1:0]==0)?0:1);
localparam TILES_PER_ROW= (WINDOW_WIDTH/TILE_WIDTH)+ ((WINDOW_WIDTH % TILE_WIDTH==0)?0:1);
localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-TILE_HEIGHT)/TILE_VSTEP) + (((WINDOW_HEIGHT-TILE_HEIGHT)%TILE_VSTEP==0)?0:1) +1;
localparam TILE_SIZE= TILE_WIDTH*TILE_HEIGHT;
// localparam integer SCANLINE_FULL_XFER= 1<<NUM_XFER_BITS; // 64 - full page transfer in 8-bursts
// localparam integer SCANLINE_LAST_XFER= SCANLINE_WINDOW_W % (1<<NUM_XFER_BITS); // last page transfer size in a row
// localparam integer SCANLINE_LAST_XFER= WINDOW_WIDTH % (1<<NUM_XFER_BITS); // last page transfer size in a row
integer ii;
integer SCANLINE_XFER_SIZE;
......@@ -377,8 +395,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
`ifdef TEST_SCANLINE_WRITE
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_WH, SCANLINE_WINDOW_W + (SCANLINE_WINDOW_H<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, SCANLINE_X0+ (SCANLINE_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
......@@ -394,8 +412,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
*/
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
// SCANLINE_CUR_X = SCANLINE_X0 + ((ii % SCANLINE_PAGES_PER_ROW) << NUM_XFER_BITS);
// SCANLINE_CUR_Y = SCANLINE_Y0 + (ii / SCANLINE_PAGES_PER_ROW);
// SCANLINE_CUR_X = WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW) << NUM_XFER_BITS);
// SCANLINE_CUR_Y = WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW);
// VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
......@@ -403,24 +421,24 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(SCANLINE_WINDOW_W % (1<<NUM_XFER_BITS))
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(SCANLINE_WINDOW_W));
(WINDOW_WIDTH));
write_block_scanline_chn(
3,
(ii & 3),
SCANLINE_XFER_SIZE,
SCANLINE_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
SCANLINE_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);\
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);\
end
/*
localparam SCANLINE_FULL_XFER= 1<<NUM_XFER_BITS; // 64 - full page transfer in 8-bursts
localparam SCANLINE_LAST_XFER= SCANLINE_WINDOW_W % (1<<NUM_XFER_BITS); // last page transfer size in a row
localparam SCANLINE_LAST_XFER= WINDOW_WIDTH % (1<<NUM_XFER_BITS); // last page transfer size in a row
*/
for (ii=0;ii< (SCANLINE_WINDOW_H * SCANLINE_PAGES_PER_ROW) ;ii = ii+1) begin // here assuming 1 page per line
for (ii=0;ii< (WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW) ;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
......@@ -429,23 +447,23 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// write_block_scanline_chn(3, (ii & 3), SCANLINE_WINDOW_W, SCANLINE_X0,SCANLINE_Y0+ii);
// write_block_scanline_chn(3, (ii & 3), WINDOW_WIDTH, WINDOW_X0,WINDOW_Y0+ii);
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(SCANLINE_WINDOW_W % (1<<NUM_XFER_BITS))
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(SCANLINE_WINDOW_W));
(WINDOW_WIDTH));
write_block_scanline_chn(
3,
(ii & 3),
SCANLINE_XFER_SIZE,
SCANLINE_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
SCANLINE_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);
end
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
end
......@@ -463,8 +481,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
// program to the
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_WH, SCANLINE_WINDOW_W + (SCANLINE_WINDOW_H<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, SCANLINE_X0+ (SCANLINE_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
......@@ -472,17 +490,17 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
enable_memcntrl_channels(16'h000f); // channels 0,1,2,3 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE, TEST01_START_FRAME);
for (ii=0;ii<(SCANLINE_WINDOW_H * SCANLINE_PAGES_PER_ROW);ii = ii+1) begin
for (ii=0;ii<(WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW);ii = ii+1) begin
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(SCANLINE_WINDOW_W % (1<<NUM_XFER_BITS))
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(SCANLINE_WINDOW_W));
(WINDOW_WIDTH));
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
......@@ -492,7 +510,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// read block (if needed), for now just sikip
`ifdef TEST_SCANLINE_READ_SHOW
`ifdef TEST_READ_SHOW
read_block_buf_chn (
2,
(ii & 3),
......@@ -503,6 +521,40 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
end
`endif
`ifdef TEST_TILED_READ
// program to the
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_MODE, {27'b0,TILED_KEEP_OPEN,TILED_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(4,0); // lowest priority channel 2
enable_memcntrl_channels(16'h001f); // channels 0,1,2,3,4 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE, TEST01_START_FRAME);
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
ii << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// read block (if needed), for now just sikip
`ifdef TEST_READ_SHOW
read_block_buf_chn (
4, // channel
(ii & 3), // page
TILE_SIZE << 2, // length in 32-bit words
1 ); // chn=4, page=?, number of 32-bit words=?, wait_done
`endif
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE, TEST01_NEXT_PAGE);
end
`endif
#20000;
$finish;
end
......@@ -702,7 +754,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WH (MCNTRL_TILED_TILE_WH),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
......
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