Loading memctrl/mcntrl393.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -218,7 +218,7 @@ module mcntrl393 #( ) ( ) ( input rst_in, input rst_in, input clk_in, input clk_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // programming interface // programming interface input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d Loading memctrl/mcntrl393_test01.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -38,7 +38,7 @@ module mcntrl393_test01#( parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4 parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4 )( )( input rst, input rst, input mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // programming interface // programming interface input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d Loading memctrl/memctrl16.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -140,7 +140,7 @@ module memctrl16 #( ) ( ) ( input rst_in, input rst_in, input clk_in, input clk_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // programming interface // programming interface input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d Loading memctrl/phy/ddrc_sequencer.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -68,7 +68,7 @@ module ddrc_sequencer #( // clocks, reset // clocks, reset input clk_in, input clk_in, input rst_in, input rst_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... input cmd0_clk, input cmd0_clk, input cmd0_we, input cmd0_we, Loading memctrl/phy/mcontr_sequencer.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -114,7 +114,7 @@ module mcontr_sequencer #( // clocks, reset // clocks, reset input clk_in, input clk_in, input rst_in, input rst_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... input cmd0_clk, input cmd0_clk, input cmd0_we, input cmd0_we, Loading Loading
memctrl/mcntrl393.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -218,7 +218,7 @@ module mcntrl393 #( ) ( ) ( input rst_in, input rst_in, input clk_in, input clk_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // programming interface // programming interface input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d Loading
memctrl/mcntrl393_test01.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -38,7 +38,7 @@ module mcntrl393_test01#( parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4 parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4 )( )( input rst, input rst, input mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // programming interface // programming interface input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d Loading
memctrl/memctrl16.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -140,7 +140,7 @@ module memctrl16 #( ) ( ) ( input rst_in, input rst_in, input clk_in, input clk_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // programming interface // programming interface input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input cmd_stb, // strobe (with first byte) for the command a/d input cmd_stb, // strobe (with first byte) for the command a/d Loading
memctrl/phy/ddrc_sequencer.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -68,7 +68,7 @@ module ddrc_sequencer #( // clocks, reset // clocks, reset input clk_in, input clk_in, input rst_in, input rst_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... input cmd0_clk, input cmd0_clk, input cmd0_we, input cmd0_we, Loading
memctrl/phy/mcontr_sequencer.v +1 −1 Original line number Original line Diff line number Diff line Loading @@ -114,7 +114,7 @@ module mcontr_sequencer #( // clocks, reset // clocks, reset input clk_in, input clk_in, input rst_in, input rst_in, output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... input cmd0_clk, input cmd0_clk, input cmd0_we, input cmd0_we, Loading
