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Commit c8b01721 authored by Andrey Filippov's avatar Andrey Filippov
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working on infrequent errors when cirbuf rolls over

parent 64e5e516
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Showing with 101 additions and 45 deletions
.project
View file @ c8b01721
......@@ -62,52 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160512172954764.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160512122847249.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160512122847249.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160512122847249.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160512122847249.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160512122847249.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160512120153045.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160513114712446.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160512122847249.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160513115248831.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160512120153045.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160513114712446.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160512120153045.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160513114712446.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -127,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160512120153045.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160513114712446.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ c8b01721
......@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_hispi
VivadoBitstream_124_rawfile=x393_parallel
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1
axi/cmprs_afi_mux.v
View file @ c8b01721
......@@ -207,6 +207,7 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
reg [1:0] winner1; // 2 first level arbitration winners
reg [1:0] winner2; // 2-bit second level arbitration winner
wire [1:0] pre_winner2_w; // 1 cycle ahead of winner2
// reg [1:0] cur_chn; // Can it be the same as cur_chn?
wire [7:0] fifo_count0_m1 = fifo_count0 - 1;
......@@ -290,6 +291,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign {fifo_rst3, fifo_rst2, fifo_rst1, fifo_rst0} = reset_pointers;
assign {fifo_ren3, fifo_ren2, fifo_ren1, fifo_ren0} = fifo_ren;
assign pre_winner2_w = (counts_corr1[1 * 9 +: 9] > counts_corr1[0 * 9 +: 9]) ? {1'b1,winner1[1]} : {1'b0,winner1[0]};
assign afi_awaddr = {chunk_addr,5'b0};
assign afi_awid = afi_awid_r; // {1'b0,wleft[3:2],last_burst_in_frame,cur_chn};
assign afi_awvalid = awvalid[1];
......@@ -306,6 +309,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign afi_awqos = 4'h0;
assign afi_wstrb = 8'hff;
assign afi_wrissuecap1en = 1'b0;
`ifdef DEBUG_RING
debug_slave #(
.SHIFT_WIDTH (64),
......@@ -433,11 +439,14 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
// second arbitration level (latency 3 clk)
if (counts_corr1[1 * 9 +: 9] > counts_corr1[0 * 9 +: 9]) begin
counts_corr2 <= counts_corr1[1 * 9 +: 9];
winner2 <= {1'b1,winner1[1]};
// winner2 <= {1'b1,winner1[1]};
end else begin
counts_corr2 <= counts_corr1[0 * 9 +: 9];
winner2 <= {1'b0,winner1[0]};
// winner2 <= {1'b0,winner1[0]};
end
winner2 <= pre_winner2_w;
//ready_to_start need_to_bother
//done_burst
if (!en) busy <= 0;
......@@ -549,7 +558,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
.en (en), // input
.reset_pointers (reset_pointers), // input[3:0]
.pre_busy_w (pre_busy_w), // input
.winner_channel (winner2), // input[1:0]
.pre_winner_channel (pre_winner2_w), // input[1:0]
// .winner_channel (winner2), // input[1:0]
.need_to_bother (need_to_bother), // input
// .chunk_inc (chunk_inc), // input[2:0]
.chunk_inc_want_m1 (pre_chunk_inc_m1), // input[1:0] Want to increment by this (0..3) + 1, if not roll over
......
axi/cmprs_afi_mux_ptr.v
View file @ c8b01721
......@@ -44,7 +44,8 @@ module cmprs_afi_mux_ptr(
input en, // 0 - resets, 0->1 resets all pointers. While reset allows write response
input [ 3:0] reset_pointers, // per-channel - reset pointers
input pre_busy_w, // combinatorial signal - one before busy[0] (depends on ptr_resetting)
input [ 1:0] winner_channel, // channel that won arbitration for AXI access, valid @ pre_busy_w
input [ 1:0] pre_winner_channel, // channel that won arbitration for AXI access, valid 1 cycle ahead of @ pre_busy_w
// input [ 1:0] winner_channel, // channel that won arbitration for AXI access, valid @ pre_busy_w
input need_to_bother, // wants to start access if address and data FIFO permit
input [1:0] chunk_inc_want_m1, // how much to increment chunk pointer (0..3) +1 - valid with busy[0] (w/o rollover)
......@@ -81,26 +82,34 @@ module cmprs_afi_mux_ptr(
reg [3:0] chunks_to_rollover_r; // [3] >=8
wire [3:0] chunks_to_rollover_m1;
wire [3:0] pre_chunks_to_rollover_m1;
reg max_inc_ram_we;
reg [1:0] max_inc_ram_wa;
wire rollover_w; // this cycle causes rollover - valid at pre_busy_w
reg rollover_r; // this cycle causes rollover - valid at busy[0] and late
reg [ 1:0] winner_channel; // channel that won arbitration for AXI access, valid @ pre_busy_w
wire ptr_ram_wa = ptr_ram[ptr_wa]; // SuppressThisWarning VEditor debug - just to view
// wire [2:0] max_wlen_di; // data to write to max_inc_ram and bypass register
reg [2:0] max_wlen_r; // memory registered output
reg [2:0] max_wlen_same; // used to bypass max_inc_ram for the same channel
// reg use_same_max_wlen; // valid @ pre_busy_w
reg [1:0] last_max_written; // channel for which max_wlen was written to RAM
assign ptr_resetting = resetting[0];
assign sa_len_ra= {busy[1],ptr_wa[1:0]};
assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
reset_rq_pri[3] | reset_rq_pri[1]};
// assign ptr_ram_di= resetting[1] ? 27'b0 : (chunk_ptr_rovr[27] ? chunk_ptr_inc : chunk_ptr_rovr[26:0]);
assign ptr_ram_di= (resetting[1] ||rollover_r) ? 27'b0 : chunk_ptr_inc ;
assign chunk_ptr_rd = ptr_ram[chunk_ptr_ra];
assign start_resetting_w = en && !busy[0] && !resetting[0] && (|reset_rq) && !need_to_bother;
// assign max_inc = max_inc_ram[winner_channel];
assign max_wlen = max_inc_ram[winner_channel]; // valid @pre_busy_w
/// assign max_wlen = max_inc_ram[winner_channel]; // valid @pre_busy_w
// assign max_wlen = (last_max_written == winner_channel) ? (max_inc_ram_we? max_wlen_di: max_wlen_same) :max_wlen_r ; // valid @pre_busy_w
assign max_wlen = (last_max_written == winner_channel) ? max_wlen_same :max_wlen_r ; // valid @pre_busy_w
//chunk_inc_want_m1
assign pre_chunk_inc_m1 = (max_wlen[1:0] >= chunk_inc_want_m1)? chunk_inc_want_m1 : max_wlen[1:0];
......@@ -108,8 +117,15 @@ module cmprs_afi_mux_ptr(
assign chunks_to_rollover = sa_len_ram[sa_len_ra] - ptr_ram_di;
assign chunks_to_rollover_m1 = chunks_to_rollover_r -1;
// assign max_wlen_di = (|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};
// 1 cycle ahead of chunks_to_rollover_m1
assign pre_chunks_to_rollover_m1 = {|chunks_to_rollover[26:3],chunks_to_rollover[2:0]} - 1;
always @ (posedge hclk) begin
winner_channel <= pre_winner_channel;
max_wlen_r <= max_inc_ram[pre_winner_channel]; // valid @pre_busy_w
if (!en) last_max_written <= 0;
else if (ptr_we & ~ptr_wa[2]) last_max_written <= ptr_wa[1:0];
en_d <= en;
// ===== calculate and rollover channel addresses ====
// clear (during "resetting" or update 8x27 RAM that holds chunk pointers for the current burst and currenty frame
......@@ -161,8 +177,16 @@ module cmprs_afi_mux_ptr(
max_inc_ram_we <= ptr_we & ~ptr_wa[2];
max_inc_ram_wa <= ptr_wa[1:0];
if (max_inc_ram_we) max_inc_ram[max_inc_ram_wa] <= (|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};
// set 1 cycle earlier
if (ptr_we & ~ptr_wa[2]) max_wlen_same <= (|pre_chunks_to_rollover_m1[3:2])?3'h7:{1'b0,pre_chunks_to_rollover_m1[1:0]};
if (max_inc_ram_we) begin
max_inc_ram[max_inc_ram_wa] <= max_wlen_same; // max_wlen_di; // (|chunks_to_rollover_m1[3:2])?3'h7:{1'b0,chunks_to_rollover_m1[1:0]};
// max_wlen_same <= max_wlen_di;
end
end
endmodule
......
fpga_version.vh
View file @ c8b01721
......@@ -32,7 +32,9 @@
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393008a; // HiSPI sensor (14 MPix)
// parameter FPGA_VERSION = 32'h0393008c; // hispi, all met, 83.55%
parameter FPGA_VERSION = 32'h0393008b; // parallel, all met, 82.06%
// parameter FPGA_VERSION = 32'h0393008a; // HiSPI sensor (14 MPix) no timing errors
// parameter FPGA_VERSION = 32'h03930089; // Auto-synchronizing i2c sequencers with the command ones
// parameter FPGA_VERSION = 32'h03930088; // Fixing circbuf rollover pointers bug (only one path violated)
// parameter FPGA_VERSION = 32'h03930087; // Fixed default 90% quantization table
......
system_defines.vh
View file @ c8b01721
......@@ -48,7 +48,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
......
x393_hispi.bit
View file @ c8b01721
No preview for this file type
x393_parallel.bit
View file @ c8b01721
No preview for this file type
x393_testbench03.tf
View file @ c8b01721
......@@ -1289,13 +1289,16 @@ assign #10 gpio_pins[9] = gpio_pins[8];
'h10000 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks
*/
'h10000000 >> 5, // input [26:0] afi_cmprs0_sa; // input [26:0] sa; // start address in 32-byte chunks
'hba0 >> 5, // 59e/5e0 (exact 2-1) 'h800 >> 5, // input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks
// 'hba0 >> 5, // 59e/5e0 (exact 2-1) 'h800 >> 5, // input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'hb80 >> 5, // 59e/5e0 (exact 2-2) 'h800 >> 5, // input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h10010000 >> 5, // input [26:0] afi_cmprs1_sa; // input [26:0] sa; // start address in 32-byte chunks
'h640>> 5, // 2f0/320 (exact 2) h400 >> 5, // input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks
// 'h640>> 5, // 2f0/320 (exact 2) h400 >> 5, // input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h600>> 5, // 2f0/320 (exact 2) h400 >> 5, // input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h10020000 >> 5, // input [26:0] afi_cmprs2_sa; // input [26:0] sa; // start address in 32-byte chunks
'h520 >> 5, // 25e/2a0 (1 less)'h200 >> 5, // input [26:0] afi_cmprs2_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h10030000 >> 5, // input [26:0] afi_cmprs3_sa; // input [26:0] sa; // start address in 32-byte chunks
'h460 >> 5); // 1de/ 220 (1 more) 'h100 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks
// 'h460 >> 5); // 1de/ 220 (1 more) 'h100 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks
'h400 >> 5); // 1de/ 220 (2 less) 'h100 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks
camsync_setup (
4'hf ); // sensor_mask); //
......
x393_testbench04.sav
View file @ c8b01721
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun May 8 03:34:28 2016
[*] Fri May 13 15:32:02 2016
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160507180624832.fst"
[dumpfile_mtime] "Sun May 8 00:54:54 2016"
[dumpfile_size] 169675454
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160513083231165.fst"
[dumpfile_mtime] "Fri May 13 15:20:12 2016"
[dumpfile_size] 169994092
[savefile] "/home/andrey/git/x393/x393_testbench04.sav"
[timestart] 40584000
[size] 1823 1180
[pos] 1919 0
*-17.720415 40842388 255683333 256143333 274856667 275790000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 209230300
[size] 1920 1180
[pos] -1920 0
*-15.456448 209370000 209370000 209396667 209423333 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.read_compressor_frame_irq.
[treeopen] x393_testbench03.read_contol_register_irq.
......@@ -49,8 +49,8 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.
[sst_width] 412
[signals_width] 429
[sst_width] 295
[signals_width] 339
[sst_expanded] 1
[sst_vpaned_height] 578
@820
......@@ -321,7 +321,7 @@ x393_testbench03.sim_soc_interrupts_i.inta[8:0]
-
@1000200
-sim_soc_interrupts
@c00200
@800200
-interrupts
@28
x393_testbench03.MAIN_GO
......@@ -647,6 +647,15 @@ x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_s
@800200
-cmprs_afi_mux_ptr
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.sa_len_ra[2:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunks_to_rollover[26:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunks_to_rollover_r[3:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunks_to_rollover_m1[3:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.max_wlen_same[2:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.max_wlen_r[2:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.max_wlen[2:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.last_max_written[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.pre_winner_channel[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.winner_channel[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunk_ptr_ra[2:0]
@28
......@@ -681,14 +690,21 @@ x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_p
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunk_inc[2:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunk_inc_want_m1[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunks_to_rollover[26:0]
@23
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.pre_chunks_to_rollover_m1[3:0]
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunks_to_rollover_m1[3:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunks_to_rollover_r[3:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.rollover_w
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.rollover_r
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.max_inc_ram_we
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.max_inc_ram_wa[1:0]
@800200
-cmprs_afi_mux
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.winner1[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.winner2[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.max_wlen[2:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.want_wleft32[1:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.wleft[3:0]
......@@ -915,7 +931,7 @@ x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.cmd_we
@22
x393_testbench03.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.wpage_asap[3:0]
x393_testbench03.x393_i.frame_num[15:0]
@1401200
@1000200
-interrupts
@c00022
x393_testbench03.x393_i.cmd_seq_mux_i.status_generate_cmd_seq_mux_i.status[25:0]
......@@ -1307,7 +1323,7 @@ x393_testbench03.x393_i.membridge_i.read_busy
@1401200
-read_to_sys
-membridge
@c00200
@800200
-simul_axi_hp_wr0
@22
x393_testbench03.simul_axi_hp_wr_i.write_address[31:0]
......@@ -1329,9 +1345,9 @@ x393_testbench03.simul_axi_hp_wr_i.start_write_burst_w
x393_testbench03.simul_axi_hp_wr_i.num_full_data[7:0]
@200
-
@1401200
@1000200
-simul_axi_hp_wr0
@800200
@c00200
-frame_numbers
@28
x393_testbench03.x393_i.mclk
......@@ -1361,12 +1377,12 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.se
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_sync
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wen
@800029
@c00028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wen_r[1:0]
@29
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wen_r[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wen_r[1:0]
@1001201
@1401200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.pre_wpage0_inc
......@@ -1394,6 +1410,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-
@1000200
-i2c
@1401200
-frame_numbers
[pattern_trace] 1
[pattern_trace] 0
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