Commit 64e5e516 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

added bitsteam selection to Python programs

parent 510a3dc6

py393/x393_jpeg.py

+2 −0
Original line number Diff line number Diff line
@@ -998,6 +998,7 @@ setup_all_sensors True None 0x4 


################## Parallel ##################

cd /usr/local/verilog/; test_mcntrl.py @hargs

bitstream_set_path /usr/local/verilog/x393_parallel.bit

#fpga_shutdown

setupSensorsPower "PAR12"

measure_all "*DI"
@@ -1060,6 +1061,7 @@ jpeg_write "img.jpeg" 0 85 


################## Serial ####################

cd /usr/local/verilog/; test_mcntrl.py @hargs

bitstream_set_path /usr/local/verilog/x393_hispi.bit

setupSensorsPower "HISPI"

measure_all "*DI"

setup_all_sensors True None 0xf

py393/x393_utils.py

+7 −0
Original line number Diff line number Diff line
@@ -109,6 +109,13 @@ class X393Utils(object): 
            print ("fpga_shutdown(): Applying PROG_B")

        self.x393_mem.write_mem(FPGA_DEVCFG_CTRL,old_devcfg_ctrl & ~(1 << 30))

                    

    def bitstream_get_path(self):

        return DEFAULT_BITFILE

    

    def bitstream_set_path(self, bitfile):

        global DEFAULT_BITFILE

        DEFAULT_BITFILE = bitfile

                    

    def bitstream(self,

                  bitfile=None,

                  quiet=1):