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Commit c57b67b8 authored by Andrey Filippov's avatar Andrey Filippov
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debugging hardware

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.project
View file @ c57b67b8
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>ise_logs/ISExst.log</name> <name>ise_logs/ISExst.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140531140025056.log</location> <location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140607155721361.log</location>
</link> </link>
<link> <link>
<name>ise_state/eddr3-synth.tgz</name> <name>ise_state/eddr3-synth.tgz</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140531140025056.tgz</location> <location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140607155721361.tgz</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140606182054344.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607160650782.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140606182315739.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607160728042.log</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-opt-phys.dcp</name> <name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140606182315739.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607160728042.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-place.dcp</name> <name>vivado_state/eddr3-place.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140606182315739.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607160728042.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-route.dcp</name> <name>vivado_state/eddr3-route.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140606182315739.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607160728042.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-synth.dcp</name> <name>vivado_state/eddr3-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140606171026321.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607005118430.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ddrc_test01.v
View file @ c57b67b8
...@@ -91,7 +91,7 @@ module ddrc_test01 #( ...@@ -91,7 +91,7 @@ module ddrc_test01 #(
parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
parameter DCI_RST_REL = 'h02a, // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry parameter DCI_RST_REL = 'h02a, // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry
parameter DCI_RST_REL_MASK = 'h3fe, // address mask for DCI calibrate circuitry parameter DCI_RST_REL_MASK = 'h3fe, // address mask for DCI calibrate circuitry
parameter DLY_RST_REL = 'h02a, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry parameter DLY_RST_REL = 'h02c, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry
parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry
parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div) parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div)
parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters
...@@ -134,10 +134,10 @@ module ddrc_test01 #( ...@@ -134,10 +134,10 @@ module ddrc_test01 #(
// AXI write interface signals // AXI write interface signals
(* keep = "true" *) //(* keep = "true" *)
wire axi_aclk; // clock - should be buffered wire axi_aclk; // clock - should be buffered
// wire axi_aresetn; // reset, active low // wire axi_aresetn; // reset, active low
(* dont_touch = "true" *) //(* dont_touch = "true" *)
wire axi_rst; // reset, active high wire axi_rst; // reset, active high
// AXI Write Address // AXI Write Address
wire [31:0] axi_awaddr; // AWADDR[31:0], input wire [31:0] axi_awaddr; // AWADDR[31:0], input
...@@ -290,16 +290,7 @@ module ddrc_test01 #( ...@@ -290,16 +290,7 @@ module ddrc_test01 #(
wire refresh_set; wire refresh_set;
assign port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0); assign port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
// assign en_cmd0_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h1);
// assign en_port0_rd= axird_bram_ren && (axird_bram_raddr[11:10]==2'h0);
// assign en_port0_regen= axird_bram_regen && (axird_bram_raddr[11:10]==2'h0);
// assign en_port1_wr= axiwr_bram_wen && (axiwr_bram_waddr[11:10]==2'h0);
assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0); assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0);
// assign en_port0_rd= axird_bram_ren && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
// assign en_port0_regen= axird_bram_regen && (((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
assign en_port0_rd= axird_bram_ren && port0_rd_match; assign en_port0_rd= axird_bram_ren && port0_rd_match;
assign en_port0_regen= axird_bram_regen && port0_rd_match_r; assign en_port0_regen= axird_bram_regen && port0_rd_match_r;
...@@ -311,6 +302,19 @@ module ddrc_test01 #( ...@@ -311,6 +302,19 @@ module ddrc_test01 #(
assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
assign locked=locked_mmcm && locked_pll; assign locked=locked_mmcm && locked_pll;
// Clock and reset from PS
wire comb_rst=~frst[0] | frst[1];
reg axi_rst_pre=1'b1;
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
end
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
always @ (posedge axi_aclk) begin always @ (posedge axi_aclk) begin
port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
end end
...@@ -323,33 +327,8 @@ always @ (posedge axi_rst or posedge axi_aclk) begin ...@@ -323,33 +327,8 @@ always @ (posedge axi_rst or posedge axi_aclk) begin
end end
// Clock and reset from PS
reg frst_inv;
always @ (negedge frst[0] or posedge axi_aclk) begin
if (!frst[0]) frst_inv <= 1'b1;
else frst_inv <= 1'b0;
end
/* Instance template for module PULLDOWN */
PULLDOWN PULLDOWN_i (
.O(MEMCLK) // output
);
wire dbg_clk; // = fclk[1] ^ MEMCLK;
//BUFG dbg_clk_ii (.O(dbg_clk),.I(fclk[1] ^ MEMCLK));
BUFG dbg_clk_ii (.O(dbg_clk),.I(MEMCLK));
//(* dont_touch = "true" *)
reg [7:0] dbg_toggle;
//always @ (posedge axi_rst or posedge axi_aclk) begin
wire dbg_rst=frst[1] && !frst[0];
always @ (posedge dbg_rst or posedge dbg_clk) begin
//always @ (posedge axi_rst or posedge dbg_clk) begin
//always @ (posedge fclk[1]) begin
if (dbg_rst) dbg_toggle <= 8'ha5;
else dbg_toggle <= dbg_toggle+1; //dbg_toggle+1;
end
/* /*
dly_addr[1], dly_addr[1],
dly_addr[0], dly_addr[0],
clkin_stopped_mmcm, clkin_stopped_mmcm,
clkfb_stopped_mmcm, clkfb_stopped_mmcm,
...@@ -357,104 +336,63 @@ end ...@@ -357,104 +336,63 @@ end
rst_in, rst_in,
dci_rst, dci_rst,
dly_rst dly_rst
*/ */
//MEMCLK //MEMCLK
wire [63:0] gpio_in; wire [63:0] gpio_in;
assign gpio_in={ assign gpio_in={
16'b0, 16'b0,
1'b1, // 1 1'b1, // 1
MEMCLK, // 1/0? - external clock MEMCLK, // 1/0? - external clock
dbg_rst, // 1 1'b0, //
fclk[1] ^ MEMCLK, //dbg_clk, // 0/1 1'b0, //
frst[1], // 1 (follows) frst[1], // 0 (follows)
fclk[1:0], // 2'bXX (toggle) fclk[1:0], // 2'bXX (toggle)
axird_dev_busy, // 0 axird_dev_busy, // 0
{frst[2]?8'h5a:{ 4'b0, // 4'b0
dbg_toggle[7:4], // 4'b1111 -> 4'ha
dbg_toggle[3:0]}}, // 4'b1111 -> 4'ha 4'b0, // 4'b0
tmp_debug[7:4], // 4'b0111 -> 4'bx00x tmp_debug[7:4], // 4'b0111 -> 4'bx00x
// dly_addr[1], // dly_addr[1], 0
// dly_addr[0], // dly_addr[0], 0
// clkin_stopped_mmcm, // clkin_stopped_mmcm, 0
// clkfb_stopped_mmcm, // clkfb_stopped_mmcm, 0
tmp_debug[3:0], // 4'b1100 -> 4'bxx00 tmp_debug[3:0], // 4'b1100 -> 4'bxx00
// ddr_rst, // ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
// rst_in, // rst_in, 0 0
// dci_rst, // dci_rst, 0 1
// dly_rst // dly_rst 0 1
phy_locked_mmcm, // 0 1 phy_locked_mmcm, // 1 1
phy_locked_pll, // 0 1 phy_locked_pll, // 1 1
phy_dly_ready, // 0 1 phy_dly_ready, // 1 0
phy_dci_ready, // 1 1 phy_dci_ready, // 1 0
locked_mmcm, // 0 1 locked_mmcm, // 1 1
locked_pll, // 0 1 locked_pll, // 1 1
dly_ready, // 0 1 dly_ready, // 1 0
dci_ready, // 0 1 dci_ready, // 1 0
ps_out[7:4], // 4'b0 input[7:0] 4'b0 ps_out[7:4], // 4'b0 input[7:0] 4'b0
ps_out[3:0], // 4'b0 input[7:0] 4'b0 ps_out[3:0], // 4'b0 input[7:0] 4'b0
run_busy, // input // 0 run_busy, // input // 0
locked, // input // 0 locked, // input // 1
ps_rdy, // input // 0 ps_rdy, // input // 1
axi_arready, // 1 axi_arready, // 1
axi_awready, // 1 axi_awready, // 1
axi_wready, // 1 axi_wready, // 1
axi_aclk, // 0/1 fclk[0], // 0/1
axi_rst // 0 axi_rst_pre //axi_rst // 0
}; };
/*
assign tmp_debug ={
1'b1,
clkin_stopped_mmcm,
clkfb_stopped_mmcm,
clk_in, // dbg_reg3,
dbg_reg2,
dbg_reg1,
rst_in,
dly_rst
};
*/ assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0];
//assign DUMMY_TO_KEEP = ^gpio_in[63:0]; // to keep PS7 signals from "optimization"
assign DUMMY_TO_KEEP = dbg_toggle[0];
/*
.rdata (status_rdata[31:0]), // output[31:0]
.busy (axird_dev_busy), // output
// .run_done (run_done), // input
.run_busy (run_busy), // input
.locked (locked), // input
.ps_rdy (ps_rdy), // input
.ps_out (ps_out[7:0]) // input[7:0]
*/
/*
`ifndef IVERILOG
(* dont_touch = "true" *)
`endif
wire frst_inv= ~frst[0];
*/
//BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0]));
//assign axi_rst=~frst[0];
assign axi_rst=~frst[0] || frst[1]; // prevent releasing reset before explicit command
//BUFG bufg_axi_rst_i (.O(axi_rst),.I(frst_inv));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
axibram_write #( axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS) .ADDRESS_BITS(AXI_WR_ADDR_BITS)
...@@ -633,12 +571,10 @@ run_busy ...@@ -633,12 +571,10 @@ run_busy
.need (refresh_need), // output .need (refresh_need), // output
.grant (refresh_grant) // input .grant (refresh_grant) // input
); );
always @(posedge axi_rst or posedge mclk) begin
always @ (posedge axi_rst or posedge mclk) begin
if (axi_rst) refresh_grant <= 0; if (axi_rst) refresh_grant <= 0;
refresh_grant <= !refresh_grant && refresh_en && !run_busy && !axi_run_seq && (refresh_need || (refresh_want && !run_seq_rq_gen)); else refresh_grant <= !refresh_grant && refresh_en && !run_busy && !axi_run_seq && (refresh_need || (refresh_want && !run_seq_rq_gen));
end end
ddrc_status ddrc_status
// #( // #(
......
ddrc_test01_testbench.sav
View file @ c57b67b8
This diff is collapsed.
phy/cmd_addr.v
View file @ c57b67b8
...@@ -19,7 +19,10 @@ ...@@ -19,7 +19,10 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
/*
Currently ddr3_a, ddr3_ba, ddr_cke and ddr_odt do not change inside a 2-clock command cycle, so half register
bits are removed during optimization
*/
module cmd_addr #( module cmd_addr #(
parameter IODELAY_GRP = "IODELAY_MEMORY", parameter IODELAY_GRP = "IODELAY_MEMORY",
parameter IOSTANDARD = "SSTL15", parameter IOSTANDARD = "SSTL15",
...@@ -62,7 +65,8 @@ reg in_tri_r=1'b1; // or tri-state on reset? ...@@ -62,7 +65,8 @@ reg in_tri_r=1'b1; // or tri-state on reset?
(* keep = "true" *) reg set_r=0; (* keep = "true" *) reg set_r=0;
reg [7:0] ld_dly_cmd=8'b0; reg [7:0] ld_dly_cmd=8'b0;
reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0; reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0;
wire [ADDRESS_NUMBER-1:0] decode_addr; //wire [ADDRESS_NUMBER-1:0] decode_addr;
wire [23:0] decode_addr24;
wire [7:0] decode_sel={ wire [7:0] decode_sel={
(dly_addr[2:0]==7)?1'b1:1'b0, (dly_addr[2:0]==7)?1'b1:1'b0,
(dly_addr[2:0]==6)?1'b1:1'b0, (dly_addr[2:0]==6)?1'b1:1'b0,
...@@ -72,7 +76,10 @@ wire [7:0] decode_sel={ ...@@ -72,7 +76,10 @@ wire [7:0] decode_sel={
(dly_addr[2:0]==2)?1'b1:1'b0, (dly_addr[2:0]==2)?1'b1:1'b0,
(dly_addr[2:0]==1)?1'b1:1'b0, (dly_addr[2:0]==1)?1'b1:1'b0,
(dly_addr[2:0]==0)?1'b1:1'b0}; (dly_addr[2:0]==0)?1'b1:1'b0};
assign decode_addr24={
(dly_addr[4:3] == 2'h2)?decode_sel[7:0]:8'h0,
(dly_addr[4:3] == 2'h1)?decode_sel[7:0]:8'h0,
(dly_addr[4:3] == 2'h0)?decode_sel[7:0]:8'h0};
always @ (posedge clk_div or posedge rst) begin always @ (posedge clk_div or posedge rst) begin
if (rst) begin if (rst) begin
in_a_r <= 0; in_ba_r <= 6'b0; in_a_r <= 0; in_ba_r <= 6'b0;
...@@ -89,7 +96,8 @@ always @ (posedge clk_div or posedge rst) begin ...@@ -89,7 +96,8 @@ always @ (posedge clk_div or posedge rst) begin
dly_data_r<=dly_data; dly_data_r<=dly_data;
set_r<=set; set_r<=set;
ld_dly_cmd <= {8 { dly_addr[4] & dly_addr[3] & ld_delay}} & decode_sel[7:0]; ld_dly_cmd <= {8 { dly_addr[4] & dly_addr[3] & ld_delay}} & decode_sel[7:0];
ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr; // ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr;
ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr24[ADDRESS_NUMBER-1:0];
end end
end end
...@@ -97,7 +105,7 @@ end ...@@ -97,7 +105,7 @@ end
generate generate
genvar i; genvar i;
for (i=0; i<ADDRESS_NUMBER; i=i+1) begin: addr_block for (i=0; i<ADDRESS_NUMBER; i=i+1) begin: addr_block
assign decode_addr[i]=(ld_dly_addr[4:0] == i)?1'b1:1'b0; // assign decode_addr[i]=(ld_dly_addr[4:0] == i)?1'b1:1'b0;
cmda_single #( cmda_single #(
.IODELAY_GRP(IODELAY_GRP), .IODELAY_GRP(IODELAY_GRP),
.IOSTANDARD(IOSTANDARD), .IOSTANDARD(IOSTANDARD),
......
phy/ddrc_sequencer.v
View file @ c57b67b8
...@@ -364,7 +364,7 @@ module ddrc_sequencer #( ...@@ -364,7 +364,7 @@ module ddrc_sequencer #(
.CMD_DONE_BIT (CMD_DONE_BIT) // bit number (address) to signal sequence done .CMD_DONE_BIT (CMD_DONE_BIT) // bit number (address) to signal sequence done
) phy_cmd_i ( ) phy_cmd_i (
.SDRST (SDRST), // output **************** .SDRST (SDRST), // output
.SDCLK (SDCLK), // output .SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output .SDNCLK (SDNCLK), // output
.SDA (SDA[ADDRESS_NUMBER-1:0]), // output[14:0] .SDA (SDA[ADDRESS_NUMBER-1:0]), // output[14:0]
...@@ -403,15 +403,12 @@ module ddrc_sequencer #( ...@@ -403,15 +403,12 @@ module ddrc_sequencer #(
.ps_rdy (ps_rdy), // output .ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]), // output[7:0] .ps_out (ps_out[7:0]), // output[7:0]
/// debugging
// .phy_cmd_word (32'h0), //phy_cmd_word[31:0]), // input[31:0]
.phy_cmd_word (phy_cmd_word[31:0]), // input[31:0] .phy_cmd_word (phy_cmd_word[31:0]), // input[31:0]
.phy_cmd_nop (phy_cmd_nop), // output .phy_cmd_nop (phy_cmd_nop), // output
.phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts) .phy_cmd_add_pause (phy_cmd_add_pause), // one pause cycle (for 8-bursts)
.add_pause (add_pause), .add_pause (add_pause),
.pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0] .pause_len (pause_len), // output [CMD_PAUSE_BITS-1:0]
.sequence_done (sequence_done), // output .sequence_done (sequence_done), // output
// .buf_addr (buf_addr[6:0]), // output[6:0]
.buf_wdata (buf_wdata[63:0]), // output[63:0] .buf_wdata (buf_wdata[63:0]), // output[63:0]
.buf_rdata (buf_rdata[63:0]), // input[63:0] .buf_rdata (buf_rdata[63:0]), // input[63:0]
.buf_wr (buf_wr_ndly), // output .buf_wr (buf_wr_ndly), // output
......
phy/dm_single.v
View file @ c57b67b8
...@@ -19,7 +19,8 @@ ...@@ -19,7 +19,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
//`define use_iobuf 1 // ISE 14.7 does not have OBUFT_DCIEN
`define USE_IOBUF 1
module dm_single #( module dm_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY", parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN
...@@ -69,7 +70,7 @@ odelay_fine_pipe # ( ...@@ -69,7 +70,7 @@ odelay_fine_pipe # (
.data_in(d_ser), .data_in(d_ser),
.data_out(dq_data_dly) .data_out(dq_data_dly)
); );
`ifdef use_iobuf `ifdef USE_IOBUF
IOBUF_DCIEN #( IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), // .IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD), .IOSTANDARD(IOSTANDARD),
......
phy/dq_single.v
View file @ c57b67b8
...@@ -49,7 +49,7 @@ wire dq_tri; ...@@ -49,7 +49,7 @@ wire dq_tri;
wire dq_data_dly; wire dq_data_dly;
wire dq_dly; wire dq_dly;
// keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same // keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
(* keep = "true" *) //(* keep = "true" *)
wire dq_di; wire dq_di;
......
phy/phy_cmd.v
View file @ c57b67b8
...@@ -220,16 +220,16 @@ module phy_cmd#( ...@@ -220,16 +220,16 @@ module phy_cmd#(
} = phy_cmd_word; } = phy_cmd_word;
assign { assign {
phy_rcw_cur[2:0], phy_rcw_cur[2:0], // all set to 0
phy_odt_cur, phy_odt_cur, // 8 ODT
phy_cke_dis_cur, // disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) phy_cke_dis_cur, // 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
phy_sel_cur, // fitst/second half-cycle, oter will be nop (cke+odt applicable to both) phy_sel_cur, // 6 first/second half-cycle, other will be nop (cke+odt applicable to both) - NOT USED?
phy_dq_en_cur, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) phy_dq_en_cur, // 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_cur, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) phy_dqs_en_cur, // 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_cur,//enable toggle DQS according to the pattern phy_dqs_toggle_cur,// 3 enable toggle DQS according to the pattern
phy_dci_en_cur, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) phy_dci_en_cur, // 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr_cur, // connect to external buffer (but only if not paused) phy_buf_wr_cur, // 1 connect to external buffer (but only if not paused)
phy_buf_rd_cur // connect to external buffer (but only if not paused) phy_buf_rd_cur // 0 connect to external buffer (but only if not paused)
} = add_pause ? {3'b0, extra_prev} : // 3'b0 for rcw (nop) } = add_pause ? {3'b0, extra_prev} : // 3'b0 for rcw (nop)
{ {
phy_rcw_pos[2:0], // {ras,cas,we} phy_rcw_pos[2:0], // {ras,cas,we}
...@@ -302,15 +302,15 @@ module phy_cmd#( ...@@ -302,15 +302,15 @@ module phy_cmd#(
phy_addr_prev <= phy_addr_in; phy_addr_prev <= phy_addr_in;
phy_bank_prev <= phy_bank_in; phy_bank_prev <= phy_bank_in;
extra_prev <= { extra_prev <= {
phy_odt_in, // may be optimized? phy_odt_in, // 8 may be optimized?
phy_cke_dis, // disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed) phy_cke_dis, // 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
phy_sel_in, // fitst/second half-cycle, oter will be nop (cke+odt applicable to both) phy_sel_in, // 6 first/second half-cycle, other will be nop (cke+odt applicable to both)
phy_dq_en_in, //phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0) phy_dq_en_in, // 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_in, //phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0) phy_dqs_en_in, // 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_en,//enable toggle DQS according to the pattern phy_dqs_toggle_en,// 3 enable toggle DQS according to the pattern
phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) phy_dci_en_in, // 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr, // connect to external buffer (but only if not paused) phy_buf_wr, // 1 connect to external buffer (but only if not paused)
phy_buf_rd // connect to external buffer (but only if not paused) phy_buf_rd // 0 connect to external buffer (but only if not paused)
}; };
end end
......
phy/phy_top.v
View file @ c57b67b8
...@@ -116,16 +116,10 @@ module phy_top #( ...@@ -116,16 +116,10 @@ module phy_top #(
output [PHASE_WIDTH-1:0] ps_out output [PHASE_WIDTH-1:0] ps_out
); );
reg rst= 1'b1; reg rst= 1'b1;
// reg rst_dbg=1'b1;
// always @(posedge clk_div or posedge rst_in) begin // got min hold violation
always @(negedge clk_div or posedge rst_in) begin always @(negedge clk_div or posedge rst_in) begin
if (rst_in) rst <= 1'b1; if (rst_in) rst <= 1'b1;
else rst <= 1'b0; else rst <= 1'b0;
end end
// always @(posedge clk_div or posedge rst_in) begin
// if (rst_in) rst_dbg <= 1'b1;
// else rst_dbg <= 1'b0;
// end
wire ld_data_l = (dly_addr[6:5] == 2'h0) && ld_delay ; wire ld_data_l = (dly_addr[6:5] == 2'h0) && ld_delay ;
wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ; wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ; wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
...@@ -136,15 +130,24 @@ module phy_top #( ...@@ -136,15 +130,24 @@ module phy_top #(
// assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated // assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
wire clkin_stopped_mmcm; wire clkin_stopped_mmcm;
wire clkfb_stopped_mmcm; wire clkfb_stopped_mmcm;
reg dbg1=0;
reg dbg2=0;
always @ (posedge rst_in or posedge mclk) begin
if (rst_in) dbg1 <= 0;
else dbg1 <= ~dbg1;
end
always @ (posedge rst_in or posedge clk_div) begin
if (rst_in) dbg2 <= 0;
else dbg2 <= ~dbg2;
end
/*
reg dbg_reg1=1;
reg dbg_reg2=1;
reg dbg_reg3=1;
*/
assign tmp_debug ={ assign tmp_debug ={
dly_addr[1], dbg2, //dly_addr[1],
dly_addr[0], dbg1, //dly_addr[0],
clkin_stopped_mmcm, clkin_stopped_mmcm,
clkfb_stopped_mmcm, clkfb_stopped_mmcm,
ddr_rst, ddr_rst,
...@@ -152,17 +155,7 @@ module phy_top #( ...@@ -152,17 +155,7 @@ module phy_top #(
dci_rst, dci_rst,
dly_rst dly_rst
}; };
/*
always @ (posedge clk_in) begin
dbg_reg1 <= ~dbg_reg1;
end
always @ (posedge clk_ref) begin
dbg_reg2 <= ~dbg_reg2;
end
always @ (posedge clk_div) begin
dbg_reg3 <= ~dbg_reg3;
end
*/
/* memory reset */ /* memory reset */
obuf #( obuf #(
.CAPACITANCE("DONT_CARE"), .CAPACITANCE("DONT_CARE"),
...@@ -174,7 +167,6 @@ module phy_top #( ...@@ -174,7 +167,6 @@ module phy_top #(
.I(~ddr_rst) // input .I(~ddr_rst) // input
); );
cmd_addr #( cmd_addr #(
.IODELAY_GRP(IODELAY_GRP), .IODELAY_GRP(IODELAY_GRP),
.IOSTANDARD(IOSTANDARD_CMDA), .IOSTANDARD(IOSTANDARD_CMDA),
......
util_modules/fifo_same_clock.v
View file @ c57b67b8
...@@ -37,6 +37,10 @@ module fifo_same_clock ...@@ -37,6 +37,10 @@ module fifo_same_clock
output reg half_full // FIFO half full output reg half_full // FIFO half full
); );
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1; localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why?
reg [DATA_DEPTH :0] fill=0; reg [DATA_DEPTH :0] fill=0;
reg just_one,two_or_less; reg just_one,two_or_less;
reg [DATA_WIDTH-1:0] inreg; reg [DATA_WIDTH-1:0] inreg;
...@@ -56,16 +60,18 @@ module fifo_same_clock ...@@ -56,16 +60,18 @@ module fifo_same_clock
assign outreg_use_inreg=(out_full && two_or_less) || just_one; assign outreg_use_inreg=(out_full && two_or_less) || just_one;
// assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000)); // assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000));
// TODO: verify rem is not needed instead of re // TODO: verify rem is not needed instead of re
assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000)); //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target. assign next_fill = fill[DATA_DEPTH:0]+((we && ~re)?1:((~we && re)?-1:0)); //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
always @ (posedge clk or posedge rst) begin always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0; if (rst) fill <= 0;
else if (we && ~re) fill <= fill+1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target. else fill <= next_fill;
else if (~we && re) fill <= fill-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target. // else if (we && ~re) fill <= fill+1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
// else if (~we && re) fill <= fill-1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
if (rst) wa <= 0; if (rst) wa <= 0;
else if (wem) wa <= wa+1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target. else if (wem) wa <= wa+1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) ra <= 1; // 0; if (rst) ra <= 1; // 0;
else if (re) ra <= ra+1; //now ra is 1 ahead //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target. else if (re) ra <= ra+1; //now ra is 1 ahead //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target. else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
......
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