Commit c4c0d10a authored by Andrey Filippov's avatar Andrey Filippov

working on address export for C, fixed some copied typos in multiple files

parent e16fd10f
...@@ -62,52 +62,52 @@ ...@@ -62,52 +62,52 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160316133233827.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160319192210839.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
...@@ -127,7 +127,7 @@ ...@@ -127,7 +127,7 @@
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160316133233827.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160319192210839.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
...@@ -31,9 +31,16 @@ ...@@ -31,9 +31,16 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
// parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support // parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing // parameter FPGA_VERSION = 32'h03930079; // diff - failed
// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
// parameter FPGA_VERSION = 32'h03930077; // Restoring IOSTANDARDs - OK
// parameter FPGA_VERSION = 32'h03930076; // Trying PPDS_25 with 1.8 actual power - Stuck when applying 1.8 or 2.5V
// parameter FPGA_VERSION = 32'h03930075; // Trying IN_TERM = "UNTUNED_50"
// parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller 16365 ( 83.28%)
// parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
// parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%) // parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%) // parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %) // parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
......
...@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused ...@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number 0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately) wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
...@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused ...@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number 1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately) wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue // task wait_read_queue_empty; - alternative way to check fo empty read queue
...@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused ...@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number 2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately) wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end end
...@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused ...@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number 0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging: // tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately) // wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end end
...@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused ...@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number 3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number 2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first) schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number 1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write 0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished `PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately) wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end end
......
This diff is collapsed.
...@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to ...@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to
input [1:0] page; // buffer page number input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO) input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
begin begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full // wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr}); write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
......
...@@ -72,6 +72,7 @@ import x393_sensor ...@@ -72,6 +72,7 @@ import x393_sensor
import x393_rtc import x393_rtc
import x393_jpeg import x393_jpeg
import vrlg import vrlg
import x393_export_c
__all__ = [] __all__ = []
__version__ = 0.1 __version__ = 0.1
__date__ = '2015-03-01' __date__ = '2015-03-01'
...@@ -357,6 +358,7 @@ USAGE ...@@ -357,6 +358,7 @@ USAGE
x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams) x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams)
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams) x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams) x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams)
x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams)
''' '''
print ("----------------------") print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__)) print("x393_mem.__dict__="+str(x393_mem.__dict__))
...@@ -390,6 +392,7 @@ USAGE ...@@ -390,6 +392,7 @@ USAGE
extractTasks(x393_sensor.X393Sensor, x393Sensor) extractTasks(x393_sensor.X393Sensor, x393Sensor)
extractTasks(x393_rtc.X393Rtc, x393Rtc) extractTasks(x393_rtc.X393Rtc, x393Rtc)
extractTasks(x393_jpeg.X393Jpeg, x393Jpeg) extractTasks(x393_jpeg.X393Jpeg, x393Jpeg)
extractTasks(x393_export_c.X393ExportC, x393ExportC)
for cmdLine in commands: for cmdLine in commands:
print ('Running task: '+str(cmdLine)) print ('Running task: '+str(cmdLine))
......
...@@ -711,6 +711,7 @@ MCONTR_LINTILE_REPEAT = int ...@@ -711,6 +711,7 @@ MCONTR_LINTILE_REPEAT = int
CHNBUF_READ_LATENCY = int CHNBUF_READ_LATENCY = int
SENS_CTRL_QUADRANTS_WIDTH = int SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str STATUS_PSHIFTER_RDY_MASK__RAW = str
WBUF_DLY_DFLT__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str SENS_GAMMA_MODE_BAYER__TYPE = str
TILE_WIDTH__TYPE = str TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str MCNTRL_TILED_FRAME_LAST__RAW = str
...@@ -917,7 +918,7 @@ T_RFC__RAW = str ...@@ -917,7 +918,7 @@ T_RFC__RAW = str
WBUF_DLY_DFLT__TYPE = str WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str PXD_SLEW__TYPE = str
SENSI2C_REL_RADDR__RAW = str FRAME_START_ADDRESS = int
DEBUG_SET_STATUS__RAW = str DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int LOGGER_CONF_EN = int
...@@ -1151,7 +1152,7 @@ MULT_SAXI_BSLOG0__RAW = str ...@@ -1151,7 +1152,7 @@ MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str CLKFBOUT_USE_FINE_PS__RAW = str
CMPRS_FRMT_LMARG__RAW = str CMPRS_FRMT_LMARG__RAW = str
SENSOR_CHN_EN_BIT__TYPE = str CMDFRAMESEQ_IRQ_BIT__RAW = str
LOGGER_BIT_DURATION = int LOGGER_BIT_DURATION = int
CAMSYNC_MODE__TYPE = str CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str CHNBUF_READ_LATENCY__RAW = str
...@@ -1165,6 +1166,7 @@ LOGGER_CONF_EN_BITS = int ...@@ -1165,6 +1166,7 @@ LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int CAMSYNC_POST_MAGIC = int
CMDFRAMESEQ_IRQ_BIT__TYPE = str
PXD_IBUF_LOW_PWR__RAW = str PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str MULT_SAXI_BSLOG2__RAW = str
...@@ -1186,6 +1188,7 @@ CMPRS_CBIT_CMODE_JP4DC__RAW = str ...@@ -1186,6 +1188,7 @@ CMPRS_CBIT_CMODE_JP4DC__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
MCONTR_TOP_0BIT_ADDR_MASK = int MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str HISPI_IBUF_DELAY_VALUE__TYPE = str
CMDFRAMESEQ_REL = int CMDFRAMESEQ_REL = int
...@@ -1265,7 +1268,7 @@ SENSIO_ADDR_MASK = int ...@@ -1265,7 +1268,7 @@ SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int SCANLINE_STARTY = int
SCANLINE_STARTX = int SCANLINE_STARTX = int
FFCLK0_DIFF_TERM__TYPE = str FFCLK0_DIFF_TERM__TYPE = str
WBUF_DLY_DFLT__RAW = str HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str LD_DLY_CMDA__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN = int MCONTR_TOP_0BIT_REFRESH_EN = int
CMPRS_CBIT_RUN_RST = int CMPRS_CBIT_RUN_RST = int
...@@ -1293,7 +1296,7 @@ DEBUG_SET_STATUS = int ...@@ -1293,7 +1296,7 @@ DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int STATUS_ADDR = int
WINDOW_X0__RAW = str WINDOW_X0__RAW = str
FRAME_START_ADDRESS = int CMDFRAMESEQ_IRQ_BIT = int
CONTROL_ADDR__TYPE = str CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int CLKFBOUT_MULT_PCLK = int
CMPRS_GROUP_ADDR = int CMPRS_GROUP_ADDR = int
...@@ -1833,6 +1836,7 @@ SENSIO_RADDR__RAW = str ...@@ -1833,6 +1836,7 @@ SENSIO_RADDR__RAW = str
DFLT_CHN_EN__TYPE = str DFLT_CHN_EN__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str MCONTR_PHY_0BIT_ADDR__RAW = str
MCLK_PHASE = float MCLK_PHASE = float
CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int CMDSEQMUX_MASK = int
...@@ -1874,6 +1878,7 @@ MCONTR_BUF3_RD_ADDR__RAW = str ...@@ -1874,6 +1878,7 @@ MCONTR_BUF3_RD_ADDR__RAW = str
CLKIN_PERIOD = int CLKIN_PERIOD = int
RSEL__TYPE = str RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str CMDFRAMESEQ_ADDR_INC__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
LOGGER_CONF_GPS_BITS = int LOGGER_CONF_GPS_BITS = int
HISPI_FIFO_DEPTH = int HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float CLKFBOUT_PHASE = float
...@@ -2075,6 +2080,7 @@ RTC_SET_STATUS__RAW = str ...@@ -2075,6 +2080,7 @@ RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str LD_DLY_PHASE__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_INTERRUPTS__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int DFLT_WBUF_DELAY = int
...@@ -2130,6 +2136,7 @@ AXI_WR_ADDR_BITS = int ...@@ -2130,6 +2136,7 @@ AXI_WR_ADDR_BITS = int
FFCLK1_IBUF_LOW_PWR__RAW = str FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
STATUS_SEQ_SHFT__TYPE = str STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int MCONTR_CMPRS_BASE = int
...@@ -2154,6 +2161,7 @@ MULT_SAXI_ADDR = int ...@@ -2154,6 +2161,7 @@ MULT_SAXI_ADDR = int
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
SENSOR_BASE_INC = int SENSOR_BASE_INC = int
MULT_SAXI_CNTRL_MASK__RAW = str MULT_SAXI_CNTRL_MASK__RAW = str
SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str SENSI2C_REL_RADDR__TYPE = str
...@@ -2183,6 +2191,7 @@ DEBUG_SHIFT_DATA__RAW = str ...@@ -2183,6 +2191,7 @@ DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int SENS_NUM_SUBCHN = int
MCONTR_BUF0_WR_ADDR__TYPE = str MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str CMPRS_COLOR18__RAW = str
LOGGER_STATUS = int LOGGER_STATUS = int
CMDFRAMESEQ_RUN_BIT__RAW = str CMDFRAMESEQ_RUN_BIT__RAW = str
...@@ -966,6 +966,7 @@ ff d9 ...@@ -966,6 +966,7 @@ ff d9
""" """
""" """
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "HISPI"
measure_all "*DI" measure_all "*DI"
setup_all_sensors True None 0xf setup_all_sensors True None 0xf
#write_sensor_i2c 0 1 0 0x30700101 #write_sensor_i2c 0 1 0 0x30700101
......
...@@ -68,9 +68,9 @@ class X393PIOSequences(object): ...@@ -68,9 +68,9 @@ class X393PIOSequences(object):
def schedule_ps_pio(self, #; // schedule software-control memory operation (may need to check FIFO status first) def schedule_ps_pio(self, #; // schedule software-control memory operation (may need to check FIFO status first)
seq_addr, # input [9:0] seq_addr; // sequence start address seq_addr, # input [9:0] seq_addr; // sequence start address
page, # input [1:0] page; // buffer page number page, # input [1:0] page; // buffer page number
urgent, # input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO) urgent, # input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
chn, # input chn; // channel buffer to use: 0 - memory read, 1 - memory write chn, # input chn; // channel buffer to use: 0 - memory read, 1 - memory write
wait_complete): # input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished wait_complete): # input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
""" """
Schedule PS PIO memory transaction Schedule PS PIO memory transaction
<seq_addr> 10-bit sequence start address <seq_addr> 10-bit sequence start address
...@@ -971,7 +971,7 @@ class X393PIOSequences(object): ...@@ -971,7 +971,7 @@ class X393PIOSequences(object):
2, # input [1:0] page; # buffer page number 2, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO) 0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write 0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately) self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 2, num, show_rslt ) # chn=0, page=2, number of 32-bit words=num, show_rslt return self.x393_mcntrl_buffers.read_block_buf_chn (0, 2, num, show_rslt ) # chn=0, page=2, number of 32-bit words=num, show_rslt
...@@ -992,7 +992,7 @@ class X393PIOSequences(object): ...@@ -992,7 +992,7 @@ class X393PIOSequences(object):
3, # input [1:0] page; # buffer page number 3, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO) 0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write 0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished wait_complete) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately) self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt
...@@ -1146,7 +1146,7 @@ class X393PIOSequences(object): ...@@ -1146,7 +1146,7 @@ class X393PIOSequences(object):
0, # input [1:0] page; # buffer page number 0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO) 0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write 0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE );# wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished wait_complete) # `PS_PIO_WAIT_COMPLETE );# wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately) self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt
...@@ -1234,7 +1234,7 @@ class X393PIOSequences(object): ...@@ -1234,7 +1234,7 @@ class X393PIOSequences(object):
0, # input [1:0] page; # buffer page number 0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO) 0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write 0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately) self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
...@@ -1285,9 +1285,9 @@ class X393PIOSequences(object): ...@@ -1285,9 +1285,9 @@ class X393PIOSequences(object):
self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first) self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
vrlg.INITIALIZE_OFFSET, # input [9:0] seq_addr; # sequence start address vrlg.INITIALIZE_OFFSET, # input [9:0] seq_addr; # sequence start address
0, # input [1:0] page; # buffer page number 0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, wiil not pass in this FIFO) 0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write 0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete ); # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished wait_complete ); # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
# Wait PS PIO sequence DOEN # Wait PS PIO sequence DOEN
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE, 1 , 2.0); # wait FIFO not half full, sync sequences, timeout 2 sec self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE, 1 , 2.0); # wait FIFO not half full, sync sequences, timeout 2 sec
......
...@@ -78,6 +78,7 @@ GLBL_WINDOW = None ...@@ -78,6 +78,7 @@ GLBL_WINDOW = None
# for now - single sensor type per interface # for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"}, SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}} x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3}, SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}} # SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
...@@ -188,6 +189,11 @@ class X393SensCmprs(object): ...@@ -188,6 +189,11 @@ class X393SensCmprs(object):
if quiet == 0: if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv)) print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1) # time.sleep(0.1)
def setupSensorsPower(self, ifaceType, quiet=0):
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0): def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
""" """
Set interface voltage and turn on power for interface and the sensors Set interface voltage and turn on power for interface and the sensors
...@@ -212,7 +218,9 @@ class X393SensCmprs(object): ...@@ -212,7 +218,9 @@ class X393SensCmprs(object):
if quiet == 0: if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair])) print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1) # time.sleep(0.1)
# for sub_pair in (0,1):
# self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
# def getSensorInterfaceType(self): # def getSensorInterfaceType(self):
# """ # """
# Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi # Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
...@@ -220,16 +228,19 @@ class X393SensCmprs(object): ...@@ -220,16 +228,19 @@ class X393SensCmprs(object):
# """ # """
# return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI" # return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def setupSensorsPowerClock(self,quiet=0):
def setupSensorsPowerClock(self, setPower=False, quiet=0):
""" """
Set interface voltage for all sensors, clock for frequency and sensor power Set interface voltage for all sensors, clock for frequency and sensor power
for the interface matching bitstream file for the interface matching bitstream file
Not possible for diff. termination - power should be set before the bitstream
""" """
ifaceType = self.x393Sensor.getSensorInterfaceType(); ifaceType = self.x393Sensor.getSensorInterfaceType();
if quiet == 0: if setPower:
print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType)) if quiet == 0:
for sub_pair in (0,1): print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType))
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"]) for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
self.setSensorClock(freq_MHz = SENSOR_INTERFACES[ifaceType]["freq"], iface = SENSOR_INTERFACES[ifaceType]["iface"]) self.setSensorClock(freq_MHz = SENSOR_INTERFACES[ifaceType]["freq"], iface = SENSOR_INTERFACES[ifaceType]["iface"])
# def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS"): # def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS"):
...@@ -1158,8 +1169,10 @@ class X393SensCmprs(object): ...@@ -1158,8 +1169,10 @@ class X393SensCmprs(object):
self.setSensorClock(freq_MHz = 24.0) self.setSensorClock(freq_MHz = 24.0)
""" """
if verbose >0 : if verbose >0 :
print ("===================== Set up sensor and interface power, clock generator =========================") # print ("===================== Set up sensor and interface power, clock generator =========================")
self.setupSensorsPowerClock(quiet = (verbose >0)) print ("===================== Set up clock generator (power should be set before bitstream) =========================")
self.setupSensorsPowerClock(setPower=False, # Should be set before bitstream
quiet = (verbose >0))
if exit_step == 1: return False if exit_step == 1: return False
if verbose >0 : if verbose >0 :
print ("===================== GPIO_SETUP =========================") print ("===================== GPIO_SETUP =========================")
......
...@@ -40,8 +40,12 @@ import vrlg # global parameters ...@@ -40,8 +40,12 @@ import vrlg # global parameters
import x393_axi_control_status import x393_axi_control_status
import shutil import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit" DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240 FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL=0xf8000178 FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
FPGA_DEVCFG_CTRL = 0xf8007000 # &= (1 << 30) - reset
FPGA_LOAD_BITSTREAM="/dev/xdevcfg" FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c INT_STS= 0xf800700c
#SAVE_FILE_NAME="Some_name"# None #SAVE_FILE_NAME="Some_name"# None
...@@ -86,6 +90,25 @@ class X393Utils(object): ...@@ -86,6 +90,25 @@ class X393Utils(object):
else: else:
for d in data: for d in data:
self.x393_mem.write_mem(FPGA_RST_CTRL,d) self.x393_mem.write_mem(FPGA_RST_CTRL,d)
def fpga_shutdown(self,
quiet = 1):
if quiet < 2:
print ("fpga_shutdown(): FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
if quiet < 2:
print ("fpga_shutdown(): Reset ON")
self.reset(0)
if quiet < 2:
print ("fpga_shutdown(): Disabling level shifters")
# turn off level shifters
self.x393_mem.write_mem(FPGA_LVL_SHFTR,0)
old_devcfg_ctrl = self.x393_mem.read_mem(FPGA_DEVCFG_CTRL)
if quiet < 2:
print ("fpga_shutdown():FPGA_DEVCFG_CTRL was 0x%08x"%(old_devcfg_ctrl))
print ("fpga_shutdown(): Applying PROG_B")
self.x393_mem.write_mem(FPGA_DEVCFG_CTRL,old_devcfg_ctrl & ~(1 << 30))
def bitstream(self, def bitstream(self,
bitfile=None, bitfile=None,
quiet=1): quiet=1):
...@@ -100,8 +123,8 @@ class X393Utils(object): ...@@ -100,8 +123,8 @@ class X393Utils(object):
# POWER393_PATH = '/sys/devices/elphel393-pwr.1' # POWER393_PATH = '/sys/devices/elphel393-pwr.1'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0' POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
with open (POWER393_PATH + "/channels_dis","w") as f: # with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f) # print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF") print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1) self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON") print ("Reset ON")
......
...@@ -98,6 +98,7 @@ module sens_10398 #( ...@@ -98,6 +98,7 @@ module sens_10398 #(
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
...@@ -368,6 +369,7 @@ module sens_10398 #( ...@@ -368,6 +369,7 @@ module sens_10398 #(
.HISPI_FIFO_START (HISPI_FIFO_START), .HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),