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Commit c4c0d10a authored by Andrey Filippov's avatar Andrey Filippov
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working on address export for C, fixed some copied typos in multiple files

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.project
View file @ c4c0d10a
......@@ -62,52 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160319192210839.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160316133233827.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160319192210839.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -127,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160316133233827.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160319192210839.dcp</location>
</link>
</linkedResources>
</projectDescription>
fpga_version.vh
View file @ c4c0d10a
......@@ -31,9 +31,16 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller
// parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
parameter FPGA_VERSION = 32'h0393007b; // lvcmos25_lvds_25_diff
// parameter FPGA_VERSION = 32'h0393007a; // lvcmos25_ppds_25_nodiff - OK
// parameter FPGA_VERSION = 32'h03930079; // diff - failed
// parameter FPGA_VERSION = 32'h03930078; // lvcmos18_ppds_25_nodiff
// parameter FPGA_VERSION = 32'h03930077; // Restoring IOSTANDARDs - OK
// parameter FPGA_VERSION = 32'h03930076; // Trying PPDS_25 with 1.8 actual power - Stuck when applying 1.8 or 2.5V
// parameter FPGA_VERSION = 32'h03930075; // Trying IN_TERM = "UNTUNED_50"
// parameter FPGA_VERSION = 32'h03930074; // Adding SATA controller 16365 ( 83.28%)
// parameter FPGA_VERSION = 32'h03930073; // Adding interrupts support
// parameter FPGA_VERSION = 32'h03930072; // Adding hact monitor bit 77.9%, failed timing
// parameter FPGA_VERSION = 32'h03930071; // Fixing AXI HP multiplexer xclk -0.083 -1.968 44 / 15163 (77.17%)
// parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
......
includes/tasks_tests_memory.vh
View file @ c4c0d10a
......@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
......@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
......@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
......@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end
......@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
......
includes/x393_parameters.vh
View file @ c4c0d10a
/*******************************************************************************
* File: x393_parameters.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Parameters for the x393 (simulation and implementation)
*
* Copyright (c) 2015 Elphel, Inc.
......@@ -43,7 +43,7 @@
parameter STATUS_ADDR = 'h0800, // AXI read address of status read registers
parameter STATUS_ADDR_MASK = 'h3c00, // AXI write address of status registers
parameter MCONTR_CMD_WR_ADDR = 'h0c00, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h1000, // AXI read address from buffer 0 (PS sequence, memory read) (was 'h400)
......@@ -55,29 +55,29 @@
parameter MCONTR_BUF3_WR_ADDR = 'h1800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h1c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF4_WR_ADDR = 'h1c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
parameter AXI_WR_ADDR_BITS = 14,
parameter AXI_RD_ADDR_BITS = 14,
parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
// 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
// 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
// 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
// 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
// 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
// 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // enable/disable active-low reset signal to DDR3 memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
//0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
......@@ -85,26 +85,26 @@
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1050 - PATTERNS // 16 bits
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// 0x1053 - EXTRA_REL // 1 bit - set extra parameters (currently just inv_clk_div)
// 0x1054 - STATUS_CNTRL // 8 bits - write to status control
parameter MCONTR_PHY_16BIT_PATTERNS = 'h0, // set DQM and DQS patterns (16'h0055)
parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter MCONTR_PHY_16BIT_WBUF_DELAY = 'h2, // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
parameter MCONTR_PHY_16BIT_EXTRA = 'h3, // ? bits - set extra parameters (currently just inv_clk_div)
parameter MCONTR_PHY_STATUS_CNTRL = 'h4, // write to status control (8-bit)
//0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h7f0, // Address mask to set channel priorities
......@@ -119,23 +119,23 @@
parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1, // 8-bit refresh period
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
// Status read address
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'haa, // TODO: make work for the simulator too 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h9, // TODO: Find the reason - simulation needs 8, target - 9
parameter DFLT_WBUF_DELAY= 4'h9, // TODO: Find the reason - simulation needs 8, target - 9
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
parameter DFLT_REFRESH_ADDR= 10'h0, // refresh sequence address in command memory
parameter DFLT_REFRESH_PERIOD= 8'h0, // default 8-bit refresh period (scale?)
......@@ -151,19 +151,19 @@
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
`ifdef MCLK_VCO_MULT
`ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else
`else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif
`endif
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
`endif
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new
parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000, //11.25, /// 0.000,
......@@ -175,9 +175,9 @@
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
parameter NUM_CYCLES_LOW_BIT= 'h6, // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
// TODO: put actual data
// TODO: put actual data
parameter NUM_CYCLES_00 = 2, // 2-cycle 000.003f
parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
......@@ -210,7 +210,7 @@
parameter NUM_CYCLES_29 = 6, //
parameter NUM_CYCLES_30 = 6, //
parameter NUM_CYCLES_31 = 6, //
// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
parameter MCNTRL_PS_ADDR= 'h100,
......@@ -221,8 +221,8 @@
parameter MCNTRL_PS_STATUS_CNTRL= 'h2,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
......@@ -245,8 +245,8 @@
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
......@@ -273,22 +273,22 @@
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
parameter BUFFER_DEPTH32= 10, // Block RAM buffer depth on a 32-bit port
// bits in mode control word
parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
parameter MCONTR_LINTILE_EN = 1, // enable requests
parameter MCONTR_LINTILE_EN = 1, // enable requests
parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
......@@ -304,7 +304,7 @@
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
parameter MCONTR_SENS_BASE = 'h680, // .. 'h6bf
parameter MCONTR_SENS_INC = 'h10,
parameter MCONTR_CMPRS_BASE = 'h6c0, // .. 'h6ff
......@@ -314,7 +314,7 @@
parameter MCONTR_CMPRS_STATUS_BASE = 'h2c, // .. 'h2f
parameter MCONTR_CMPRS_STATUS_INC = 'h1,
// membridge module parameters
// membridge module parameters
parameter MEMBRIDGE_ADDR= 'h200,
parameter MEMBRIDGE_MASK= 'h7f0,
parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 01 - start, 11 - start and reset address
......@@ -324,19 +324,19 @@
parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0, // late/early WRITE commands (to adjust timing by 1 SDCLK period)
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
......@@ -345,17 +345,17 @@
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
// parameters defining address map
parameter SENSOR_CTRL_RADDR = 0, // relative to SENSOR_GROUP_ADDR
parameter SENSOR_CTRL_RADDR = 0, // relative to SENSOR_GROUP_ADDR
parameter SENSOR_CTRL_ADDR_MASK = 'h7ff, //
// bits of the SENSOR mode register
parameter SENSOR_MODE_WIDTH = 10,
parameter SENSOR_HIST_EN_BITS = 0, // 0..3 1 - enable histogram modules, disable after processing the started frame
parameter SENSOR_HIST_NRST_BITS = 4, // 0 - immediately reset all histogram modules
parameter SENSOR_HIST_NRST_BITS = 4, // 0 - immediately reset all histogram modules
parameter SENSOR_CHN_EN_BIT = 8, // 1 - this enable channel
parameter SENSOR_16BIT_BIT = 9, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
parameter SENSI2C_CTRL_RADDR = 2, // 302..'h303
parameter SENSI2C_CTRL_MASK = 'h7fe,
// sensor_i2c_io relative control register addresses
......@@ -363,16 +363,16 @@
// Control register bits
parameter SENSI2C_CMD_TABLE = 29, // [29]: 1 - write to translation table (ignore any other fields), 0 - write other fields
parameter SENSI2C_CMD_TAND = 28, // [28]: 1 - write table address (8 bits), 0 - write table data (28 bits)
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
//i2c page table bit fields
parameter SENSI2C_TBL_RAH = 0, // high byte of the register address
parameter SENSI2C_TBL_RAH = 0, // high byte of the register address
parameter SENSI2C_TBL_RAH_BITS = 8,
parameter SENSI2C_TBL_RNWREG = 8, // read register (when 0 - write register
parameter SENSI2C_TBL_SA = 9, // Slave address in write mode
......@@ -384,18 +384,18 @@
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_STATUS = 'h1,
parameter SENS_SYNC_RADDR = 'h4,
parameter SENS_SYNC_MASK = 'h7fc,
// 2 locations reserved for control/status (if they will be needed)
parameter SENS_SYNC_MULT = 'h2, // relative register address to write number of frames to combine in one (minus 1, '0' - each farme)
parameter SENS_SYNC_LATE = 'h3, // number of lines to delay late frame sync
parameter SENS_GAMMA_RADDR = 'h38, // 'h38..'h3b was 4,
parameter SENS_GAMMA_ADDR_MASK = 'h7fc,
// sens_gamma registers
......@@ -410,10 +410,10 @@
parameter SENS_GAMMA_MODE_EN = 3,
parameter SENS_GAMMA_MODE_REPET = 4,
parameter SENS_GAMMA_MODE_TRIG = 5,
// Vignetting correction / pixel value scaling - controlled via single data word (same as in 252), some of bits [23:16]
// are used to select register, bits 25:24 - select sub-frame
parameter SENS_LENS_RADDR = 'h3c,
parameter SENS_LENS_RADDR = 'h3c,
parameter SENS_LENS_ADDR_MASK = 'h7fc,
parameter SENS_LENS_COEFF = 'h3, // set vignetting/scale coefficients (
parameter SENS_LENS_AX = 'h00, // 00000...
......@@ -434,7 +434,7 @@
parameter SENS_LENS_FAT0_OUT_MASK = 'hff,
parameter SENS_LENS_POST_SCALE = 'h6a, // 01101010
parameter SENS_LENS_POST_SCALE_MASK = 'hff,
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
// sens_parallel12 registers
......@@ -446,18 +446,18 @@
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
//`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
//`else
//`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
//`endif
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
//`else
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
//`endif
//`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
......@@ -468,7 +468,7 @@
parameter SENS_JTAG_TDI = 0,
//`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
//`endif
//`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
......@@ -485,18 +485,18 @@
// sens_hist registers
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
//sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
//`endif
//`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
......@@ -506,20 +506,20 @@
parameter HIST_CONFIRM_WRITE = 2, // wait write confirmation for each block
// bit 3 is not used
parameter HIST_SAXI_AWCACHE = 4, // ..7 Write 4'h3 there, cache mode (4 bits, default 4'h3)
parameter HIST_SAXI_MODE_ADDR_MASK = 'h7ff,
parameter NUM_FRAME_BITS = 4, // number of bits use for frame number
parameter NUM_FRAME_BITS = 4, // number of bits use for frame number
// Other parameters
parameter SENS_SYNC_FBITS = 16, // number of bits in a frame counter for linescan mode
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LATE_DFLT = 15, // number of lines to delay late frame sync
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
......@@ -529,32 +529,38 @@
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
`else
parameter real SENS_REFCLK_FREQUENCY = 200.0,
`endif
`endif
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
//`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`endif
//`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
`define TWEAKING_IOSTANDARD
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
// parameter PXD_IOSTANDARD = "LVCMOS25",
// parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`else
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`endif
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
......@@ -562,22 +568,36 @@
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFIO", /// "BUFR", //G", // "BUFR",
parameter BUF_IPCLK2X_SENS0 = "BUFIO", /// "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFIO", ///"BUFR", //G", // "BUFR",
parameter BUF_IPCLK2X_SENS2 = "BUFIO", ///"BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -590,10 +610,10 @@
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK0= "TRUE",
parameter HISPI_DELAY_CLK1= "TRUE",
parameter HISPI_DELAY_CLK2= "TRUE",
parameter HISPI_DELAY_CLK3= "TRUE",
parameter HISPI_DELAY_CLK0= "TRUE",
parameter HISPI_DELAY_CLK1= "TRUE",
parameter HISPI_DELAY_CLK2= "TRUE",
parameter HISPI_DELAY_CLK3= "TRUE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
......@@ -603,28 +623,27 @@
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif DIFF_HSTL_II_18
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif DIFF_HSTL_II_18
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_MASK= 'h7f0,
parameter CMPRS_STATUS_REG_BASE= 'h10,
parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations
parameter CMPRS_AFIMUX_REG_ADDR1= 'h1c, // Uses 4 locations
parameter CMPRS_STATUS_REG_INC= 1,
parameter CMPRS_HIFREQ_REG_INC= 1,
parameter CMPRS_MASK= 'h7f8,
......@@ -639,7 +658,7 @@
parameter TABLE_CORING_INDEX = 1,
parameter TABLE_FOCUS_INDEX = 2,
parameter TABLE_HUFFMAN_INDEX = 3,
// Bit-fields in compressor control word
parameter CMPRS_CBIT_RUN = 2, // bit # to control compressor run modes
......@@ -674,7 +693,7 @@
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
......@@ -683,7 +702,7 @@
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word
......@@ -695,10 +714,10 @@
parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_TIMEOUT_BITS= 12,
parameter CMPRS_TIMEOUT= 1000, // mclk cycles
parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
......@@ -713,19 +732,19 @@
parameter GPIO_ADDR = 'h700, // .701
parameter GPIO_MASK = 'h7fe,
parameter GPIO_STATUS_REG_ADDR = 'h30, // address where status can be read out (10 GPIO inputs)
parameter GPIO_IBUF_LOW_PWR = "TRUE",
parameter GPIO_IOSTANDARD = "LVCMOS15", // power is 1.5V
parameter GPIO_SLEW = "SLOW",
parameter GPIO_SET_PINS = 0, // Set GPIO output state, give control for some bits to other modules
parameter GPIO_SET_PINS = 0, // Set GPIO output state, give control for some bits to other modules
parameter GPIO_SET_STATUS = 1, // set status mode
parameter GPIO_N = 10, // number of GPIO bits to control
parameter GPIO_PORTEN = 24, // bit number to control port enables (up from this)
// Timing (rtc+camsync) parameters
parameter GPIO_PORTEN = 24, // bit number to control port enables (up from this)
// Timing (rtc+camsync) parameters
parameter RTC_ADDR= 'h704, // 'h707
parameter CAMSYNC_ADDR = 'h708, // 'h70f
parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address)
parameter RTC_MASK = 'h7fc,
parameter CAMSYNC_MASK = 'h7f8,
......@@ -746,9 +765,9 @@
parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation
parameter CAMSYNC_PRE_MAGIC = 6'b110100,
parameter CAMSYNC_POST_MAGIC = 6'b001101,
parameter RTC_MHZ= 25, // RTC input clock in MHz (should be interger number)
parameter RTC_BITC_PREDIV = 5, // number of bits to generate 2 MHz pulses counting refclk
parameter RTC_BITC_PREDIV = 5, // number of bits to generate 2 MHz pulses counting refclk
parameter RTC_SET_USEC= 0, // 20-bit number of microseconds
parameter RTC_SET_SEC= 1, // 32-bit full number of seconds (und actually update timer)
parameter RTC_SET_CORR= 2, // write correction 16-bit signed
......@@ -764,7 +783,7 @@
parameter CMDFRAMESEQ_RST_BIT = 14,
parameter CMDFRAMESEQ_RUN_BIT = 13,
parameter CMDFRAMESEQ_IRQ_BIT = 0,
parameter CMDSEQMUX_ADDR = 'h702, // only status control
parameter CMDSEQMUX_MASK = 'h7ff,
parameter CMDSEQMUX_STATUS = 'h38,
......@@ -778,7 +797,7 @@
parameter LOGGER_PAGE_IMU = 0, // 'h00..'h1f - overlaps with period/duration/halfperiod/config?
parameter LOGGER_PAGE_GPS = 1, // 'h20..'h3f
parameter LOGGER_PAGE_MSG = 2, // 'h40..'h5f
parameter LOGGER_PERIOD = 0,
parameter LOGGER_BIT_DURATION = 1,
parameter LOGGER_BIT_HALF_PERIOD = 2, //rs232 half bit period
......@@ -799,7 +818,7 @@
parameter MULT_SAXI_HALF_BRAM_IN = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_WLOG = 4, // number of bits for the input data ( 3 - 8 bit, 4 - 16-bit, 5 - 32-bit
parameter MULT_SAXI_ADDR = 'h730, // ..'h737
parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
......@@ -814,17 +833,17 @@
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3, // number of clock cycles before end of write to genearte adv_wr_done
// Clock management (input, generation, buffering)
// Clock management (input, generation, buffering)
parameter CLK_ADDR = 'h728, // ..'h729
parameter CLK_MASK = 'h7fe, //
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
// These are needed for Python:
//`ifdef DEBUG_RING
// Debug module (read/write serial ring)
parameter DEBUG_ADDR = 'h710, //..'h713 // SuppressThisWarning VEditor
parameter DEBUG_ADDR = 'h710, //..'h713 // SuppressThisWarning VEditor
parameter DEBUG_MASK = 'h7fc,
parameter DEBUG_STATUS_REG_ADDR = 'hfc, // address where status can be read out // SuppressThisWarning VEditor
parameter DEBUG_READ_REG_ADDR = 'hfd, // read 32-bit received shifted data// SuppressThisWarning VEditor
......@@ -846,9 +865,9 @@
`ifdef USE_XCLK2X
parameter MULTICLK_DIV_XCLK = 12, // 100 MHz for compressor
parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
`else
`else
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
`endif
`endif
parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
// Additional parameters for multi-clock PLL (phases and buffer types)
parameter MULTICLK_PHASE_FB = 0.0,
......@@ -861,10 +880,10 @@
`ifdef USE_XCLK2X
parameter MULTICLK_PHASE_XCLK2X = 0.0,
parameter MULTICLK_BUF_XCLK2X = "BUFG",
`endif
`endif
parameter MULTICLK_PHASE_SYNC = 0.0,
parameter MULTICLK_BUF_SYNC = "BUFG",
// parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
// parameter DIVCLK_DIVIDE_AXIHP = 1,
// parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
......@@ -874,40 +893,20 @@
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 36, // 880 MHz
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
`endif
parameter PHASE_CLK2X_PCLK = 0.000,
`endif
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
// parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
// parameter DIVCLK_DIVIDE_XCLK = 1,
// parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
//`ifdef USE_XCLK2X
// parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
//`else
// parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
//`endif
// parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
// parameter PHASE_CLK2X_XCLK = 0.000,
// parameter BUF_CLK1X_XCLK = "BUFG",
// parameter BUF_CLK1X_XCLK2X = "BUFG",
// parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
// parameter DIVCLK_DIVIDE_SYNC = 1,
// parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
// parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
// parameter BUF_CLK1X_SYNC = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IOSTANDARD = "SSTL15",
......@@ -916,16 +915,15 @@
parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IOSTANDARD = "RSDS_25",
parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IOSTANDARD = "RSDS_25"
\ No newline at end of file
includes/x393_tasks_ps_pio.vh
View file @ c4c0d10a
......@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to
input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
......
py393/test_mcntrl.py
View file @ c4c0d10a
......@@ -72,6 +72,7 @@ import x393_sensor
import x393_rtc
import x393_jpeg
import vrlg
import x393_export_c
__all__ = []
__version__ = 0.1
__date__ = '2015-03-01'
......@@ -357,6 +358,7 @@ USAGE
x393Sensor = x393_sensor.X393Sensor(verbose,args.simulated,args.localparams)
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams)
x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams)
'''
print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__))
......@@ -390,6 +392,7 @@ USAGE
extractTasks(x393_sensor.X393Sensor, x393Sensor)
extractTasks(x393_rtc.X393Rtc, x393Rtc)
extractTasks(x393_jpeg.X393Jpeg, x393Jpeg)
extractTasks(x393_export_c.X393ExportC, x393ExportC)
for cmdLine in commands:
print ('Running task: '+str(cmdLine))
......
py393/vrlg.py
View file @ c4c0d10a
......@@ -711,6 +711,7 @@ MCONTR_LINTILE_REPEAT = int
CHNBUF_READ_LATENCY = int
SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str
WBUF_DLY_DFLT__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str
TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
......@@ -917,7 +918,7 @@ T_RFC__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
SENSI2C_REL_RADDR__RAW = str
FRAME_START_ADDRESS = int
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
......@@ -1151,7 +1152,7 @@ MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
CMPRS_FRMT_LMARG__RAW = str
SENSOR_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
LOGGER_BIT_DURATION = int
CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
......@@ -1165,6 +1166,7 @@ LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int
CMDFRAMESEQ_IRQ_BIT__TYPE = str
PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
......@@ -1186,6 +1188,7 @@ CMPRS_CBIT_CMODE_JP4DC__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
CMDFRAMESEQ_REL = int
......@@ -1265,7 +1268,7 @@ SENSIO_ADDR_MASK = int
SCANLINE_STARTY = int
SCANLINE_STARTX = int
FFCLK0_DIFF_TERM__TYPE = str
WBUF_DLY_DFLT__RAW = str
HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN = int
CMPRS_CBIT_RUN_RST = int
......@@ -1293,7 +1296,7 @@ DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
WINDOW_X0__RAW = str
FRAME_START_ADDRESS = int
CMDFRAMESEQ_IRQ_BIT = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
CMPRS_GROUP_ADDR = int
......@@ -1833,6 +1836,7 @@ SENSIO_RADDR__RAW = str
DFLT_CHN_EN__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCLK_PHASE = float
CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
......@@ -1874,6 +1878,7 @@ MCONTR_BUF3_RD_ADDR__RAW = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
LOGGER_CONF_GPS_BITS = int
HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
......@@ -2075,6 +2080,7 @@ RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_INTERRUPTS__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int
......@@ -2130,6 +2136,7 @@ AXI_WR_ADDR_BITS = int
FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
......@@ -2154,6 +2161,7 @@ MULT_SAXI_ADDR = int
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
SENSOR_BASE_INC = int
MULT_SAXI_CNTRL_MASK__RAW = str
SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str
......@@ -2183,6 +2191,7 @@ DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str
LOGGER_STATUS = int
CMDFRAMESEQ_RUN_BIT__RAW = str
py393/x393_jpeg.py
View file @ c4c0d10a
......@@ -966,6 +966,7 @@ ff d9
"""
"""
cd /usr/local/verilog/; test_mcntrl.py @hargs
setupSensorsPower "HISPI"
measure_all "*DI"
setup_all_sensors True None 0xf
#write_sensor_i2c 0 1 0 0x30700101
......
py393/x393_pio_sequences.py
View file @ c4c0d10a
......@@ -68,9 +68,9 @@ class X393PIOSequences(object):
def schedule_ps_pio(self, #; // schedule software-control memory operation (may need to check FIFO status first)
seq_addr, # input [9:0] seq_addr; // sequence start address
page, # input [1:0] page; // buffer page number
urgent, # input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
urgent, # input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
chn, # input chn; // channel buffer to use: 0 - memory read, 1 - memory write
wait_complete): # input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete): # input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
"""
Schedule PS PIO memory transaction
<seq_addr> 10-bit sequence start address
......@@ -971,7 +971,7 @@ class X393PIOSequences(object):
2, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 2, num, show_rslt ) # chn=0, page=2, number of 32-bit words=num, show_rslt
......@@ -992,7 +992,7 @@ class X393PIOSequences(object):
3, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt
......@@ -1146,7 +1146,7 @@ class X393PIOSequences(object):
0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE );# wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # `PS_PIO_WAIT_COMPLETE );# wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # wait previous memory transaction finished before changing delays (effective immediately)
buf=self.x393_mcntrl_buffers.read_block_buf_chn (0, 0, numBufWords, (0,1)[quiet<1]) # chn=0, page=0, number of 32-bit words=32, show_rslt
......@@ -1234,7 +1234,7 @@ class X393PIOSequences(object):
0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete) # `PS_PIO_WAIT_COMPLETE ) # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
......@@ -1285,9 +1285,9 @@ class X393PIOSequences(object):
self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
vrlg.INITIALIZE_OFFSET, # input [9:0] seq_addr; # sequence start address
0, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, # input urgent; # high priority request (only for competition with other channels, will not pass in this FIFO)
0, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete ); # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_complete ); # wait_complete; # Do not request a new transaction from the scheduler until previous memory transaction is finished
# Wait PS PIO sequence DOEN
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE, 1 , 2.0); # wait FIFO not half full, sync sequences, timeout 2 sec
......
py393/x393_sens_cmprs.py
View file @ c4c0d10a
......@@ -78,6 +78,7 @@ GLBL_WINDOW = None
# for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
SENSOR_DEFAULTS= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# SENSOR_INTERFACE_HISPI: {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
......@@ -188,6 +189,11 @@ class X393SensCmprs(object):
if quiet == 0:
print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))
# time.sleep(0.1)
def setupSensorsPower(self, ifaceType, quiet=0):
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
def setSensorIfaceVoltagePower(self, sub_pair, voltage_mv, quiet=0):
"""
Set interface voltage and turn on power for interface and the sensors
......@@ -212,7 +218,9 @@ class X393SensCmprs(object):
if quiet == 0:
print ("Turned on +3.3V power for sensors %s"%(("0, 1","2, 3")[sub_pair]))
# time.sleep(0.1)
# for sub_pair in (0,1):
# self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
# def getSensorInterfaceType(self):
# """
# Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
......@@ -220,16 +228,19 @@ class X393SensCmprs(object):
# """
# return (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
def setupSensorsPowerClock(self,quiet=0):
def setupSensorsPowerClock(self, setPower=False, quiet=0):
"""
Set interface voltage for all sensors, clock for frequency and sensor power
for the interface matching bitstream file
Not possible for diff. termination - power should be set before the bitstream
"""
ifaceType = self.x393Sensor.getSensorInterfaceType();
if quiet == 0:
print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType))
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
if setPower:
if quiet == 0:
print ("Configuring sensor ports for interface type: \"%s\""%(ifaceType))
for sub_pair in (0,1):
self.setSensorIfaceVoltagePower(sub_pair, SENSOR_INTERFACES[ifaceType]["mv"])
self.setSensorClock(freq_MHz = SENSOR_INTERFACES[ifaceType]["freq"], iface = SENSOR_INTERFACES[ifaceType]["iface"])
# def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS"):
......@@ -1158,8 +1169,10 @@ class X393SensCmprs(object):
self.setSensorClock(freq_MHz = 24.0)
"""
if verbose >0 :
print ("===================== Set up sensor and interface power, clock generator =========================")
self.setupSensorsPowerClock(quiet = (verbose >0))
# print ("===================== Set up sensor and interface power, clock generator =========================")
print ("===================== Set up clock generator (power should be set before bitstream) =========================")
self.setupSensorsPowerClock(setPower=False, # Should be set before bitstream
quiet = (verbose >0))
if exit_step == 1: return False
if verbose >0 :
print ("===================== GPIO_SETUP =========================")
......
py393/x393_utils.py
View file @ c4c0d10a
......@@ -40,8 +40,12 @@ import vrlg # global parameters
import x393_axi_control_status
import shutil
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178
FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
FPGA_DEVCFG_CTRL = 0xf8007000 # &= (1 << 30) - reset
FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c
#SAVE_FILE_NAME="Some_name"# None
......@@ -86,6 +90,25 @@ class X393Utils(object):
else:
for d in data:
self.x393_mem.write_mem(FPGA_RST_CTRL,d)
def fpga_shutdown(self,
quiet = 1):
if quiet < 2:
print ("fpga_shutdown(): FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
if quiet < 2:
print ("fpga_shutdown(): Reset ON")
self.reset(0)
if quiet < 2:
print ("fpga_shutdown(): Disabling level shifters")
# turn off level shifters
self.x393_mem.write_mem(FPGA_LVL_SHFTR,0)
old_devcfg_ctrl = self.x393_mem.read_mem(FPGA_DEVCFG_CTRL)
if quiet < 2:
print ("fpga_shutdown():FPGA_DEVCFG_CTRL was 0x%08x"%(old_devcfg_ctrl))
print ("fpga_shutdown(): Applying PROG_B")
self.x393_mem.write_mem(FPGA_DEVCFG_CTRL,old_devcfg_ctrl & ~(1 << 30))
def bitstream(self,
bitfile=None,
quiet=1):
......@@ -100,8 +123,8 @@ class X393Utils(object):
# POWER393_PATH = '/sys/devices/elphel393-pwr.1'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
# with open (POWER393_PATH + "/channels_dis","w") as f:
# print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
print ("Reset ON")
......
sensor/sens_10398.v
View file @ c4c0d10a
......@@ -98,6 +98,7 @@ module sens_10398 #(
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -368,6 +369,7 @@ module sens_10398 #(
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
sensor/sens_hispi12l4.v
View file @ c4c0d10a
......@@ -68,6 +68,7 @@ module sens_hispi12l4#(
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -197,6 +198,7 @@ module sens_hispi12l4#(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
sensor/sens_hispi_clock.v
View file @ c4c0d10a
......@@ -61,6 +61,7 @@ module sens_hispi_clock#(
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -97,20 +98,37 @@ module sens_hispi_clock#(
assign ps_rdy = (HISPI_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (HISPI_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
generate
if (HISPI_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end
endgenerate
generate
if (HISPI_DELAY_CLK == "TRUE") begin
idelay_nofine # (
......
sensor/sens_hispi_din.v
View file @ c4c0d10a
......@@ -42,6 +42,7 @@ module sens_hispi_din #(
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -67,19 +68,35 @@ module sens_hispi_din #(
generate
genvar i;
for (i=0; i < HISPI_NUMLANES; i=i+1) begin: din_block
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
if (HISPI_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM),
.DQS_BIAS (HISPI_DQS_BIAS),
.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
......
sensor/sensor_channel.v
View file @ c4c0d10a
......@@ -81,7 +81,7 @@ module sensor_channel#(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
......@@ -263,6 +263,7 @@ module sensor_channel#(
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -788,6 +789,7 @@ module sensor_channel#(
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
sensor/sensor_i2c.v
View file @ c4c0d10a
......@@ -49,7 +49,7 @@ module sensor_i2c#(
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
......
sensor/sensor_i2c_io.v
View file @ c4c0d10a
......@@ -49,7 +49,7 @@ module sensor_i2c_io#(
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
......
sensor/sensors393.v
View file @ c4c0d10a
......@@ -40,7 +40,7 @@ module sensors393 #(
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
// Sesnors use 8 status registers, 'h20..'h27
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
......@@ -72,7 +72,7 @@ module sensors393 #(
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_FIFO_RD = 3, // advane I2C read data FIFO by 1
parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1
parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
parameter SENSI2C_CMD_ACIVE_SDA = 0, // drive SDA=1 during the second half of SCL=1
......@@ -295,6 +295,7 @@ module sensors393 #(
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
......@@ -620,6 +621,7 @@ module sensors393 #(
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......
wrap/ibufds_ibufgds.v
View file @ c4c0d10a
......@@ -70,3 +70,33 @@ module ibufds_ibufgds #(
endmodule
module ibufds_ibufgds_50 #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
(* IN_TERM="UNTUNED_SPLIT_50" *)
IBUFDS #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
.DQS_BIAS (DQS_BIAS),
.IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFDS_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
wrap/pll_base.v
View file @ c4c0d10a
......@@ -2,7 +2,7 @@
* Module: pll_base
* Date:2014-05-01
* Author: Andrey Filippov
* Description: PLLE2_BASE wrapper
* Description: PLLE2_ADV wrapper for PLL_BASE functionality
*
* Copyright (c) 2014 Elphel, Inc.
* pll_base.v is free software; you can redistribute it and/or modify
......@@ -74,7 +74,7 @@ module pll_base#(
output clkfbout, // dedicate feedback output
output locked // PLL locked output
);
PLLE2_BASE #(
PLLE2_ADV #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
......@@ -100,18 +100,30 @@ module pll_base#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_BASE_i (
) PLLE2_ADV_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst) // input
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst), // input
// Unused ports for advanced option
// Unused second clock input and select
.CLKIN2 (1'b0), // input
.CLKINSEL (1'b1), // input
// Unused DRP I/O
.DADDR (7'b0), // input[6:0]
.DCLK (1'b0), // input
.DEN (1'b0), // input
.DI (16'b0), // input[15:0]
.DO (), // output[15:0]
.DRDY (), // output
.DWE () // input
);
endmodule
x393.v
View file @ c4c0d10a
......@@ -1762,6 +1762,7 @@ assign axi_grst = axi_rst_pre;
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
......@@ -1792,8 +1793,8 @@ assign axi_grst = axi_rst_pre;
`ifdef HISPI
.sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // input[3:0]
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0]
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] SuppressThisWarning VEditor vdt-bug
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
.sns_clkp ({sns4_clkp, sns3_clkp, sns2_clkp, sns1_clkp}), // input
.sns_clkn ({sns4_clkn, sns3_clkn, sns2_clkn, sns1_clkn}), // input
.sns_scl ({sns4_scl, sns3_scl, sns2_scl, sns1_scl}), // inout
......
x393_testbench01.tf
View file @ c4c0d10a
......@@ -447,9 +447,9 @@ assign #10 gpio_pins[9] = gpio_pins[8];
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
INITIALIZE_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
`ifdef WAIT_MRS
......@@ -1537,9 +1537,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
......@@ -1548,9 +1548,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
......@@ -1568,9 +1568,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
......@@ -1582,9 +1582,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end
......@@ -1595,21 +1595,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
......
x393_testbench02.tf
View file @ c4c0d10a
......@@ -666,9 +666,9 @@ assign #10 gpio_pins[9] = gpio_pins[8];
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
INITIALIZE_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
`ifdef WAIT_MRS
......
x393_testbench03.tf
View file @ c4c0d10a
......@@ -788,9 +788,9 @@ assign #10 gpio_pins[9] = gpio_pins[8];
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
INITIALIZE_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
`ifdef WAIT_MRS
......
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