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Commit bf7c096d authored by Andrey Filippov's avatar Andrey Filippov
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Trying synthesis, fixing revealed bugs

parent 16513305
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Showing with 135 additions and 118 deletions
.project
View file @ bf7c096d
......@@ -92,7 +92,7 @@
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150702180615691.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150718125232570.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
......
axi/cmprs_afi_mux.v
View file @ bf7c096d
......@@ -216,7 +216,7 @@ module cmprs_afi_mux#(
assign afi_awvalid = awvalid[1];
assign afi_awlen = {wleft[3:2],2'b11};
assign afi_wdata = wdata;
assign afi_bready = 1'b1; // always ready
// assign afi_bready = 1'b1; // always ready
// other fixed-value AFI signals
assign afi_awlock = 2'h0;
......@@ -325,7 +325,7 @@ module cmprs_afi_mux#(
else if (done_burst_w) busy <= 0; // {busy[2:0],1'b0};
if (!en) wleft <= 0;
else if (pre_busy_w) wleft <= {(|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2 * 8 +: 8][1:0], 2'b11};
else if (pre_busy_w) wleft <= {(|counts_corr2[7:2])? 2'b11 : left_to_eof[winner2 * 8 +: 2], 2'b11};
else if (wleft != 0) wleft <= wleft - 1;
......@@ -354,7 +354,7 @@ module cmprs_afi_mux#(
if (pre_busy_w) chunk_inc <= (|counts_corr2[7:2])?
3'h4 :
({1'b0,left_to_eof[winner2 * 8 +: 8][1:0]} + 3'h1);
({1'b0,left_to_eof[winner2 * 8 +: 2]} + 3'h1);
end
......
axi/mult_saxi_wr.v
View file @ bf7c096d
......@@ -445,7 +445,7 @@ module mult_saxi_wr #(
.wclk (mclk), // input
.waddr (buf_wa[8:0]), // input[9:0]
.we (buf_we), // input
.web (4'hff), // input[7:0]
.web (4'hf), // input[7:0]
.data_in (buf_wd) // input[31:0]
);
else
......
axi/mult_saxi_wr_inbuf.v
View file @ bf7c096d
......@@ -115,7 +115,7 @@ module mult_saxi_wr_inbuf#(
.wclk (iclk), // input
.waddr (waddr[13-MULT_SAXI_WLOG:0]), // input[9:0]
.we (valid), // input
.web (4'hff), // input[7:0]
.web (4'hf), // input[7:0]
.data_in (data_in) // input[31:0]
);
else
......
compressor_jp/jp_channel.v
View file @ bf7c096d
......@@ -785,6 +785,11 @@ module jp_channel#(
// Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was use3d for IMU instead of dcc
wire finish_dcc;
wire [15:0] stuffer_do;
wire stuffer_dv;
wire stuffer_done;
wire eof_written_xclk2xn;
// re-sync to posedge xclk2x
pulse_cross_clock finish_dcc_i (.rst(rst), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
......@@ -844,12 +849,6 @@ module jp_channel#(
);
wire [15:0] stuffer_do;
wire stuffer_dv;
wire stuffer_done;
wire eof_written_xclk2xn;
stuffer393 stuffer393_i (
.rst (rst), // input
.mclk (mclk), // input
......
compressor_jp/quantizer393.v
View file @ bf7c096d
......@@ -347,30 +347,29 @@ module zigzag393 (
5'h07: rom_q <= 6'h23;
5'h08: rom_q <= 6'h01;
5'h09: rom_q <= 6'h04;
5'h10: rom_q <= 6'h08;
5'h11: rom_q <= 6'h0b;
5'h12: rom_q <= 6'h13;
5'h13: rom_q <= 6'h16;
5'h14: rom_q <= 6'h22;
5'h15: rom_q <= 6'h24;
5'h16: rom_q <= 6'h05;
5'h17: rom_q <= 6'h07;
5'h18: rom_q <= 6'h0c;
5'h19: rom_q <= 6'h12;
5'h20: rom_q <= 6'h17;
5'h21: rom_q <= 6'h21;
5'h22: rom_q <= 6'h25;
5'h23: rom_q <= 6'h30;
5'h24: rom_q <= 6'h06;
5'h25: rom_q <= 6'h0d;
5'h26: rom_q <= 6'h11;
5'h27: rom_q <= 6'h18;
5'h28: rom_q <= 6'h20;
5'h29: rom_q <= 6'h26;
5'h30: rom_q <= 6'h2f;
5'h31: rom_q <= 6'h31;
5'h0a: rom_q <= 6'h08;
5'h0b: rom_q <= 6'h0b;
5'h0c: rom_q <= 6'h13;
5'h0d: rom_q <= 6'h16;
5'h0e: rom_q <= 6'h22;
5'h0f: rom_q <= 6'h24;
5'h10: rom_q <= 6'h05;
5'h11: rom_q <= 6'h07;
5'h12: rom_q <= 6'h0c;
5'h13: rom_q <= 6'h12;
5'h14: rom_q <= 6'h17;
5'h15: rom_q <= 6'h21;
5'h16: rom_q <= 6'h25;
5'h17: rom_q <= 6'h30;
5'h18: rom_q <= 6'h06;
5'h19: rom_q <= 6'h0d;
5'h1a: rom_q <= 6'h11;
5'h1b: rom_q <= 6'h18;
5'h1c: rom_q <= 6'h20;
5'h1d: rom_q <= 6'h26;
5'h1e: rom_q <= 6'h2f;
5'h1f: rom_q <= 6'h31;
endcase
// add symmetrical part
always @ (posedge clk) q[5:0] <= a[5]? (~rom_q[5:0]):rom_q[5:0];
endmodule
logger/imu_timestamps393.v
View file @ bf7c096d
......@@ -75,7 +75,7 @@ module imu_timestamps393(
else if (ts_stb) ts_rcv <= 1;
else if (rcv_last) ts_rcv <= 0;
if (!rcv) cntr <= 0;
if (!ts_rcv) cntr <= 0;
else cntr <= cntr + 1;
if (pre_snap) chn <= rq_enc;
// insert channel instead of the usec MSB, swap usec <-> sec
......
memctrl/memctrl16.v
View file @ bf7c096d
......@@ -1312,32 +1312,32 @@ always @ (posedge mclk) if (ext_buf_rd_late) begin
`endif
`ifdef def_enable_mem_chn10
`ifdef def_write_mem_chn10
4'h10:ext_buf_rdata <= ext_buf_rdata10;
4'ha:ext_buf_rdata <= ext_buf_rdata10;
`endif
`endif
`ifdef def_enable_mem_chn11
`ifdef def_write_mem_chn11
4'h11:ext_buf_rdata <= ext_buf_rdata11;
4'hb:ext_buf_rdata <= ext_buf_rdata11;
`endif
`endif
`ifdef def_enable_mem_chn12
`ifdef def_write_mem_chn12
4'h12:ext_buf_rdata <= ext_buf_rdata12;
4'hc:ext_buf_rdata <= ext_buf_rdata12;
`endif
`endif
`ifdef def_enable_mem_chn13
`ifdef def_write_mem_chn13
4'h13:ext_buf_rdata <= ext_buf_rdata13;
4'hd:ext_buf_rdata <= ext_buf_rdata13;
`endif
`endif
`ifdef def_enable_mem_chn14
`ifdef def_write_mem_chn14
4'h14:ext_buf_rdata <= ext_buf_rdata14;
4'he:ext_buf_rdata <= ext_buf_rdata14;
`endif
`endif
`ifdef def_enable_mem_chn15
`ifdef def_write_mem_chn15
4'h15:ext_buf_rdata <= ext_buf_rdata15;
4'hf:ext_buf_rdata <= ext_buf_rdata15;
`endif
`endif
default: ext_buf_rdata <= 'bx;
......
sensor/sensor_membuf.v
View file @ bf7c096d
......@@ -33,7 +33,7 @@ module sensor_membuf #(
input rpage_next, // advance to next page (and reset lower bits to 0)
input buf_rd, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] buf_dout, // data out
output reg page_written // buffer page (full or partial) is written to the memory buffer
output page_written // buffer page (full or partial) is written to the memory buffer
);
......
sensor/sensors393.v
View file @ bf7c096d
......@@ -189,41 +189,14 @@ module sensors393 #(
input status_start, // Acknowledge of the first status packet byte (address)
// I/O pads, pin names match circuit diagram (each sensor)
inout [7:0] sns1_dp,
inout [7:0] sns1_dn,
inout sns1_clkp,
inout sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
inout sns1_pg,
inout [7:0] sns2_dp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [7:0] sns2_dn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns2_clkp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns2_clkn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns2_scl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns2_sda, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns2_ctl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns2_pg, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [7:0] sns3_dp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [7:0] sns3_dn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns3_clkp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns3_clkn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns3_scl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns3_sda, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns3_ctl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns3_pg, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [7:0] sns4_dp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [7:0] sns4_dn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_clkp, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_clkn, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_scl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_sda, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_ctl, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout sns4_pg, //SuppressThisWarning VEditor : VDT bug? - assigned used in generate block only
inout [31:0] sns_dp,
inout [31:0] sns_dn,
inout [3:0] sns_clkp,
inout [3:0] sns_clkn,
inout [3:0] sns_scl,
inout [3:0] sns_sda,
inout [3:0] sns_ctl,
inout [3:0] sns_pg,
// Memory interface (4 channels)
input [3:0] rpage_set, // set internal read page to rpage_in (reset pointers)
......@@ -247,6 +220,8 @@ module sensors393 #(
input [NUM_FRAME_BITS-1:0] frame_num2,
input [NUM_FRAME_BITS-1:0] frame_num3,
output idelay_rdy, // need to connect outputs to prevent optimizing out
// S_AXI interface write only (histograms out)
// write address
input aclk, // global clock for S_AXI0 (150 MHz)
......@@ -275,9 +250,8 @@ module sensors393 #(
input [ 1:0] saxi_bresp // AXI PS Slave GP0 BRESP[1:0], output
);
wire [1:0] idelay_ctrl_rdy; // need to connect outputs to prevent optimizing out
assign idelay_rdy = &idelay_ctrl_rdy;
reg [7:0] cmd_ad;
reg cmd_stb;
wire [31:0] status_ad_chn;
......@@ -297,6 +271,8 @@ module sensors393 #(
cmd_ad <= cmd_ad_in;
cmd_stb <= cmd_stb_in;
end
// wire [3:0] sns_pg;
// my_alias #(.WIDTH(4)) my_alias_sns_pg_i ({sns4_pg,sns3_pg,sns2_pg,sns1_pg},sns_pg);
generate
genvar i;
......@@ -406,6 +382,7 @@ module sensors393 #(
.rst (rst), // input
.pclk (pclk), // input
.pclk2x (pclk2x), // input
/*
.sns_dp ((i & 2) ? ((i & 1) ? sns4_dp: sns3_dp): ((i & 1) ? sns2_dp: sns1_dp)), // inout[7:0]
.sns_dn ((i & 2) ? ((i & 1) ? sns4_dn: sns3_dn): ((i & 1) ? sns2_dn: sns1_dn)), // inout[7:0]
.sns_clkp ((i & 2) ? ((i & 1) ? sns4_clkp: sns3_clkp):((i & 1) ? sns2_clkp: sns1_clkp)), // inout
......@@ -413,8 +390,21 @@ module sensors393 #(
.sns_scl ((i & 2) ? ((i & 1) ? sns4_scl: sns3_scl): ((i & 1) ? sns2_scl: sns1_scl)), // inout
.sns_sda ((i & 2) ? ((i & 1) ? sns4_sda: sns3_sda): ((i & 1) ? sns2_sda: sns1_sda)), // inout
.sns_ctl ((i & 2) ? ((i & 1) ? sns4_ctl: sns3_ctl): ((i & 1) ? sns2_ctl: sns1_ctl)), // inout
.sns_pg ((i & 2) ? ((i & 1) ? sns4_pg: sns3_pg): ((i & 1) ? sns2_pg: sns1_pg)), // inout
// .sns_pg (sns_pg[i]), // inout
// .sns_pg ((i & 2) ? ((i & 1) ? sns4_pg: sns3_pg): ((i & 1) ? sns2_pg: sns1_pg)), // inout
// .sns_pg ({sns4_pg,sns3_pg,sns2_pg,sns1_pg}[i]), // inout
.sns_pg (sns_pg[i]), // inout
*/
.sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0]
.sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0]
.sns_clkp (sns_clkp[i]), // inout
.sns_clkn (sns_clkn[i]), // inout
.sns_scl (sns_scl[i]), // inout
.sns_sda (sns_sda[i]), // inout
.sns_ctl (sns_ctl[i]), // inout
.sns_pg (sns_pg[i]), // inout
.mclk (mclk), // input
.cmd_ad_in (cmd_ad), // input[7:0]
.cmd_stb_in (cmd_stb), // input
......@@ -538,13 +528,13 @@ module sensors393 #(
.rq_out (status_rq), // output
.start_out (status_start) // input
);
// TODO: connect idelay outputs to smth
idelay_ctrl# (
.IODELAY_GRP("IODELAY_SENSOR_12")
) idelay_ctrl_sensor12_i (
.refclk(ref_clk),
.rst(dly_rst), //rst || dly_rst
.rdy()
.rdy(idelay_ctrl_rdy[0])
);
idelay_ctrl# (
......@@ -552,8 +542,23 @@ module sensors393 #(
) idelay_ctrl_sensor34_i (
.refclk(ref_clk),
.rst(dly_rst), //rst || dly_rst
.rdy()
.rdy(idelay_ctrl_rdy[1])
);
endmodule
/*
module my_alias #(
parameter WIDTH = 1)
(
inout [WIDTH-1:0] a,
inout [WIDTH-1:0] a
);
module my_alias #(
parameter WIDTH = 1)
(.A(W), .B(W));
inout [WIDTH-1:0] W;
endmodule
*/
timing/camsync393.v
View file @ bf7c096d
......@@ -665,10 +665,10 @@ module camsync393 #(
assign {ts_rcv_stb_chn3, ts_rcv_stb_chn2, ts_rcv_stb_chn1, ts_rcv_stb_chn0}= ts_stb;
pulse_cross_clock i_start_to_pclk (.rst(1'b0), .src_clk(mclk), .dst_clk(pclk), .in_pulse(start_d && start_en), .out_pulse(start_to_pclk),.busy());
pulse_cross_clock i_ts_snap_mclk (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[0]), .out_pulse(ts_snap_triggered_mclk[0]),.busy());
pulse_cross_clock i_ts_snap_mclk (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[1]), .out_pulse(ts_snap_triggered_mclk[1]),.busy());
pulse_cross_clock i_ts_snap_mclk (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy());
pulse_cross_clock i_ts_snap_mclk (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy());
pulse_cross_clock i_ts_snap_mclk0 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[0]), .out_pulse(ts_snap_triggered_mclk[0]),.busy());
pulse_cross_clock i_ts_snap_mclk1 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[1]), .out_pulse(ts_snap_triggered_mclk[1]),.busy());
pulse_cross_clock i_ts_snap_mclk2 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[2]), .out_pulse(ts_snap_triggered_mclk[2]),.busy());
pulse_cross_clock i_ts_snap_mclk3 (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(ts_snap_triggered[3]), .out_pulse(ts_snap_triggered_mclk[3]),.busy());
pulse_cross_clock i_rcv_done_mclk (.rst(1'b0), .src_clk(pclk), .dst_clk(mclk), .in_pulse(rcv_done), .out_pulse(rcv_done_mclk),.busy());
......
timing/timestamp_fifo.v
View file @ bf7c096d
......@@ -51,14 +51,18 @@ module timestamp_fifo(
if (rst) wpntr <= 0;
else if (!rcv) wpntr <= {wpntr[3],3'b0};
else wpntr <= wpntr + 1;
end
always @ (posedge sclk) begin
if (rcv) fifo_ram[wpntr] <= din;
end
always @(posedge rst or posedge aclk) begin
if (rst) advance_r <= 0;
else advance_r <= {advance_r[0], advance};
end
always @(posedge aclk) begin
if (advance_r[0] && !advance_r[1]) rpntr[3] <= wpntr[3];
end
......@@ -70,7 +74,9 @@ module timestamp_fifo(
if (rst) rpntr[2:0] <= 0;
else if (!snd && !rstb) rpntr[2:0] <= 0;
else rpntr[2:0] <= rpntr[2:0] + 1;
end
always @(posedge rclk) begin
if (snd) dout <= fifo_ram[rpntr];
end
endmodule
......
util_modules/clocks393.v
View file @ bf7c096d
......@@ -101,7 +101,8 @@ module clocks393#(
output xclk, // global clock for compressor (now 100MHz)
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref // non-global, just RTC (currently just mclk/8 = 25 MHz)
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
input [1:0] extra_status // just extra two status bits from the top module
);
wire memclk;
wire ffclk0;
......@@ -127,7 +128,7 @@ module clocks393#(
if (rst) pwrdwn_clk <= 0;
if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4];
end
assign status_data = {test_clk, locked, 2'b0};
assign status_data = {test_clk, locked, extra_status};
always @ (posedge memclk or posedge memclk_rst) if (memclk_rst) test_clk[0] <= ~test_clk[0];
always @ (posedge ffclk0 or posedge ffclk0_rst) if (ffclk0_rst) test_clk[1] <= ~test_clk[1];
always @ (posedge ffclk1 or posedge ffclk1_rst) if (ffclk1_rst) test_clk[2] <= ~test_clk[2];
......
util_modules/gpio393.v
View file @ bf7c096d
......@@ -150,9 +150,6 @@ module gpio393 #(
.d_out (ds[i]), // output
.en_out (ds_en[i]) // output
);
end
iobuf #(
.DRIVE (GPIO_DRIVE),
.IBUF_LOW_PWR (GPIO_IBUF_LOW_PWR),
......@@ -164,6 +161,9 @@ module gpio393 #(
.I (io_do[i]), // input
.T (io_t[i]) // input
);
end
endgenerate
cmd_deser #(
......
util_modules/status_generate.v
View file @ bf7c096d
......@@ -68,9 +68,9 @@ module status_generate #(
end else begin
status_generate_only #(
.STATUS_REG_ADDR(7),
.PAYLOAD_BITS(15),
.REGISTER_STATUS(1)
.STATUS_REG_ADDR (STATUS_REG_ADDR),
.PAYLOAD_BITS (PAYLOAD_BITS),
.REGISTER_STATUS (REGISTER_STATUS)
) status_generate_only_i (
.rst (rst), // input
.clk (clk), // input
......
wrap/ibufds_ibufgds.v
View file @ bf7c096d
......@@ -53,6 +53,3 @@ module ibufds_ibufgds #(
endmodule
endmodule
wrap/ram18_var_w_var_r.v
View file @ bf7c096d
......@@ -474,6 +474,3 @@ module ram18_dummy
assign data_out=0;
endmodule
endmodule
x393.v
View file @ bf7c096d
......@@ -464,6 +464,7 @@ module x393 #(
wire [31:0] logger_data32;
wire logger_pre_valid_chn;
wire idelay_ctrl_rdy;// just to keep idelay_ctrl instances
assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
assign axird_dev_busy = 1'b0; // always for now
......@@ -1343,7 +1344,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
wire [ 5:0] saxi1_bid;
wire [ 1:0] saxi1_bresp;
sensors393 #(
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC),
......@@ -1464,6 +1464,17 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.status_ad (status_sensor_ad), // output[7:0]
.status_rq (status_sensor_rq), // output
.status_start (status_sensor_start), // input
.sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // inout[7:0]
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // inout[7:0]
.sns_clkp ({sns4_clkp, sns3_clkp, sns2_clkp, sns1_clkp}), // inout
.sns_clkn ({sns4_clkn, sns3_clkn, sns2_clkn, sns1_clkn}), // inout
.sns_scl ({sns4_scl, sns3_scl, sns2_scl, sns1_scl}), // inout
.sns_sda ({sns4_sda, sns3_sda, sns2_sda, sns1_sda}), // inout
.sns_ctl ({sns4_ctl, sns3_ctl, sns2_ctl, sns1_ctl}), // inout
.sns_pg ({sns4_pg, sns3_pg, sns2_pg, sns1_pg}), // inout
/*
.sns1_dp (sns1_dp), // inout[7:0]
.sns1_dn (sns1_dn), // inout[7:0]
.sns1_clkp (sns1_clkp), // inout
......@@ -1499,7 +1510,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.sns4_sda (sns4_sda), // inout
.sns4_ctl (sns4_ctl), // inout
.sns4_pg (sns4_pg), // inout
*/
.rpage_set (sens_rpage_set), // input
.rpage_next (sens_rpage_next), // input
.buf_rd (sens_buf_rd), // input
......@@ -1518,6 +1529,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.frame_num1 (frame_num[1 * NUM_FRAME_BITS +: NUM_FRAME_BITS]), // input[3:0]
.frame_num2 (frame_num[2 * NUM_FRAME_BITS +: NUM_FRAME_BITS]), // input[3:0]
.frame_num3 (frame_num[3 * NUM_FRAME_BITS +: NUM_FRAME_BITS]), // input[3:0]
.idelay_rdy (idelay_ctrl_rdy), // output[1:0] // just to preserve iodelay_cntr
.aclk (saxi0_aclk), // input
.saxi_awaddr (saxi0_awaddr), // output[31:0]
......@@ -2073,7 +2085,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.xclk (xclk), // output
.xclk2x (xclk2x), // output
.sync_clk (camsync_clk), // output
.time_ref (time_ref) // output
.time_ref (time_ref), // output
.extra_status ({1'b0,idelay_ctrl_rdy}) // input[1:0]
);
axibram_write #(
......
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