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Commit b732c0f0 authored by Andrey Filippov's avatar Andrey Filippov
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103993A, no DE deglitch, FPGA_VERSION = 32'h03934014

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fpga_version.vh
View file @ b732c0f0
......@@ -35,7 +35,11 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934010; // Boson640, for 103993A
parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
// parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases)
// parameter FPGA_VERSION = 32'h03934012; // Boson640, for 103993A, debugging 2 works, shifted by 1 pix hor (found bug)
// parameter FPGA_VERSION = 32'h03934011; // Boson640, for 103993A, debugging 1
// parameter FPGA_VERSION = 32'h03934010; // Boson640, for 103993A
// parameter FPGA_VERSION = 32'h03934006; // Boson640, adjusted initial phase to 70.5 degrees (47 counts)
// parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
......
includes/x393_parameters.vh
View file @ b732c0f0
......@@ -734,10 +734,14 @@
`endif
//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
`ifdef SIMULATION
parameter CLKFBOUT_PHASE_SENSOR = 54.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`ifdef BOSON_REVA
parameter CLKFBOUT_PHASE_SENSOR = 0.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`else
parameter CLKFBOUT_PHASE_SENSOR = 54.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`endif
`else
//It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 35.000] = 1.286
parameter CLKFBOUT_PHASE_SENSOR = 0.0, // 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKFBOUT_PHASE_SENSOR = 37.285714, // 360/(35*8)*29, // 37.2857 // 0.0, // 70.5, // -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`endif
parameter PCLK_PHASE = 0.000, // not used
parameter IPCLK1X_PHASE = 0.000, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
......
py393/x393_sensor.py
View file @ b732c0f0
......@@ -215,16 +215,16 @@ class X393Sensor(object):
elif (sensorType == SENSOR_INTERFACE_BOSON):
print (" drp_odd_bit = %d"%((status>> 0) & 0x01))
print (" drp_bit = %d"%((status>> 1) & 0x01))
print (" ps_out = 0x%x"%((status>> 0) & 0xff))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" perr = %d"%((status>> 9) & 1))
print (" test_bits = 0x%x"%((status>> 0) & 0xff))
print (" perr_now = %d"%((status>> 8) & 1))
print (" perr_persist %d"%((status>> 9) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
print (" recv_prgrs = %d"%((status>>14) & 1))
print (" recv_dav = %d"%((status>>15) & 1))
print (" recv_data = %d"%((status>>16) & 0xff))
print (" recv_data/numerr = %d"%((status>>16) & 0xff))
print (" senspgmin = %d"%((status>>24) & 1))
print (" xmit_busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
......@@ -616,7 +616,7 @@ class X393Sensor(object):
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param alt_status - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param alt_status - True: set status output to test pattern (should be 0xaa /0x17 for rev0 ), False: set to MMCM phase
@param test_pattern - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient
@param drp_cmd - DRP command di-bit: 0 - nop, 1 - shift 0, 2 - shift 1, 3 - execute command
@return sensor i/o control word
......@@ -1346,7 +1346,7 @@ class X393Sensor(object):
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param alt_status - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param alt_status - True: set status output to test pattern (should be 0xaa for RevA and 0x17 for Rev0), False: set to MMCM phase
@param test_pattern - 0..7 - 0 normal data, 1+ - test patterns (1 - LSB col//3. MSB row//3, 2 - horizontal gradient , 3 - vertical gradient
@param drp_cmd - DRP command di-bit: 0 - nop, 1 - shift 0, 2 - shift 1, 3 - execute command
"""
......@@ -1516,9 +1516,10 @@ class X393Sensor(object):
def set_sensor_io_dly_boson (self,
num_sensor,
mmcm_phase = None, #24 steps in 3ns period
lane0_dly = None,
lane1_dly = None,
lane2_dly = None):
lane0_dly = 0,
lane1_dly = 0,
lane2_dly = 0,
lane3_dly = 0):
"""
Set sensor port input delays and mmcm phase
@param num_sensor - sensor port number (0..3) or all, 'A'
......@@ -1526,6 +1527,7 @@ class X393Sensor(object):
@param lane0_dly - delay in the lane0 (3 LSB are not used) // All 4 lane delays should be set simultaneously
@param lane1_dly - delay in the lane1 (3 LSB are not used)
@param lane2_dly - delay in the lane2 (3 LSB are not used)
@param lane3_dly - delay in the lane3 (3 LSB are not used)
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1534,13 +1536,14 @@ class X393Sensor(object):
mmcm_phase = mmcm_phase,
lane0_dly = lane0_dly,
lane1_dly = lane1_dly,
lane2_dly = lane2_dly)
lane2_dly = lane2_dly,
lane3_dly = lane3_dly)
return
except:
pass
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS
try: # if any delay is None - do not set
dlys=(lane0_dly & 0xff) | ((lane1_dly & 0xff) << 8) | ((lane2_dly & 0xff) << 16)
dlys=(lane0_dly & 0xff) | ((lane1_dly & 0xff) << 8) | ((lane2_dly & 0xff) << 16) | ((lane3_dly & 0xff) << 24)
self.x393_axi_tasks.write_control_register(reg_addr + 2, dlys)
except:
return # do not apply delays
......@@ -1563,8 +1566,8 @@ class X393Sensor(object):
self.program_status_sensor_io(num_sensor, mode=1, seq_num=0)
status= self.get_status_sensor_io(num_sensor)
sign17 = status & 0xff
if sign17 != 0x17:
print("Signature: 0x%x (should be 0x17)"%(sign17,))
if (sign17 != 0x17) and (sign17 != 0xaa) :
print("Signature: 0x%x (should be 0x17 for rev0 and 0xaa for revA)"%(sign17,))
return (sign17, -1, 0)
nerr=0
ntry = 0
......@@ -1878,6 +1881,16 @@ uart_print_packet 0 False False
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = 3)
return data
def drp_read_all(self,
num_sensor):
"""
Read all defined DRP registers for MMCM/PLL
@param num_sensor - sensor port number (0..3)
"""
for addr in (0x6,0x7,0x8,0x9,0xa,0xa,0xb,0xc,0xd,0xe,0xf,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x18,0x19,0x1a,0x27,0x28,0x4e,0x4f):
d= self.drp_read_reg(num_sensor,addr)
print("0x%02x: 0x%04x"%(addr,d))
def drp_write_reg(self,
num_sensor,
addr,
......
sensor/sens_103993.v
View file @ b732c0f0
......@@ -305,7 +305,7 @@ module sens_103993 #(
test_patt? nonlock_persistent : clkin_pxd_stopped_mmcm, // 11
recv_odd_even, // clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
// test_patt? perr : ps_rdy, // 8
// test_patt? perr : ps_rdy, // 8
// test_patt? test_out[7:0]:ps_out[7:0],// [7:0]
perr, // 8
test_out[7:2], // [7:2]
......@@ -525,7 +525,7 @@ module sens_103993 #(
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD), // "DIFF_SSTL18_I")
.DEGLITCH_DVALID (1),
.DEGLITCH_DVALID (0), // 1),
.DEGLITCH_HSYNC (3),
.DEGLITCH_VSYNC (7)
) sens_103993_l3_i ( // same instance name
......
sensor/sens_103993A_lanes.v
View file @ b732c0f0
......@@ -108,6 +108,22 @@ module sens_103993A_lanes #(
output drp_bit,
output drp_odd_bit
);
/*
Lanes bits: 6 5 4 3 2 1 0
0 (TA) 1 0 d4 d3 d2 d1 d0 sns_d[ 6: 0]
1 (TB) 1 0 d9 d8 d7 d6 d5 sns_d[13: 7]
2 (TC) 1 0 d14 d13 d12 d11 d10 sns_d[20:14]
3 (TD) 1 0 0 de vs hs d15 sns_d[27:21]
0 (TA) 6 5 4 3 2 1 0 sns_d[ 6: 0]
1 (TB) 13 12 11 10 9 8 7 sns_d[13: 7]
2 (TC) 20 19 18 17 16 15 14 sns_d[20:14]
3 (TD) 27 26 25 24 23 22 21 sns_d[27:21]
perr_r <= ~sns_d[27] | sns_d[26] | sns_d[25] | ~sns_d[20] | sns_d[19] | ~sns_d[13] | sns_d[12] | ~sns_d[6] | sns_d[5];
*/
wire [NUMLANES * 7-1:0] sns_d;
wire ipclk2x;// re-generated clock (135 MHz)
......@@ -119,10 +135,10 @@ module sens_103993A_lanes #(
wire for_pclk;
wire for_pclk_last;
assign pxd_out = (DEGLITCH_DVALID>0) ? pxd_out_r: pxd_out_r2;
assign pxd_out = (DEGLITCH_DVALID == 0) ? pxd_out_r: pxd_out_r2;
assign perr = perr_r;
assign test_out = {sns_d[27:26],sns_d[20:19],sns_d[13:12],sns_d[6:5]}; // should be 8'haa
assign pxd_w = {sns_d[19:12],sns_d[9:2]};
assign pxd_w = {sns_d[21],sns_d[18:14],sns_d[11:7],sns_d[4:0]};
sens_103993A_clock #(
.SENS_BANDWIDTH (SENS_BANDWIDTH),
......@@ -218,7 +234,7 @@ module sens_103993A_lanes #(
always @(posedge pclk) begin
pxd_out_r <= pxd_w;
pxd_out_r2 <= pxd_out_r;
perr_r <= ~sns_d[27] | sns_d[26] | sns_d[25] | ~sns_d[20] | sns_d[19] | ~sns_d[13] | sns_d[13] | ~sns_d[6] | sns_d[5];
perr_r <= ~sns_d[27] | sns_d[26] | sns_d[25] | ~sns_d[20] | sns_d[19] | ~sns_d[13] | sns_d[12] | ~sns_d[6] | sns_d[5];
end
deglitch #(
......
x393_boson.bit
View file @ b732c0f0
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x393_boson.timing_summary_impl
View file @ b732c0f0
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x393_boson_utilization.report
View file @ b732c0f0
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Fri Apr 2 01:44:50 2021
| Date : Sun Apr 11 14:45:12 2021
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_boson_utilization.report
| Design : x393
......@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 43731 | 0 | 78600 | 55.64 |
| LUT as Logic | 40349 | 0 | 78600 | 51.33 |
| LUT as Memory | 3382 | 0 | 26600 | 12.71 |
| Slice LUTs | 43475 | 0 | 78600 | 55.31 |
| LUT as Logic | 40095 | 0 | 78600 | 51.01 |
| LUT as Memory | 3380 | 0 | 26600 | 12.71 |
| LUT as Distributed RAM | 2834 | 0 | | |
| LUT as Shift Register | 548 | 0 | | |
| Slice Registers | 55910 | 0 | 157200 | 35.57 |
| Register as Flip Flop | 55910 | 0 | 157200 | 35.57 |
| LUT as Shift Register | 546 | 0 | | |
| Slice Registers | 55965 | 0 | 157200 | 35.60 |
| Register as Flip Flop | 55965 | 0 | 157200 | 35.60 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
......@@ -59,7 +59,7 @@ Table of Contents
| 16 | Yes | - | Set |
| 676 | Yes | - | Reset |
| 1219 | Yes | Set | - |
| 53999 | Yes | Reset | - |
| 54054 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 17026 | 0 | 19650 | 86.65 |
| SLICEL | 11218 | 0 | | |
| SLICEM | 5808 | 0 | | |
| LUT as Logic | 40349 | 0 | 78600 | 51.33 |
| using O5 output only | 3 | | | |
| using O6 output only | 31464 | | | |
| using O5 and O6 | 8882 | | | |
| LUT as Memory | 3382 | 0 | 26600 | 12.71 |
| Slice | 17097 | 0 | 19650 | 87.01 |
| SLICEL | 11257 | 0 | | |
| SLICEM | 5840 | 0 | | |
| LUT as Logic | 40095 | 0 | 78600 | 51.01 |
| using O5 output only | 4 | | | |
| using O6 output only | 31207 | | | |
| using O5 and O6 | 8884 | | | |
| LUT as Memory | 3380 | 0 | 26600 | 12.71 |
| LUT as Distributed RAM | 2834 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2748 | | | |
| LUT as Shift Register | 548 | 0 | | |
| using O5 output only | 262 | | | |
| using O6 output only | 237 | | | |
| using O5 and O6 | 49 | | | |
| LUT Flip Flop Pairs | 25423 | 0 | 78600 | 32.34 |
| fully used LUT-FF pairs | 4862 | | | |
| LUT-FF pairs with one unused LUT output | 18383 | | | |
| LUT-FF pairs with one unused Flip Flop | 18136 | | | |
| Unique Control Sets | 5278 | | | |
| LUT as Shift Register | 546 | 0 | | |
| using O5 output only | 276 | | | |
| using O6 output only | 219 | | | |
| using O5 and O6 | 51 | | | |
| LUT Flip Flop Pairs | 25539 | 0 | 78600 | 32.49 |
| fully used LUT-FF pairs | 4875 | | | |
| LUT-FF pairs with one unused LUT output | 18503 | | | |
| LUT-FF pairs with one unused Flip Flop | 18221 | | | |
| Unique Control Sets | 4998 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
......@@ -197,12 +197,12 @@ Table of Contents
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 53999 | Flop & Latch |
| LUT3 | 11860 | LUT |
| LUT6 | 10460 | LUT |
| LUT2 | 8628 | LUT |
| LUT4 | 8367 | LUT |
| LUT5 | 8282 | LUT |
| FDRE | 54054 | Flop & Latch |
| LUT3 | 11826 | LUT |
| LUT6 | 10403 | LUT |
| LUT2 | 8591 | LUT |
| LUT4 | 8302 | LUT |
| LUT5 | 8223 | LUT |
| RAMD32 | 4174 | Distributed Memory |
| CARRY4 | 2805 | CarryLogic |
| LUT1 | 1634 | LUT |
......
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