merged with master

.eclipse_project_setup/.project

-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>x393</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.python.pydev.PyDevBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>com.elphel.vdt.veditor.simulateBuilder</name>
-			<arguments>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>
-					<value>echo &apos;Clean&apos;</value>
-				</dictionary>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>
-					<value>0</value>
-				</dictionary>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>
-					<value>echo &apos;No Build Configuration Specified&apos;</value>
-				</dictionary>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>
-					<value>Default</value>
-				</dictionary>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>
-					<value></value>
-				</dictionary>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>com.elphel.vdt.veditor.HdlNature</nature>
-		<nature>org.python.pydev.pythonNature</nature>
-	</natures>
-</projectDescription>

.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs

-cocotb_@_COCOTB_DEBUG=false
-cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v
-cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
-cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
-cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
-cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
-cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
-cocotb_@_GrepFindErr=error|ERROR
-cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
-cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
-cocotb_@_SaveLogsPreprocessor=true
-cocotb_@_SaveLogsSimulator=true
-com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->cocotb_@_PatternInfo<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->
-com.elphel.store.version.cocotb=0.8
-eclipse.preferences.version=1

.gitignore

@@ -49,17 +49,20 @@ x393_testbench03_01.sav
 simulation_data/*.dat
 simulation_data/*.jpeg
 #these two project files are now in .eclipse_project_setup directory
-.project
-.pydevproject
+/.project
+/.pydevproject
+/.settings
 #copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported
-workingSet.psf
+/workingSet.psf
 *.fst
 cocotb/Makefile
 cocotb/sim_build
 cocotb/results.xml
 *.directory
 html.tar.gz
-latex
-bitbake-logs                                                                                                                                               
-sysroots
-image
+/latex
+/bitbake-logs                                                                                                                                               
+/sysroots
+/image
+/scripts
+

.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
-FPGA_project_@_DUTTopModule=x393_dut
-FPGA_project_@_ImplementationTopFile=x393.v
-FPGA_project_@_SimulationTopFile=x393_testbench03.tf
-FPGA_project_@_SimulationTopModule=x393_testbench03
-FPGA_project_@_part=xc7z030fbg484-1
-com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
-com.elphel.store.version.FPGA_project=1.0
-eclipse.preferences.version=1

.settings/com.elphel.vdt.ISExst.prefs

-ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
-ISExst_@_constraints=ddrc_test01.xcf
-com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoBitstream.prefs

-VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
-VivadoBitstream_@_force=true
-VivadoBitstream_@_rawfile=x393_parallel
-com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoOpt.prefs

-VivadoOpt_@_SkipSnapshotOpt=true
-com.elphel.store.context.VivadoOpt=VivadoOpt_@_SkipSnapshotOpt<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoOptPhys.prefs

-VivadoOptPhys_@_SkipSnapshotOptPhys=true
-com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_@_SkipSnapshotOptPhys<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoOptPower.prefs

-VivadoOptPower_@_SkipSnapshotOptPower=true
-com.elphel.store.context.VivadoOptPower=VivadoOptPower_@_SkipSnapshotOptPower<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoPlace.prefs

-VivadoPlace_@_SkipSnapshotPlace=true
-VivadoPlace_@_verbose_place=true
-com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoRoute.prefs

-VivadoRoute_@_SkipSnapshotRoute=true
-VivadoRoute_@_directive_route=MoreGlobalIterations
-com.elphel.store.context.VivadoRoute=VivadoRoute_@_SkipSnapshotRoute<-@\#\#@->VivadoRoute_@_directive_route<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

-VivadoSynthesis_@_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
-VivadoSynthesis_@_MaxMsg=20000
-VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
-VivadoSynthesis_@_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
-VivadoSynthesis_@_ResetProject=true
-VivadoSynthesis_@_ShowInfo=true
-VivadoSynthesis_@_parser_mode=1
-VivadoSynthesis_@_verbose=true
-com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_PreTCL<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_ResetProject<-@\#\#@->
-com.elphel.store.version.VivadoSynthesis=1.1
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs

-VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
-com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs

-VivadoTimingReportImplemented_@_DisableVivadoTiming=true
-VivadoTimingReportImplemented_@_rawfile=
-com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_@_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs

-VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
-com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
-eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->
-com.elphel.store.version.iverilog=1.1
-eclipse.preferences.version=1
-iverilog_@_ExtraFiles=glbl.v<-@\#\#@->
-iverilog_@_GTKWaveSavFile=x393_testbench04.sav
-iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
-iverilog_@_SaveLogsPreprocessor=false
-iverilog_@_SaveLogsSimulator=true
-iverilog_@_ShowNoProblem=true
-iverilog_@_ShowWarnings=false
-iverilog_@_TopModulesOther=glbl<-@\#\#@->

.settings/com.elphel.vdt.prefs

-com.elphel.store.context.=com.elphel.vdt.PROJECT_DESING_MENU<-@\#\#@->
-com.elphel.vdt.PROJECT_DESING_MENU=MainDesignMenu
-eclipse.preferences.version=1

.settings/org.eclipse.core.resources.prefs

-eclipse.preferences.version=1
-encoding//attic/gen_hist_test.py=utf-8
-encoding//helpers/convert_data_to_params.py=utf-8
-encoding//helpers/convert_pass_init_params.py=utf-8
-encoding//helpers/convert_zigzag_rom.py=utf-8
-encoding//py393/test_mcntrl.py=utf-8
-encoding//py393/x393_i2c.py.test=utf-8
-encoding//py393/x393_init_usb_hub.py=utf-8

README.md

@@ -3,15 +3,15 @@ x393
 
 ![x393 Block Diagram](x393_diagram.png)
 
-FPGA code for Elphel 393 camera, created with [VDT plugin](https://github.com/Elphel/vdt-plugin). It runs on Xilinx Zynq 7030 SoC (FPGA plus dual ARM).
+FPGA code for Elphel 393 camera, created with [VDT plugin](https://git.elphel.com/Elphel/vdt-plugin). It runs on Xilinx Zynq 7030 SoC (FPGA plus dual ARM).
 
-[Documentation](http://docs.elphel.com/x393) is generated with Doxygen-based Doxverilog.
+[Documentation](https://docs.elphel.com/x393) is generated with Doxygen-based Doxverilog.
 
 Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproject files for Eclipse
 
 Simulation of this project requires some files from the Xilinx proprietary _unisims_ library (list of dependencies
-is in this [blog post](http://blog.elphel.com/2016/03/free-fpga-reimplement-the-primitives-models/)).
-[VDT plugin](https://github.com/Elphel/vdt-plugin) README file describes steps needed after installation of Xilinx software
+is in this [blog post](https://blog.elphel.com/2016/03/free-fpga-reimplement-the-primitives-models/)).
+[VDT plugin](https://git.elphel.com/Elphel/vdt-plugin) README file describes steps needed after installation of Xilinx software
 (unisims library is not distributed separately). 
 
 Python program used on the target and during Cocotb simulation requires Python numpy module, on Ubuntu you may

eclipse_project_setup/.project

+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>x393</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.python.pydev.PyDevBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.elphel.vdt.veditor.HdlNature</nature>
+		<nature>org.python.pydev.pythonNature</nature>
+	</natures>
+</projectDescription>

includes/ahci_defaults.vh

@@ -2,6 +2,6 @@
 , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
 , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
 , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
-, .INIT_0C (256'h000000000000000000000000000000000000000001010012001000000001FFFE)
+, .INIT_0C (256'h000000000000000000000000000000000000000001010013001000000001FFFE)
 , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
 , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)

includes/ahci_localparams.vh

@@ -97,7 +97,7 @@
 // RO: HBA Revision ID
     localparam PCI_Header__RID__RID__ADDR = 'h62;
     localparam PCI_Header__RID__RID__MASK = 'hff;
-    localparam PCI_Header__RID__RID__DFLT = 'h12;
+    localparam PCI_Header__RID__RID__DFLT = 'h13;
 // RO: Base Class Code: 1 - Mass Storage Device
     localparam PCI_Header__CC__BCC__ADDR = 'h62;
     localparam PCI_Header__CC__BCC__MASK = 'hff000000;

x393_sata/device/oob_dev.v

@@ -44,7 +44,10 @@
 // All references to doc = to SerialATA_Revision_2_6_Gold.pdf
 module oob_dev #(
     parameter DATA_BYTE_WIDTH = 4,
-    parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
+    parameter CLK_SPEED_GRADE = 2, // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
+    parameter TEST_ELIDLE =      2,      // test transmitting eidle between data rates (number of times)
+    parameter ELIDLE_DELAY =    'h28, // 80,    // counter cycles
+    parameter ELIDLE_DURATION = 'h80    // counter cycles
 )
 (
     // sata clk = usrclk2
@@ -83,15 +86,21 @@ localparam  STATE_CALIBRATE         = 4;
 localparam  STATE_COMWAKE           = 5;
 localparam  STATE_RECAL             = 55;
 localparam  STATE_SENDALIGN         = 6;
+localparam  STATE_EIDLE_RATE        = 65; 
 localparam  STATE_READY             = 7;
 localparam  STATE_PARTIAL           = 8;
 localparam  STATE_SLUMBER           = 9;
 localparam  STATE_REDUCESPEED       = 10;
 localparam  STATE_ERROR             = 11;
 
+
+reg     [31:0]  rate_change_cntr;
+reg             was_txelecidle;
 reg     [9:0]   state;
 wire    retry_interval_elapsed;
 wire    wait_interval_elapsed;
+wire    elidle_rate_delay_elapsed; 
+wire    elidle_rate_duration_elapsed; 
 wire    nocomwake;
 wire    [31:0]  align;
 wire    [31:0]  sync;
@@ -111,8 +120,20 @@ always @ (posedge clk)
 
 reg [31:0]  wait_timer;
 assign  wait_interval_elapsed =   wait_timer == 32'd4096;
+assign elidle_rate_delay_elapsed = wait_timer == ELIDLE_DELAY;
 always @ (posedge clk)
     wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1;
+reg [31:0] elidle_timer;
+assign elidle_rate_duration_elapsed = elidle_timer == ELIDLE_DURATION;    
+always @ (posedge clk)
+    elidle_timer <= rst | ~(state == STATE_EIDLE_RATE) ? 32'h0 : elidle_timer + 1'b1;
+
+always @ (posedge clk) begin
+    was_txelecidle <= txelecidle;
+    if (rst)                                rate_change_cntr <= 0;
+    else if (txelecidle && !was_txelecidle) rate_change_cntr <= rate_change_cntr + 1;  
+end
+
 
 reg [31:0]  data;
 reg [3:0]   isk;
@@ -218,6 +239,7 @@ always @ (posedge clk)
         end
         STATE_SENDALIGN:
         begin
+            txelecidle <= 1'b0;
             data    <= align;
             isk     <= 4'h1;
             if (aligndet)
@@ -225,9 +247,21 @@ always @ (posedge clk)
             else 
             if (wait_interval_elapsed)
                 state   <= STATE_ERROR;
+            else if ((rate_change_cntr < TEST_ELIDLE) && elidle_rate_delay_elapsed)
+                state   <= STATE_EIDLE_RATE;
             else 
                 state   <= STATE_SENDALIGN;
         end
+
+        STATE_EIDLE_RATE:
+        begin
+            txelecidle <= 1'b1;
+            data    <= 0; // align; // 'bz;
+            isk     <= 4'h1;
+            if (elidle_rate_duration_elapsed)
+                state   <= STATE_SENDALIGN;
+        end
+        
         STATE_READY:
         begin
             txelecidle <= 1'b0;

x393_sata/host/oob.v

@@ -223,7 +223,11 @@ always @ (posedge clk) begin
     else                         rxdlysreset_r <= rxdlysreset_r << 1; 
 end
 
-
+reg was_rxelecidle_waiting_reset;
+always @ (posedge clk) begin
+    if      (rst || set_wait_eidle)          was_rxelecidle_waiting_reset <= 0;
+    else if (state_wait_rxrst && rxelecidle) was_rxelecidle_waiting_reset <= 1;
+end
 assign  state_idle = ~state_wait_cominit &
                      ~state_wait_comwake &
                      ~state_wait_align &
@@ -253,11 +257,17 @@ end
 assign  set_wait_cominit   = state_idle & oob_start & ~cominit_req;
 assign  set_wait_comwake   = state_idle & cominit_req_l & cominit_allow & rxcominit_done | state_wait_cominit & rxcominitdet_l & rxcominit_done;
 assign  set_recal_tx       = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
-assign  set_wait_eidle     = state_recal_tx & recal_tx_done;
+///assign  set_wait_eidle     = state_recal_tx & recal_tx_done;
+assign  set_wait_eidle     = (state_recal_tx & recal_tx_done) |
+                             (rxelecidle & 
+                              (state_wait_align | state_wait_clk_align | state_wait_align2 | (state_wait_rxrst & rxreset_ack & was_rxelecidle_waiting_reset) ));
 assign  set_wait_rxrst     = state_wait_eidle & eidle_timer_done;
-assign  set_wait_align     = state_wait_rxrst & rxreset_ack;
-assign  set_wait_clk_align = state_wait_align & (detected_alignp_r);
-assign  set_wait_align2    = state_wait_clk_align & clk_phase_align_ack;
+///assign  set_wait_align     = state_wait_rxrst & rxreset_ack;
+///assign  set_wait_clk_align = state_wait_align & (detected_alignp_r);
+///assign  set_wait_align2    = state_wait_clk_align & clk_phase_align_ack;
+assign  set_wait_align     = state_wait_rxrst & rxreset_ack & ~rxelecidle;
+assign  set_wait_clk_align = state_wait_align & (detected_alignp_r) & ~rxelecidle;
+assign  set_wait_align2    = state_wait_clk_align & clk_phase_align_ack & ~rxelecidle;
 
 
 
@@ -278,10 +288,18 @@ assign  clr_wait_cominit   = set_wait_comwake   | set_error;
 assign  clr_wait_comwake   = set_recal_tx       | set_error;
 assign  clr_recal_tx       = set_wait_eidle     | set_error;
 assign  clr_wait_eidle     = set_wait_rxrst     | set_error;
-assign  clr_wait_rxrst     = set_wait_align     | set_error;
-assign  clr_wait_align     = set_wait_clk_align | set_error;
-assign  clr_wait_clk_align = set_wait_align2    | set_error;
-assign  clr_wait_align2    = set_wait_synp      | set_error;
+///assign  clr_wait_rxrst     = set_wait_align     | set_error;
+assign  clr_wait_rxrst     = state_wait_rxrst & rxreset_ack; 
+
+///assign  clr_wait_align     = set_wait_clk_align | set_error;
+///assign  clr_wait_clk_align = set_wait_align2    | set_error;
+///assign  clr_wait_align2    = set_wait_synp      | set_error;
+assign  clr_wait_align     = set_wait_clk_align | set_error | rxelecidle;
+assign  clr_wait_clk_align = set_wait_align2    | set_error | rxelecidle;
+assign  clr_wait_align2    = set_wait_synp      | set_error | rxelecidle;
+
+
+
 assign  clr_wait_synp      = set_wait_linkup    | set_error;
 assign  clr_wait_linkup    = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
 assign  clr_error          = state_error;