Commit b406a02c authored by Andrey Filippov's avatar Andrey Filippov
Browse files

merged with master

parents 3b76078a 1bdf877a

.eclipse_project_setup/.project

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<?xml version="1.0" encoding="UTF-8"?>

<projectDescription>

	<name>x393</name>

	<comment></comment>

	<projects>

	</projects>

	<buildSpec>

		<buildCommand>

			<name>org.python.pydev.PyDevBuilder</name>

			<arguments>

			</arguments>

		</buildCommand>

		<buildCommand>

			<name>com.elphel.vdt.veditor.simulateBuilder</name>

			<arguments>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.CleanCommand</key>

					<value>echo &apos;Clean&apos;</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.buildOrder</key>

					<value>0</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.command</key>

					<value>echo &apos;No Build Configuration Specified&apos;</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.enable</key>

					<value>true</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.name</key>

					<value>Default</value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.parser</key>

					<value></value>

				</dictionary>

				<dictionary>

					<key>com.elphel.vdt.veditor.simulateBuilder.00000000Default.workFolder</key>

					<value></value>

				</dictionary>

			</arguments>

		</buildCommand>

	</buildSpec>

	<natures>

		<nature>com.elphel.vdt.veditor.HdlNature</nature>

		<nature>org.python.pydev.pythonNature</nature>

	</natures>

</projectDescription>

.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs

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cocotb_@_COCOTB_DEBUG=false

cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v

cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->

cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->

cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->

cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->

cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav

cocotb_@_GrepFindErr=error|ERROR

cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING

cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)

cocotb_@_SaveLogsPreprocessor=true

cocotb_@_SaveLogsSimulator=true

com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->cocotb_@_PatternInfo<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->

com.elphel.store.version.cocotb=0.8

eclipse.preferences.version=1

.gitignore

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@@ -49,17 +49,20 @@ x393_testbench03_01.sav 
simulation_data/*.dat

simulation_data/*.dat

simulation_data/*.jpeg

simulation_data/*.jpeg

#these two project files are now in .eclipse_project_setup directory

#these two project files are now in .eclipse_project_setup directory

.project

/.project

.pydevproject

/.pydevproject

/.settings

#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported

#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported

workingSet.psf

/workingSet.psf

*.fst

*.fst

cocotb/Makefile

cocotb/Makefile

cocotb/sim_build

cocotb/sim_build

cocotb/results.xml

cocotb/results.xml

*.directory

*.directory

html.tar.gz

html.tar.gz

latex

/latex

bitbake-logs                                                                                                                                               

/bitbake-logs                                                                                                                                               

sysroots

/sysroots

image
 
/image

/scripts

.settings/com.elphel.vdt.FPGA_project.prefs

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FPGA_project_@_DUTTopFile=cocotb/x393_dut.v

FPGA_project_@_DUTTopModule=x393_dut

FPGA_project_@_ImplementationTopFile=x393.v

FPGA_project_@_SimulationTopFile=x393_testbench03.tf

FPGA_project_@_SimulationTopModule=x393_testbench03

FPGA_project_@_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->

com.elphel.store.version.FPGA_project=1.0

eclipse.preferences.version=1

.settings/com.elphel.vdt.ISExst.prefs

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ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->

ISExst_@_constraints=ddrc_test01.xcf

com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->

eclipse.preferences.version=1