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Commit ad1c2b04 authored by Andrey Filippov's avatar Andrey Filippov
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103993-rev0 with DRP MMCM/PLL control

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fpga_version.vh
View file @ ad1c2b04
......@@ -35,7 +35,12 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934001; // Boson640, adding camsync trigger decimation // git commit
parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
// parameter FPGA_VERSION = 32'h03934004; // Boson640, implementing DRP to control MMCME2/PLLE2
// parameter FPGA_VERSION = 32'h03934003; // Boson640, mitigating LVDS errors
// parameter FPGA_VERSION = 32'h03934002; // Boson640, mitigating LVDS errors
// parameter FPGA_VERSION = 32'h03934001; // Boson640, adding camsync trigger decimation // git commit
///parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - debugging // git commit
// parameter FPGA_VERSION = 32'h03931002; // parallel, adding camsync trigger decimation
// parameter FPGA_VERSION = 32'h03931001; // parallel, fixing delays // git commit
......
includes/x393_parameters.vh
View file @ ad1c2b04
This diff is collapsed.
py393/vrlg.py
View file @ ad1c2b04
......@@ -187,6 +187,30 @@ BUF_CLK1X_PCLK2X__RAW = str
BUF_CLK1X_PCLK2X__TYPE = str
BUF_CLK1X_PCLK__RAW = str
BUF_CLK1X_PCLK__TYPE = str
BUF_CLK_FB_SENS0 = str
BUF_CLK_FB_SENS0__RAW = str
BUF_CLK_FB_SENS0__TYPE = str
BUF_CLK_FB_SENS1 = str
BUF_CLK_FB_SENS1__RAW = str
BUF_CLK_FB_SENS1__TYPE = str
BUF_CLK_FB_SENS2 = str
BUF_CLK_FB_SENS2__RAW = str
BUF_CLK_FB_SENS2__TYPE = str
BUF_CLK_FB_SENS3 = str
BUF_CLK_FB_SENS3__RAW = str
BUF_CLK_FB_SENS3__TYPE = str
BUF_IPCLK1X_SENS0 = str
BUF_IPCLK1X_SENS0__RAW = str
BUF_IPCLK1X_SENS0__TYPE = str
BUF_IPCLK1X_SENS1 = str
BUF_IPCLK1X_SENS1__RAW = str
BUF_IPCLK1X_SENS1__TYPE = str
BUF_IPCLK1X_SENS2 = str
BUF_IPCLK1X_SENS2__RAW = str
BUF_IPCLK1X_SENS2__TYPE = str
BUF_IPCLK1X_SENS3 = str
BUF_IPCLK1X_SENS3__RAW = str
BUF_IPCLK1X_SENS3__TYPE = str
BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS0__RAW = str
BUF_IPCLK2X_SENS0__TYPE = str
......@@ -199,18 +223,18 @@ BUF_IPCLK2X_SENS2__TYPE = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS3__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS0__RAW = str
BUF_IPCLK_SENS0__TYPE = str
BUF_IPCLK_SENS1 = str
BUF_IPCLK_SENS1__RAW = str
BUF_IPCLK_SENS1__TYPE = str
BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS2__RAW = str
BUF_IPCLK_SENS2__TYPE = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS3__RAW = str
BUF_IPCLK_SENS3__TYPE = str
BUF_PCLK_SENS0 = str
BUF_PCLK_SENS0__RAW = str
BUF_PCLK_SENS0__TYPE = str
BUF_PCLK_SENS1 = str
BUF_PCLK_SENS1__RAW = str
BUF_PCLK_SENS1__TYPE = str
BUF_PCLK_SENS2 = str
BUF_PCLK_SENS2__RAW = str
BUF_PCLK_SENS2__TYPE = str
BUF_PCLK_SENS3 = str
BUF_PCLK_SENS3__RAW = str
BUF_PCLK_SENS3__TYPE = str
CAMSYNC_ADDR = int
CAMSYNC_ADDR__RAW = str
CAMSYNC_ADDR__TYPE = str
......@@ -1015,12 +1039,12 @@ IDELAY_VALUE__TYPE = str
INITIALIZE_OFFSET = int
INITIALIZE_OFFSET__RAW = str
INITIALIZE_OFFSET__TYPE = str
IPCLK1X_PHASE = float
IPCLK1X_PHASE__RAW = str
IPCLK1X_PHASE__TYPE = str
IPCLK2X_PHASE = float
IPCLK2X_PHASE__RAW = str
IPCLK2X_PHASE__TYPE = str
IPCLK_PHASE = float
IPCLK_PHASE__RAW = str
IPCLK_PHASE__TYPE = str
LAST_BUF_FRAME = int
LAST_BUF_FRAME__RAW = str
LAST_BUF_FRAME__TYPE = str
......@@ -1828,6 +1852,9 @@ NUM_INTERRUPTS__TYPE = str
NUM_XFER_BITS = int
NUM_XFER_BITS__RAW = str
NUM_XFER_BITS__TYPE = str
PCLK_PHASE = float
PCLK_PHASE__RAW = str
PCLK_PHASE__TYPE = str
PHASE_CLK2X_PCLK = float
PHASE_CLK2X_PCLK__RAW = str
PHASE_CLK2X_PCLK__TYPE = str
......@@ -2176,6 +2203,9 @@ SENS_CTRL_ARO__TYPE = str
SENS_CTRL_ARST = int
SENS_CTRL_ARST__RAW = str
SENS_CTRL_ARST__TYPE = str
SENS_CTRL_DPR = int
SENS_CTRL_DPR__RAW = str
SENS_CTRL_DPR__TYPE = str
SENS_CTRL_EXT_CLK = int
SENS_CTRL_EXT_CLK__RAW = str
SENS_CTRL_EXT_CLK__TYPE = str
......
py393/x393_sens_cmprs.py
View file @ ad1c2b04
......@@ -935,16 +935,21 @@ class X393SensCmprs(object):
bits16 = bits16) #False)
if sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
skip_frames = 70 # 65 < min <70. 70 shows 4 frames, 100 shows 35 frames over uart
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (skip_frames): # 65): #70): #80): #100): # 60 10 2
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
timeout = 5.0) # 2.0)
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number (after skip to make sure Boson is in booted state before UART commands) = %d"%(fn))
if not self.DRY_MODE:
skip_frames = 70 # 65 < min <70. 70 shows 4 frames, 100 shows 35 frames over uart
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (skip_frames): # 65): #70): #80): #100): # 60 10 2
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
timeout = 5.0) # 2.0)
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number (after skip to make sure Boson is in booted state before UART commands) = %d"%(fn))
else:
print ("No frame skipping for Boson in simulated mode")
if verbose >0 :
print ("===================== CMPRS_EN_ARBIT =========================")
......
py393/x393_sensor.py
View file @ ad1c2b04
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sensor/sens_103993.v
View file @ ad1c2b04
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sensor/sens_103993_clock.v
View file @ ad1c2b04
......@@ -46,9 +46,12 @@ module sens_103993_clock#(
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000, // dummy here
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK1X = "BUFR", // not used here
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_CLK_FB = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -91,7 +94,7 @@ module sens_103993_clock#(
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
localparam BUF_CLK_FB = BUF_IPCLK2X;
// localparam BUF_CLK_FB = BUF_IPCLK2X;
wire pclk_pre;
wire ipclk2x_pre; // output
wire clk_fb_pre;
......@@ -218,6 +221,7 @@ module sens_103993_clock#(
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT2_PHASE (IPCLK1X_PHASE), // not used here
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT1_USE_FINE_PS ("FALSE"), //"TRUE"),
......@@ -272,6 +276,7 @@ module sens_103993_clock#(
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT2_PHASE (IPCLK1X_PHASE), // not used here
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.REF_JITTER1 (SENS_REF_JITTER1),
......@@ -328,6 +333,10 @@ module sens_103993_clock#(
else assign pclk = pclk_pre;
endgenerate
generate
if (BUF_IPCLK1X == "BUFG") begin // not used here
end
endgenerate
endmodule
......
sensor/sens_103993_clock_25.v 0 → 100644
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sensor/sens_103993_l3.v
View file @ ad1c2b04
......@@ -50,9 +50,12 @@ module sens_103993_l3#(
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK1X = "BUFR", // not used here
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_CLK_FB = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -71,9 +74,13 @@ module sens_103993_l3#(
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter DEGLITCH_DVALID = 1,
parameter DEGLITCH_HSYNC = 3,
parameter DEGLITCH_VSYNC = 7
)(
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
input prsts,
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
......@@ -104,18 +111,21 @@ module sens_103993_l3#(
wire ipclk2x;// re-generated HiSPi clock (270 MHa) 330 MHz)
wire [NUMLANES * 10-1:0] sns_d;
reg [15:0] pxd_out_r;
reg vsync_r;
reg hsync_r;
reg dvalid_r;
reg [15:0] pxd_out_r2;
// reg vsync_r;
// reg hsync_r;
// reg dvalid_r;
reg perr_r;
reg cp_r;
wire [15:0] pxd_w;
assign pxd_out = pxd_out_r;
assign vsync = vsync_r;
assign hsync = hsync_r;
assign dvalid = dvalid_r;
assign pxd_out = (DEGLITCH_DVALID>0)? pxd_out_r: pxd_out_r2;
// assign vsync = vsync_r;
// assign hsync = hsync_r;
// assign dvalid = dvalid_r;
assign perr = perr_r;
assign test_out = sns_d[29:22];
assign pxd_w = {sns_d[19:12],sns_d[9:2]};
sens_103993_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -124,9 +134,12 @@ module sens_103993_l3#(
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (PCLK_PHASE),
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_PCLK),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.BUF_CLK_FB (BUF_CLK_FB),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
......@@ -143,6 +156,7 @@ module sens_103993_l3#(
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
......@@ -195,14 +209,41 @@ module sens_103993_l3#(
.dout (sns_d) // output[29:0]
);
always @(posedge pclk) begin
pxd_out_r <= {sns_d[19:12],sns_d[9:2]};
vsync_r <= sns_d[1]; // input - active high
hsync_r <= sns_d[11]; // input - active high
dvalid_r <= sns_d[21]; // input - active hight
pxd_out_r <= pxd_w;
pxd_out_r2 <= pxd_out_r;
// vsync_r <= sns_d[1]; // input - active high
// hsync_r <= sns_d[11]; // input - active high
// dvalid_r <= sns_d[21]; // input - active hight
cp_r <= sns_d[0];
// perr_r <= ~ cp_r ^ (^pxd_out_r) ^ vsync_r ^ hsync_r ^ dvalid_r;
perr_r <= ~ (^sns_d[9:0]) ^ (^sns_d[19:11]) ^ (^sns_d[29:21]); //DS: XOR of all selected bits result in odd parity
end
deglitch #(
.CLOCKS(DEGLITCH_DVALID)
) deglitch_dvalid_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[21]), // input
.q(dvalid) // output
);
deglitch #(
.CLOCKS(DEGLITCH_HSYNC)
) deglitch_hsync_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[11]), // input
.q(hsync) // output
);
deglitch #(
.CLOCKS(DEGLITCH_VSYNC)
) deglitch_vsync_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[1]), // input
.q(vsync) // output
);
endmodule
sensor/sens_103993_lane.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> sens_103993_lane
* @file sens_103993_lane.v
* @date 2021-03-26
* @author eyesis
*
* @brief
*
* @copyright Copyright (c) 2021 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993_lane.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_lane.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_lane#(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
// parameter NUMLANES = 3,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input ld_idelay, // mclk synchronous load idelay value
input apply_idelay, // mclk synchronous set idealy value
input pclk, // 27 MHz
input ipclk2x, // 135 MHz
input ipclk1x, // 67.5 MHz
input rst, // reset// @posedge iclk
input for_pclk, // copy 10 bits form ipclk1x domain to pclk (alternating 2/3 iplck1x intervals)
input for_pclk_early, // valid with copy_to_pclk, 10 bits contain early data from 12 bits (per lane)
input din_p,
input din_n,
output [9:0] dout);
wire din;
wire din_dly;
wire [3:0] deser_w; // deserializer 4-bit output
reg [7:0] deser_r;
reg [9:0] dout_r;
reg [9:0] pre_dout_r;
assign dout=dout_r;
generate
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "40") begin
ibufds_ibufgds_40 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "50") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // inputpre_dout_r
);
end else if (LVDS_UNTUNED_SPLIT == "60") begin
ibufds_ibufgds_60 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end
endgenerate
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (apply_idelay),
.ld (ld_idelay),
.delay (dly_data[7:3]),
.data_in (din),
.data_out (din_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN ("FALSE"),
.MSB_FIRST (1) // MSB is received first
) iserdes_pxd_i (
.iclk (ipclk2x), // source-synchronous clock
.oclk (ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div (ipclk1x), // oclk divided by 2, front aligned
.inv_clk_div (1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst (rst), // reset
.d_direct (1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly (din_dly), // serial input from idelay
.dout (deser_w), // parallel data out
.comb_out() // output
);
always @ (posedge ipclk1x) begin
deser_r <= {deser_r[3:0],deser_w[3:0]};
// if (for_pclk) pre_dout_r <= for_pclk_early ? {deser_w[1:0],deser_r[7:0]} : {deser_w[3:0],deser_r[7:2]};
if (for_pclk) pre_dout_r <= for_pclk_early ? {deser_r[7:0],deser_w[3:2]} : {deser_r[5:0],deser_w[3:0]};
end
always @ (posedge pclk) begin
dout_r <= pre_dout_r;
end
endmodule
sensor/sens_103993_lanes.v 0 → 100644
View file @ ad1c2b04
This diff is collapsed.
sensor/sensor_channel.v
View file @ ad1c2b04
......@@ -213,6 +213,7 @@ module sensor_channel#(
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_CTRL_DPR= 30, // 30:31 DRP command
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
......@@ -373,7 +374,8 @@ module sensor_channel#(
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
// parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -381,8 +383,8 @@ module sensor_channel#(
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
//IPCLK* will be used as PCLK*
parameter IPCLK_PHASE = 0.000,
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -390,15 +392,20 @@ module sensor_channel#(
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
// parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`ifdef LWIR
`else // all but LWIR
parameter BUF_IPCLK = "BUFR",
`else // all but LWIR
`ifdef BOSON
parameter BUF_PCLK = "BUFR",
parameter BUF_CLK_FB = "BUFR",
`endif
parameter BUF_IPCLK1X = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -1121,9 +1128,9 @@ module sensor_channel#(
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......@@ -1205,6 +1212,7 @@ module sensor_channel#(
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_CTRL_DPR (SENS_CTRL_DPR),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
......@@ -1224,14 +1232,17 @@ module sensor_channel#(
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
// .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (IPCLK_PHASE), // use IPCLK* for PCLK*
.PCLK_PHASE (PCLK_PHASE),
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_IPCLK), // use IPCLK* for PCLK*
.BUF_PCLK (BUF_PCLK),
.BUF_CLK_FB (BUF_CLK_FB),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......@@ -1469,10 +1480,10 @@ module sensor_channel#(
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......
sensor/sensors393.v
View file @ ad1c2b04
......@@ -184,7 +184,6 @@ module sensors393 #(
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
......@@ -195,6 +194,7 @@ module sensors393 #(
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_CTRL_DPR= 30, // 30:31 DRP command
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
......@@ -377,7 +377,7 @@ module sensors393 #(
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -385,7 +385,8 @@ module sensors393 #(
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -393,7 +394,7 @@ module sensors393 #(
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
......@@ -401,13 +402,23 @@ module sensors393 #(
`ifdef LWIR
`else
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
`ifdef BOSON
parameter BUF_PCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_PCLK_SENS1 = "BUFR", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS1 = "BUFR", // "BUFR",
parameter BUF_PCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_PCLK_SENS3 = "BUFR", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS3 = "BUFR", // "BUFR",
`endif
parameter BUF_IPCLK1X_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK1X_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK1X_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK1X_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -794,6 +805,7 @@ module sensors393 #(
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_CTRL_DPR (SENS_CTRL_DPR),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
......@@ -943,13 +955,20 @@ module sensors393 #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
`ifdef BOSON
.PCLK_PHASE (PCLK_PHASE),
`endif
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK ((i & 2) ? ((i & 1) ? BUF_IPCLK_SENS3 : BUF_IPCLK_SENS2) : ((i & 1) ?BUF_IPCLK_SENS1 :BUF_IPCLK_SENS0 )),
.BUF_IPCLK2X ((i & 2) ? ((i & 1) ? BUF_IPCLK2X_SENS3 : BUF_IPCLK2X_SENS2) : ((i & 1) ?BUF_IPCLK2X_SENS1 :BUF_IPCLK2X_SENS0 )),
`ifdef BOSON
.BUF_PCLK ((i & 2) ? ((i & 1) ? BUF_PCLK_SENS3: BUF_PCLK_SENS2): ((i & 1) ?BUF_PCLK_SENS1: BUF_PCLK_SENS0)),
.BUF_CLK_FB ((i & 2) ? ((i & 1) ? BUF_CLK_FB_SENS3: BUF_CLK_FB_SENS2): ((i & 1) ?BUF_CLK_FB_SENS1: BUF_CLK_FB_SENS0)),
`endif
.BUF_IPCLK1X ((i & 2) ? ((i & 1) ? BUF_IPCLK1X_SENS3:BUF_IPCLK1X_SENS2):((i & 1) ?BUF_IPCLK1X_SENS1:BUF_IPCLK1X_SENS0)),
.BUF_IPCLK2X ((i & 2) ? ((i & 1) ? BUF_IPCLK2X_SENS3:BUF_IPCLK2X_SENS2):((i & 1) ?BUF_IPCLK2X_SENS1:BUF_IPCLK2X_SENS0)),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
......
util_modules/deglitch.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> deglitch
* @file deglitch.v
* @date 2021-03-24
* @author Andrey Filippov
*
* @brief Deglitch signal
*
* @copyright Copyright (c) 2021
*
* <b>License </b>
*
* deglitch.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* deglitch.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module deglitch #(
parameter CLOCKS = 1
)(
input clk,
input rst,
input d,
output q
);
localparam WIDTH = clogb2(CLOCKS + 1);
reg q_r;
assign q = q_r;
generate
if (CLOCKS == 0) begin
always @ (posedge clk) begin
if (rst) q_r <= 0;
else q_r <= d;
end
end else begin
reg [WIDTH-1:0] cntr;
always @ (posedge clk) begin
if (rst) q_r <= 0;
else if (cntr == 0) q_r <= d;
if (rst || (d == q_r) || (cntr == 0)) cntr <= CLOCKS;
else cntr <= cntr -1;
end
end
endgenerate
function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
endmodule
util_modules/drp_mmcm_pll.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> drp_mmcm_pll
* @file drp_mmcm_pll.v
* @date 2021-03-29
* @author eyesis
*
* @brief MMCME2/PLLE2 DRP control
*
* @copyright Copyright (c) 2021 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* drp_mmcm_pll.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* drp_mmcm_pll.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
/*
Read operation:
Shift 7 address bits (may ignore responses, just maintain expected out_odd_bit), big endian (MSB first)
Send "execute" (after 7 bits)
Wait for flipping of out_odd_bit (out_bit will not change, ignore it)
read 16 bit of data by
- shifting 0 (or 1);
- waiting for flipping of out_odd_bit
- reading out_bit (big endian, MSB first)
issue "execute" - will just reset state machine to inoitial state (as there were 16 - not 7 or 23 bits)
Write operation
Shift 7 address bits and 16 data bits (23 total) (may ignore responses, just maintain expected out_odd_bit), big endian (MSB first)
Send execute (after 23 bits)
- waiting for flipping of out_odd_bit (in response to the 24 bit sent), out_bit will not change, ignore it
Use mclk as DCLK
*/
module drp_mmcm_pll#(
parameter DRP_ADDRESS_LENGTH = 7,
parameter DRP_DATA_LENGTH = 16
)(
// host interface
input dclk,
input mmcm_rst, // this module is reset by mmcm_rst=0
input [1:0] cmd, // 0 - NOP, 1 - shift 0, 2 - shift 1, 3 - execute
output out_bit, // output data ( ready after execute, data bit after shift 0/shift 1
output out_odd_bit, // alternates when new out_bit is available
// mmcme2/plle2 interface
output [DRP_ADDRESS_LENGTH-1:0] daddr,
output [DRP_DATA_LENGTH-1:0] di_drp,
input [DRP_DATA_LENGTH-1:0] do_drp,
input drdy, // single pulse!
output den,
output dwe
);
localparam DRP_FULL_LENGTH = DRP_ADDRESS_LENGTH + DRP_DATA_LENGTH;
reg out_odd_bit_r = 0;
reg [4:0] bit_cntr;
reg [1:0] cmd_r;
reg [DRP_FULL_LENGTH-1:0] sr;
reg [DRP_ADDRESS_LENGTH-1:0] daddr_r;
wire shift0_w;
wire shift1_w;
wire shift_w;
wire exec_w;
wire exec_wr_w;
wire exec_rd_w;
wire exec_nop_w;
reg exec_wr_r;
reg exec_rd_r;
reg den_r;
reg dwe_r;
// reg [1:0] den_r2;
reg drdy_r;
wire busy_w;
reg [1:0] rdy_r;
wire done; // single-clock rd/wr over
reg nxt_bit_r;
reg was_read;
assign out_odd_bit = out_odd_bit_r;
assign out_bit = sr[DRP_FULL_LENGTH-1];
assign daddr = daddr_r;
assign den = den_r;
assign dwe = dwe_r;
assign shift0_w = (cmd_r == 1);
assign shift1_w = (cmd_r == 2);
assign shift_w = shift0_w || shift1_w;
assign exec_w = (cmd_r == 3);
assign exec_wr_w = exec_w && (bit_cntr == 23);
assign exec_rd_w = exec_w && (bit_cntr == 7);
assign exec_nop_w = exec_w && (bit_cntr != 23) && (bit_cntr != 7);
assign di_drp = sr[DRP_DATA_LENGTH-1:0];
assign busy_w = !mmcm_rst || exec_wr_w || exec_rd_w || exec_wr_r || exec_rd_r || den_r; // || (|den_r2);
assign done = rdy_r[0] && !rdy_r[1];
always @ (posedge dclk) begin
exec_wr_r <= mmcm_rst && exec_wr_w;
exec_rd_r <= mmcm_rst && exec_rd_w;
if (!mmcm_rst) cmd_r <= 0;
else cmd_r <= cmd;
if (!mmcm_rst || exec_w) bit_cntr <= 0;
else if (shift_w) bit_cntr <= bit_cntr + 1;
if (!mmcm_rst) out_odd_bit_r <= 0;
else if (nxt_bit_r) out_odd_bit_r <= !out_odd_bit_r;
if (exec_wr_w) daddr_r <= sr[22:16];
else if (exec_rd_w) daddr_r <= sr[6:0];
den_r <= mmcm_rst && (exec_wr_r || exec_rd_r);
// den_r2 <= {den_r2[0], den_r};
dwe_r <= mmcm_rst && exec_wr_r;
drdy_r <= drdy;
rdy_r <= {rdy_r[0], ~busy_w & (drdy_r | rdy_r[0])};
nxt_bit_r <= mmcm_rst && (shift_w || exec_nop_w || done);
if (exec_wr_r) was_read <= 0;
else if (exec_rd_r) was_read <= 1;
if (shift_w) sr[DRP_FULL_LENGTH-1:0] <= {sr[DRP_FULL_LENGTH-2:0], shift1_w};
else if (was_read && done) sr[DRP_FULL_LENGTH-1:0] <= {do_drp, sr[DRP_ADDRESS_LENGTH-1:0]}; // keep lower bits
end
endmodule
wrap/mmcm_drp.v 0 → 100644
View file @ ad1c2b04
This diff is collapsed.
wrap/pll_drp.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b>pll_base
* @file pll_drp.v
* @date 2021-03-29
* @author Andrey Filippov
*
* @brief PLLE2_ADV wrapper for PLL_BASE functionality with DRP contol
*
* @copyright Copyright (c) 2014 Elphel, Inc.
*
* <b>License:</b>
*
* pll_base.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pll_base.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module pll_drp#(
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", // "OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT = 1, // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT0_DIVIDE = 1, // CLK0 outout divide, integer 1..128
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE", // Delays "DONE" signal until MMCM is locked
parameter DRP_ADDRESS_LENGTH = 7,
parameter DRP_DATA_LENGTH = 16
)
(
input clkin, // General clock input
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkfbout, // dedicate feedback output
output locked, // PLL locked output
// interface for the DRP (2 input bits, 2 output bits)
input drp_clk, // connect to mclk in x393
input [1:0] drp_cmd, // 0 - NOP, 1 - shift 0, 2 - shift 1, 3 - execute
output drp_out_bit, // output data ( ready after execute, data bit after shift 0/shift 1
output drp_out_odd_bit // alternates when new out_bit is available
);
wire [DRP_ADDRESS_LENGTH-1:0] drp_addr;
wire drp_den;
wire drp_dwe;
wire drp_drdy;
wire [DRP_DATA_LENGTH-1:0] drp_di;
wire [DRP_DATA_LENGTH-1:0] drp_do;
drp_mmcm_pll #(
.DRP_ADDRESS_LENGTH (DRP_ADDRESS_LENGTH),
.DRP_DATA_LENGTH (DRP_DATA_LENGTH)
) drp_mmcm_pll_i (
.dclk (drp_clk), // input
.mmcm_rst (rst), // input
.cmd (drp_cmd), // input[1:0]
.out_bit (drp_out_bit), // output
.out_odd_bit (drp_out_odd_bit), // output
.daddr (drp_addr), // output[6:0]
.di_drp (drp_di), // output[15:0]
.do_drp (drp_do), // input[15:0]
.drdy (drp_drdy), // input
.den (drp_den), // output
.dwe (drp_dwe) // output
);
PLLE2_ADV #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_ADV_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst), // input
// Unused ports for advanced option
// Unused second clock input and select
.CLKIN2 (1'b0), // input
.CLKINSEL (1'b1), // input
// DRP I/O
.DADDR (drp_addr), // Dynamic reconfiguration address (input[6:0])
.DCLK (drp_clk), // Dynamic reconfiguration clock input
.DEN (drp_den), // Dynamic reconfiguration enable input
.DWE (drp_dwe), // Dynamic reconfiguration Write Enable input
.DRDY (drp_drdy), // Dynamic reconfiguration ready output
.DI (drp_di), // Dynamic reconfiguration data (input[15:0])
.DO (drp_do) // Dynamic reconfiguration data (output[15:0])
);
endmodule
x393.v
View file @ ad1c2b04
......@@ -1871,6 +1871,7 @@ assign axi_grst = axi_rst_pre;
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_CTRL_DPR (SENS_CTRL_DPR), // eventually use for all sensors, not just Boson
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
......@@ -2013,16 +2014,29 @@ assign axi_grst = axi_rst_pre;
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
`ifdef BOSON
.PCLK_PHASE (PCLK_PHASE),
`endif
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.BUF_IPCLK_SENS0 (BUF_IPCLK_SENS0),
`ifdef BOSON
.BUF_PCLK_SENS0 (BUF_PCLK_SENS0),
.BUF_CLK_FB_SENS0 (BUF_CLK_FB_SENS0),
.BUF_PCLK_SENS1 (BUF_PCLK_SENS1),
.BUF_CLK_FB_SENS1 (BUF_CLK_FB_SENS1),
.BUF_PCLK_SENS2 (BUF_PCLK_SENS2),
.BUF_CLK_FB_SENS2 (BUF_CLK_FB_SENS2),
.BUF_PCLK_SENS3 (BUF_PCLK_SENS3),
.BUF_CLK_FB_SENS3 (BUF_CLK_FB_SENS3),
`endif
.BUF_IPCLK1X_SENS0 (BUF_IPCLK1X_SENS0),
.BUF_IPCLK2X_SENS0 (BUF_IPCLK2X_SENS0),
.BUF_IPCLK_SENS1 (BUF_IPCLK_SENS1),
.BUF_IPCLK1X_SENS1 (BUF_IPCLK1X_SENS1),
.BUF_IPCLK2X_SENS1 (BUF_IPCLK2X_SENS1),
.BUF_IPCLK_SENS2 (BUF_IPCLK_SENS2),
.BUF_IPCLK1X_SENS2 (BUF_IPCLK1X_SENS2),
.BUF_IPCLK2X_SENS2 (BUF_IPCLK2X_SENS2),
.BUF_IPCLK_SENS3 (BUF_IPCLK_SENS3),
.BUF_IPCLK1X_SENS3 (BUF_IPCLK1X_SENS3),
.BUF_IPCLK2X_SENS3 (BUF_IPCLK2X_SENS3),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......
x393_boson.bit
View file @ ad1c2b04
No preview for this file type
x393_boson.timing_summary_impl 0 → 100644
View file @ ad1c2b04
This diff is collapsed.
x393_boson_utilization.report 0 → 100644
View file @ ad1c2b04
This diff is collapsed.
x393_placement-true.tcl 0 → 100644
View file @ ad1c2b04
This diff is collapsed.
x393_placement.tcl
View file @ ad1c2b04
......@@ -473,3 +473,45 @@ set_property PACKAGE_PIN AA5 [get_ports RXN]
set_property PACKAGE_PIN AA6 [get_ports RXP]
set_property PACKAGE_PIN AB3 [get_ports TXN]
set_property PACKAGE_PIN AB4 [get_ports TXP]
if { $BOSON } {
# set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/*E2_ADV_i"}]
if { $LWIR} {
set_msg_config -id "Vivado 12-180" -suppress
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
reset_msg_config -id "Vivado 12-180" -suppress
}
#debugging:
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
}
x393_timing.tcl
View file @ ad1c2b04
......@@ -105,11 +105,16 @@ if { $BOSON} {
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
#only for lanes (not l3)
create_generated_clock -name iclk1x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
create_generated_clock -name iclk1x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
create_generated_clock -name iclk1x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
create_generated_clock -name iclk1x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0 iclk1x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1 iclk1x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2 iclk1x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3 iclk1x3}
} elseif { $LWIR} {
# Nothing here yet
......
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