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x393
Commit ad1c2b04 authored by Andrey Filippov's avatar Andrey Filippov
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103993-rev0 with DRP MMCM/PLL control

parent a753280e
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fpga_version.vh
View file @ ad1c2b04
......@@ -35,7 +35,12 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934001; // Boson640, adding camsync trigger decimation // git commit
parameter FPGA_VERSION = 32'h03934005; // Boson640, testing
// parameter FPGA_VERSION = 32'h03934005; // Boson640, implementing DRP to control MMCME2/PLLE2 trying more BUFR
// parameter FPGA_VERSION = 32'h03934004; // Boson640, implementing DRP to control MMCME2/PLLE2
// parameter FPGA_VERSION = 32'h03934003; // Boson640, mitigating LVDS errors
// parameter FPGA_VERSION = 32'h03934002; // Boson640, mitigating LVDS errors
// parameter FPGA_VERSION = 32'h03934001; // Boson640, adding camsync trigger decimation // git commit
///parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - debugging // git commit
// parameter FPGA_VERSION = 32'h03931002; // parallel, adding camsync trigger decimation
// parameter FPGA_VERSION = 32'h03931001; // parallel, fixing delays // git commit
......
includes/x393_parameters.vh
View file @ ad1c2b04
......@@ -5,7 +5,7 @@
*
* @brief Parameters for the x393 (simulation and implementation)
*
* @copyright Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015-2021 Elphel, Inc.
*
* <b>License:</b>
*
......@@ -518,6 +518,8 @@
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_CTRL_DPR= 30, // 30:31 DRP command
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
......@@ -705,7 +707,8 @@
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter PCLK_PHASE = 0.000, // not used
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`ifdef TWEAKING_IOSTANDARD
......@@ -725,8 +728,13 @@
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
`ifdef SIMULATION
parameter CLKFBOUT_PHASE_SENSOR = 54.0, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
`else
parameter CLKFBOUT_PHASE_SENSOR = -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.0, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
`endif
parameter PCLK_PHASE = 0.000, // not used
parameter IPCLK1X_PHASE = 0.000, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
parameter IPCLK2X_PHASE = 0.000,
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`ifdef TWEAKING_IOSTANDARD
......@@ -746,8 +754,10 @@
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter PCLK_PHASE = 0.000, // not used
parameter IPCLK1X_PHASE = 0.000, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
......@@ -765,29 +775,69 @@
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
`ifdef BOSON
parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", // "BUFIO", /// "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", // "BUFIO", ///"BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
// clock region X0Y0
parameter HISPI_MMCM0 = "TRUE",
parameter BUF_IPCLK1X_SENS0 = "BUFR",
parameter BUF_IPCLK2X_SENS0 = "BUFIO",
parameter BUF_PCLK_SENS0 = "BUFR",
parameter BUF_CLK_FB_SENS0 = "NONE",
// clock region X0Y0, use PLL
parameter HISPI_MMCM1 = "FALSE", // if false - will have to use only BUFG at the PLL outputs (only MMCM drives BUFIO and BUFR)
parameter BUF_IPCLK1X_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", //"BUFIO",// "BUFG", // "BUFIO", // "BUFR",
parameter BUF_PCLK_SENS1 = "BUFG",
parameter BUF_CLK_FB_SENS1 = "NONE", //"BUFG",
// clock region X0Y1
parameter HISPI_MMCM2 = "TRUE",
parameter BUF_IPCLK1X_SENS2 = "BUFR",
parameter BUF_IPCLK2X_SENS2 = "BUFIO",
parameter BUF_PCLK_SENS2 = "BUFR",
parameter BUF_CLK_FB_SENS2 = "NONE",
// clock region X0Y1
parameter HISPI_MMCM3 = "FALSE", // if false - will have to use only BUFG at the PLL outputs (only MMCM drives BUFIO and BUFR)
parameter BUF_IPCLK1X_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
parameter BUF_PCLK_SENS3 = "BUFG",
parameter BUF_CLK_FB_SENS3 = "NONE", //"BUFG",
parameter HISPI_DELAY_CLK0= "FALSE", // "TRUE", // when true, uses general routing resources after idelay
parameter HISPI_DELAY_CLK1= "FALSE", // "TRUE",
parameter HISPI_DELAY_CLK2= "FALSE", // "TRUE",
parameter HISPI_DELAY_CLK3= "FALSE", // "TRUE",
`else
parameter BUF_IPCLK_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter HISPI_MMCM0 = "TRUE",
parameter BUF_IPCLK1X_SENS0 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFIO", /// "BUFR", //G", // "BUFR",
parameter BUF_PCLK_SENS0 = "BUFR", // not used
parameter BUF_CLK_FB_SENS0 = "BUFR", // not used
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter HISPI_MMCM1 = "FALSE", // if false - will have to use only BUFG at the PLL outputs (only MMCM drives BUFIO and BUFR)
parameter BUF_IPCLK1X_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_PCLK_SENS1 = "BUFR", // not used
parameter BUF_CLK_FB_SENS1 = "BUFR", // not used
parameter BUF_IPCLK_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter HISPI_MMCM2 = "TRUE",
parameter BUF_IPCLK1X_SENS2 = "BUFR", // "BUFR2", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFIO", ///"BUFR", //G", // "BUFR",
parameter BUF_PCLK_SENS2 = "BUFR", // not used
parameter BUF_CLK_FB_SENS2 = "BUFR", // not used
parameter HISPI_MMCM3 = "FALSE", // if false - will have to use only BUFG at the PLL outputs (only MMCM drives BUFIO and BUFR)
parameter BUF_IPCLK1X_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
parameter BUF_PCLK_SENS3 = "BUFR", // not used
parameter BUF_CLK_FB_SENS3 = "BUFR", // not used
parameter HISPI_DELAY_CLK0= "TRUE",
parameter HISPI_DELAY_CLK1= "TRUE",
parameter HISPI_DELAY_CLK2= "TRUE",
parameter HISPI_DELAY_CLK3= "TRUE",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR2", ///"BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFIO", ///"BUFG", // "BUFR",
`endif
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -804,10 +854,6 @@
parameter HISPI_NUMLANES = 4,
`endif
parameter HISPI_DELAY_CLK0= "TRUE",
parameter HISPI_DELAY_CLK1= "TRUE",
parameter HISPI_DELAY_CLK2= "TRUE",
parameter HISPI_DELAY_CLK3= "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
......@@ -822,20 +868,6 @@
//VivadoRoute: [Route 35-54] Net: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/sr_reg[3]__0 is not completely routed. sensor_channel.v /x393/sensor line 42 Problem of the external builder
//VivadoRoute: [Route 35-54] Net: sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/sr_reg[3]__0 is not completely routed. sensor_channel.v /x393/sensor line 42 Problem of the external builder
`ifdef BOSON
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
`else
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
`endif
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
......
py393/vrlg.py
View file @ ad1c2b04
......@@ -187,6 +187,30 @@ BUF_CLK1X_PCLK2X__RAW = str
BUF_CLK1X_PCLK2X__TYPE = str
BUF_CLK1X_PCLK__RAW = str
BUF_CLK1X_PCLK__TYPE = str
BUF_CLK_FB_SENS0 = str
BUF_CLK_FB_SENS0__RAW = str
BUF_CLK_FB_SENS0__TYPE = str
BUF_CLK_FB_SENS1 = str
BUF_CLK_FB_SENS1__RAW = str
BUF_CLK_FB_SENS1__TYPE = str
BUF_CLK_FB_SENS2 = str
BUF_CLK_FB_SENS2__RAW = str
BUF_CLK_FB_SENS2__TYPE = str
BUF_CLK_FB_SENS3 = str
BUF_CLK_FB_SENS3__RAW = str
BUF_CLK_FB_SENS3__TYPE = str
BUF_IPCLK1X_SENS0 = str
BUF_IPCLK1X_SENS0__RAW = str
BUF_IPCLK1X_SENS0__TYPE = str
BUF_IPCLK1X_SENS1 = str
BUF_IPCLK1X_SENS1__RAW = str
BUF_IPCLK1X_SENS1__TYPE = str
BUF_IPCLK1X_SENS2 = str
BUF_IPCLK1X_SENS2__RAW = str
BUF_IPCLK1X_SENS2__TYPE = str
BUF_IPCLK1X_SENS3 = str
BUF_IPCLK1X_SENS3__RAW = str
BUF_IPCLK1X_SENS3__TYPE = str
BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS0__RAW = str
BUF_IPCLK2X_SENS0__TYPE = str
......@@ -199,18 +223,18 @@ BUF_IPCLK2X_SENS2__TYPE = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS3__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS0__RAW = str
BUF_IPCLK_SENS0__TYPE = str
BUF_IPCLK_SENS1 = str
BUF_IPCLK_SENS1__RAW = str
BUF_IPCLK_SENS1__TYPE = str
BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS2__RAW = str
BUF_IPCLK_SENS2__TYPE = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS3__RAW = str
BUF_IPCLK_SENS3__TYPE = str
BUF_PCLK_SENS0 = str
BUF_PCLK_SENS0__RAW = str
BUF_PCLK_SENS0__TYPE = str
BUF_PCLK_SENS1 = str
BUF_PCLK_SENS1__RAW = str
BUF_PCLK_SENS1__TYPE = str
BUF_PCLK_SENS2 = str
BUF_PCLK_SENS2__RAW = str
BUF_PCLK_SENS2__TYPE = str
BUF_PCLK_SENS3 = str
BUF_PCLK_SENS3__RAW = str
BUF_PCLK_SENS3__TYPE = str
CAMSYNC_ADDR = int
CAMSYNC_ADDR__RAW = str
CAMSYNC_ADDR__TYPE = str
......@@ -1015,12 +1039,12 @@ IDELAY_VALUE__TYPE = str
INITIALIZE_OFFSET = int
INITIALIZE_OFFSET__RAW = str
INITIALIZE_OFFSET__TYPE = str
IPCLK1X_PHASE = float
IPCLK1X_PHASE__RAW = str
IPCLK1X_PHASE__TYPE = str
IPCLK2X_PHASE = float
IPCLK2X_PHASE__RAW = str
IPCLK2X_PHASE__TYPE = str
IPCLK_PHASE = float
IPCLK_PHASE__RAW = str
IPCLK_PHASE__TYPE = str
LAST_BUF_FRAME = int
LAST_BUF_FRAME__RAW = str
LAST_BUF_FRAME__TYPE = str
......@@ -1828,6 +1852,9 @@ NUM_INTERRUPTS__TYPE = str
NUM_XFER_BITS = int
NUM_XFER_BITS__RAW = str
NUM_XFER_BITS__TYPE = str
PCLK_PHASE = float
PCLK_PHASE__RAW = str
PCLK_PHASE__TYPE = str
PHASE_CLK2X_PCLK = float
PHASE_CLK2X_PCLK__RAW = str
PHASE_CLK2X_PCLK__TYPE = str
......@@ -2176,6 +2203,9 @@ SENS_CTRL_ARO__TYPE = str
SENS_CTRL_ARST = int
SENS_CTRL_ARST__RAW = str
SENS_CTRL_ARST__TYPE = str
SENS_CTRL_DPR = int
SENS_CTRL_DPR__RAW = str
SENS_CTRL_DPR__TYPE = str
SENS_CTRL_EXT_CLK = int
SENS_CTRL_EXT_CLK__RAW = str
SENS_CTRL_EXT_CLK__TYPE = str
......
py393/x393_sens_cmprs.py
View file @ ad1c2b04
......@@ -935,16 +935,21 @@ class X393SensCmprs(object):
bits16 = bits16) #False)
if sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
skip_frames = 70 # 65 < min <70. 70 shows 4 frames, 100 shows 35 frames over uart
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (skip_frames): # 65): #70): #80): #100): # 60 10 2
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
timeout = 5.0) # 2.0)
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number (after skip to make sure Boson is in booted state before UART commands) = %d"%(fn))
if not self.DRY_MODE:
skip_frames = 70 # 65 < min <70. 70 shows 4 frames, 100 shows 35 frames over uart
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (skip_frames): # 65): #70): #80): #100): # 60 10 2
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
timeout = 5.0) # 2.0)
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number (after skip to make sure Boson is in booted state before UART commands) = %d"%(fn))
else:
print ("No frame skipping for Boson in simulated mode")
if verbose >0 :
print ("===================== CMPRS_EN_ARBIT =========================")
......
py393/x393_sensor.py
View file @ ad1c2b04
......@@ -213,6 +213,8 @@ class X393Sensor(object):
print (" busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
elif (sensorType == SENSOR_INTERFACE_BOSON):
print (" drp_odd_bit = %d"%((status>> 0) & 0x01))
print (" drp_bit = %d"%((status>> 1) & 0x01))
print (" ps_out = 0x%x"%((status>> 0) & 0xff))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" perr = %d"%((status>> 9) & 1))
......@@ -603,7 +605,8 @@ class X393Sensor(object):
gpio2 = None,
gpio3 = None,
alt_status = None,
test_pattern = None):
test_pattern = None,
drp_cmd = 0):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -615,6 +618,7 @@ class X393Sensor(object):
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param alt_status - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param test_pattern - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient
@param drp_cmd - DRP command di-bit: 0 - nop, 1 - shift 0, 2 - shift 1, 3 - execute command
@return sensor i/o control word
"""
rslt = 0
......@@ -639,6 +643,10 @@ class X393Sensor(object):
test_mode_masked = test_pattern & ((1 << vrlg.SENS_TEST_BITS) - 1)
rslt |= test_mode_masked << vrlg.SENS_TEST_MODES
rslt |= 1 << vrlg.SENS_TEST_SET
if (drp_cmd > 0) and (drp_cmd < 4):
rslt |= drp_cmd << vrlg.SENS_CTRL_DPR
return rslt
def func_sensor_uart_ctl_boson (self,
......@@ -1326,7 +1334,8 @@ class X393Sensor(object):
gpio2 = None,
gpio3 = None,
alt_status = None,
test_pattern = None):
test_pattern = None,
drp_cmd = 0):
"""
Set sensor I/O controls, including I/O signals
@param num_sensor - sensor port number (0..3)
......@@ -1339,36 +1348,39 @@ class X393Sensor(object):
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param alt_status - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param test_pattern - 0..7 - 0 normal data, 1+ - test patterns (1 - LSB col//3. MSB row//3, 2 - horizontal gradient , 3 - vertical gradient
@param drp_cmd - DRP command di-bit: 0 - nop, 1 - shift 0, 2 - shift 1, 3 - execute command
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_io_ctl_boson (num_sensor,
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
alt_status = alt_status,
test_pattern = test_pattern)
self.set_sensor_io_ctl_boson (
num_sensor,
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
alt_status = alt_status,
test_pattern = test_pattern,
drp_cmd = drp_cmd)
return
except:
pass
data = self.func_sensor_io_ctl_boson (
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
alt_status = alt_status,
test_pattern = test_pattern)
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
alt_status = alt_status,
test_pattern = test_pattern,
drp_cmd = drp_cmd)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
......@@ -1535,6 +1547,45 @@ class X393Sensor(object):
if not mmcm_phase is None:
self.x393_axi_tasks.write_control_register(reg_addr + 3, mmcm_phase & 0xff)
self.set_sensor_io_ctl_boson (num_sensor, set_delays = True)
def get_boson_err_rate(self,
num_sensor,
test_time = 10): #in seconds
"""
Measure parity error rate over LVDS pairs
@param num_sensor - sensor port number (0..3)
@param test_time - number of seconds for the test to run
@return (sign17, rate, number_of_tests)
"""
time_start=time.time()
time_end = time_start + test_time
self.set_sensor_io_ctl_boson (num_sensor, alt_status = True)
self.program_status_sensor_io(num_sensor, mode=1, seq_num=0)
status= self.get_status_sensor_io(num_sensor)
sign17 = status & 0xff
if sign17 != 0x17:
print("Signature: 0x%x (should be 0x17)"%(sign17,))
return (sign17, -1, 0)
nerr=0
ntry = 0
prev_errs = (status>>16) & 0xff
# print ("prev_errs = %d"%(prev_errs,))
while time.time() < time_end:
self.program_status_sensor_io(num_sensor, mode=1, seq_num=0)
status= self.get_status_sensor_io(num_sensor)
new_errs= (status>>16) & 0xff
nerr += (new_errs - prev_errs) % 256
prev_errs = new_errs
ntry += 1
print ("%.3f (%d tests)"%(nerr/test_time, ntry))
# print ("prev_errs = %d"%(prev_errs,))
return (sign17, nerr/test_time, ntry)
# self.set_sensor_io_ctl_boson (num_sensor, alt_status = False)
def set_sensor_hispi_lanes(self,
num_sensor,
......@@ -1772,6 +1823,152 @@ uart_print_packet 0 False False
uart_extif_en = True)
return packet
def drp_close(self,
num_sensor,
wait_lock = True):
"""
Close DRP connection, remove MMCM/PLL reset
@param num_sensor - sensor port number (0..3)
@param wait_lock - wait MMCM/PLL to lock
"""
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = False)
locked_pxd_mmcm = False
while not locked_pxd_mmcm:
sensor_status = self.x393Sensor.get_new_status(num_sensor=num_sensor)
locked_pxd_mmcm = ((sensor_status >> 12) & 1) != 0
def drp_read_reg(self,
num_sensor,
addr):
"""
Read DRP register from the MMCM/PLL. MMCM/PLL will be left in reset
@param num_sensor - sensor port number (0..3)
@param addr register 7-bit address
@return 16-bit register data
"""
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True)
# send 7-bit address
for i in range (7):
b = (addr >> (6-i)) & 1
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = b + 1)
# Read current odd bit
sensor_status = self.get_new_status(num_sensor)
odd_bit = (sensor_status >> 0) & 1
#execute command
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = 3)
odd_bit1 = odd_bit
for i in range (10): # should be done immediately
sensor_status = self.get_new_status(num_sensor)
odd_bit1 = (sensor_status >> 0) & 1 # will be inverted after address
if odd_bit1 != odd_bit:
break
if (odd_bit == odd_bit1):
raise TimeoutError('Timeout while waiting for the DRP register read.')
# shift in 16 data bits
data = 0
for _ in range (16):
sensor_status = self.get_new_status(num_sensor)
data_bit = (sensor_status >> 1) & 1 # will be inverted after address
data = (data << 1) + data_bit
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = 1) # shift 0
# finish command
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = 3)
return data
def drp_write_reg(self,
num_sensor,
addr,
data,
mask=None):
"""
write DRP register to the MMCM/PLL. MMCM/PLL will be left in reset, if mask is defined
only selected bits will be updated (read operation will be performed first)
@param num_sensor - sensor port number (0..3)
@param addr register 7-bit address
@param data 16-bit data to write
@param data 16-bit mask (only ones will be updated)
"""
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True)
old_data = None
if not mask is None:
old_data = self.drp_read_reg(num_sensor, addr)
data = ((old_data ^ data) & mask) ^ old_data
# send 7-bit address
for i in range (7):
b = (addr >> (6-i)) & 1
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = b + 1)
#send 16-bit data:
for i in range (16):
b = (data >> (15-i)) & 1
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = b + 1)
# Read current odd bit
sensor_status = self.get_new_status(num_sensor)
odd_bit = (sensor_status >> 0) & 1
#execute command
self.set_sensor_io_ctl_boson ( num_sensor, mmcm_rst = True, drp_cmd = 3)
odd_bit1 = odd_bit
for i in range (10): # should be done immediately
sensor_status = self.get_new_status(num_sensor)
odd_bit1 = (sensor_status >> 0) & 1 # will be inverted after address
if odd_bit1 != odd_bit:
break
if (odd_bit == odd_bit1):
raise TimeoutError('Timeout while waiting for the DRP register write.')
def drp_phase_addr(self,
clk_out=-1):
"""
Get a pair (ClkReg1,ClkReg2 - SEE xapp888) of DRP registers for clock phases
@param clk_out - clock number: -1 - CLKFBOUT, 0..6 - CLKOUT0...CLKOUT6
@return a pair of corresponding DRP register addresses
"""
clk_reg_addr=[[0x14,0x15], #CLKFBOUT
[0x08, 0x09],
[0x0a, 0x0b],
[0x0c, 0x09],
[0x08, 0x09],
[0x08, 0x09],
]
return clk_reg_addr[clk_out + 1]
def drp_read_clock_phase(self,
num_sensor,
clk_out = -1):# -1 - FB, 0..6 - CLKOUT0...CLKOUT6
"""
Read MMCME2/PLLE2 clock phases (in 1/8 of the VCO periods)
@param num_sensor - sensor port number (0..3)
@param clk_out - clock number: -1 - CLKFBOUT, 0..6 - CLKOUT0...CLKOUT6
@return current phase shift in 1/8s of the VCO period
"""
ClkReg1, ClkReg2 = self.drp_phase_addr(clk_out)
data1 = self.drp_read_reg(num_sensor, ClkReg1)
data2 = self.drp_read_reg(num_sensor, ClkReg2)
phase = ((data1 >> 13) & 7) | ((data2 & 0x1f) << 3)
return phase
def drp_write_clock_phase(self,
num_sensor,
clk_out = -1,# -1 - FB, 0..6 - CLKOUT0...CLKOUT6
phase = 0):
"""
Read MMCME2/PLLE2 clock phases (in 1/8 of the VCO periods)
@param num_sensor - sensor port number (0..3)
@param clk_out - clock number: -1 - CLKFBOUT, 0..6 - CLKOUT0...CLKOUT6
@param phase - phase shift in 1/8s of the VCO period
"""
ClkReg1, ClkReg2 = self.drp_phase_addr(clk_out)
data1 = (phase & 7) << 13
data2 = (phase >> 3) & 0x1f
self.drp_write_reg(num_sensor, addr=ClkReg1, data=data1, mask=0xe000)
self.drp_write_reg(num_sensor, addr=ClkReg2, data=data2, mask=0x001f)
def jtag_get_tdo(self, chn):
seq_num = ((self.get_status_sensor_io(num_sensor = chn) >> 26) + 1) & 0x3f
self.program_status_sensor_io(num_sensor = chn,
......
sensor/sens_103993.v
View file @ ad1c2b04
......@@ -37,7 +37,7 @@
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`define USE_SERIALIZER_103993
module sens_103993 #(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h7f8,
......@@ -81,6 +81,8 @@ module sens_103993 #(
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_CTRL_DPR= 30, // 30:31 DRP command
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS = 10,
parameter SENS_TEST_WIDTH_INC = 3,
......@@ -93,7 +95,7 @@ module sens_103993 #(
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
......@@ -101,9 +103,12 @@ module sens_103993 #(
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK1X = "BUFR",
parameter BUF_CLK_FB = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -227,8 +232,8 @@ module sens_103993 #(
reg set_status_r;
wire perr; // parity error from deserializer
wire ps_rdy;
wire [7:0] ps_out;
// wire ps_rdy;
// wire [7:0] ps_out;
wire [7:0] test_out; // should be 0x17 from unused serial signals
wire clkin_pxd_stopped_mmcm;
wire clkfb_pxd_stopped_mmcm;
......@@ -237,6 +242,10 @@ module sens_103993 #(
reg imrst = 0; // active low
reg rst_mmcm=1; // rst and command - en/dis
reg ld_idelay=0;
reg [1:0] drp_cmd;
wire drp_bit;
wire drp_odd_bit;
wire [25:0] status;
......@@ -288,8 +297,11 @@ module sens_103993 #(
test_patt? nonlock_persistent : clkin_pxd_stopped_mmcm, // 11
recv_odd_even, // clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
test_patt? perr : ps_rdy, // 8
test_patt? test_out[7:0]:ps_out[7:0],// [7:0]
// test_patt? perr : ps_rdy, // 8
// test_patt? test_out[7:0]:ps_out[7:0],// [7:0]
perr, // 8
test_out[7:2], // [7:2]
test_patt? test_out[1:0]:{drp_bit, drp_odd_bit},// [1:0]
xmit_busy, // 25
senspgmin}; // 24
......@@ -385,6 +397,8 @@ module sens_103993 #(
if (mrst || set_ctrl_r) nonlock_persistent <= 0;
else if (!locked_pclk || clkin_pxd_stopped_mmcm || clkfb_pxd_stopped_mmcm) nonlock_persistent <= 1;
drp_cmd[1:0] <= (mrst || !set_ctrl_r)? 2'b0 : data_r[SENS_CTRL_DPR +: 2];
end
cmd_deser #(
......@@ -455,7 +469,88 @@ module sens_103993 #(
);
/*
wire pclk1;
wire [15:0] pxd_w1;
wire vsync1;
wire hsync1;
wire dvalid_w1;
wire perr1;
wire ps_rdy1;
wire [7:0] ps_out1;
wire [7:0] test_out1;
wire locked_pclk1;
wire clkin_pxd_stopped_mmcm1;
wire clkfb_pxd_stopped_mmcm1;
*/
`ifdef USE_SERIALIZER_103993
sens_103993_lanes #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
// .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), // (54.0),
.PCLK_PHASE (PCLK_PHASE), // (0.000),
.IPCLK1X_PHASE (IPCLK1X_PHASE), //(0.000), // not actually used
.IPCLK2X_PHASE (IPCLK2X_PHASE), //(0.000),
.BUF_PCLK (BUF_PCLK), // "BUFR"),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X), // "BUFR"),
.BUF_CLK_FB (BUF_CLK_FB),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), // 1),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), // 0.010),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), // 0.010),
.SENS_SS_EN (SENS_SS_EN), // "FALSE"),
.SENS_SS_MODE (SENS_SS_MODE), // "CENTER_HIGH"),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), // 10000),
.NUMLANES (NUMLANES), // 3),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK), // "FALSE"),
.LVDS_MMCM (LVDS_MMCM), // "TRUE"),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE), // "DONT_CARE"),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM), // "TRUE"),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT), // "FALSE"),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS), // "TRUE"),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE), // "0"),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD), // "DIFF_SSTL18_I")
.DEGLITCH_DVALID (1),
.DEGLITCH_HSYNC (3),
.DEGLITCH_VSYNC (7)
) sens_103993_l3_i ( // same instance name
.pclk (pclk), // output
.prsts (prsts), // input,
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd_w), // output[15:0]
.vsync (vsync), // output
.hsync (hsync), // output
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r[23:0]), // input[23:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.apply_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
.rst_mmcm (rst_mmcm), // input
.perr (perr), // output
// .ps_rdy (ps_rdy), // output
// .ps_out (ps_out), // output[7:0]
.test_out (test_out), // output[7:0] // should be 0x17
.locked_pxd_mmcm (locked_pclk), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output
.drp_cmd (drp_cmd), // input[1:0]
.drp_bit (drp_bit), // output
.drp_odd_bit (drp_odd_bit) // output
);
`else //USE_SERIALIZER_103993 - need to update to use DRP, current ports will be invalid
sens_103993_l3 #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
......@@ -467,9 +562,12 @@ module sens_103993 #(
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), // (0.000),
.PCLK_PHASE (PCLK_PHASE), // (0.000),
.IPCLK1X_PHASE (IPCLK1X_PHASE), //(0.000), // not actually used
.IPCLK2X_PHASE (IPCLK2X_PHASE), //(0.000),
.BUF_PCLK (BUF_PCLK), // "BUFR"),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X), // "BUFR"),
.BUF_CLK_FB (BUF_CLK_FB),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), // 1),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), // 0.010),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), // 0.010),
......@@ -489,8 +587,9 @@ module sens_103993 #(
.LVDS_IOSTANDARD (LVDS_IOSTANDARD) // "DIFF_SSTL18_I")
) sens_103993_l3_i (
.pclk (pclk), // output
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
.prsts (prsts), // input,
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd_w), // output[15:0]
......@@ -512,6 +611,8 @@ module sens_103993 #(
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
`endif // USE_SERIALIZER_103993
// implement test gradient
assign pxd_test =
......
sensor/sens_103993_clock.v
View file @ ad1c2b04
......@@ -46,9 +46,12 @@ module sens_103993_clock#(
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000, // dummy here
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK1X = "BUFR", // not used here
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_CLK_FB = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -91,7 +94,7 @@ module sens_103993_clock#(
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
localparam BUF_CLK_FB = BUF_IPCLK2X;
// localparam BUF_CLK_FB = BUF_IPCLK2X;
wire pclk_pre;
wire ipclk2x_pre; // output
wire clk_fb_pre;
......@@ -218,6 +221,7 @@ module sens_103993_clock#(
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT2_PHASE (IPCLK1X_PHASE), // not used here
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT1_USE_FINE_PS ("FALSE"), //"TRUE"),
......@@ -272,6 +276,7 @@ module sens_103993_clock#(
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT2_PHASE (IPCLK1X_PHASE), // not used here
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.REF_JITTER1 (SENS_REF_JITTER1),
......@@ -328,6 +333,10 @@ module sens_103993_clock#(
else assign pclk = pclk_pre;
endgenerate
generate
if (BUF_IPCLK1X == "BUFG") begin // not used here
end
endgenerate
endmodule
......
sensor/sens_103993_clock_25.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b>sens_103993_clock_25
* @file sens_103993_clock_25.v
* @date 2020-12-16
* @author Andrey Filippov
*
* @brief Recover iclk/iclk2x from the 103993 differntial clock
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_clock_25#(
// parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps 1000/27.0
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK1X = "BUFR",
parameter BUF_CLK_FB = "BUFR", // was localparam BUF_CLK_FB = BUF_IPCLK2X;
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// Used with delay
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter DRP_ADDRESS_LENGTH = 7,
parameter DRP_DATA_LENGTH = 16
)(
input mclk,
input mrst,
input [7:0] phase,
input set_phase,
input apply, // only used when delay, not phase
input rst_mmcm,
input clp_p,
input clk_n,
output ipclk2x, // 330 MHz
output ipclk1x, // 165 MHz
output pclk, // 27 MHz
// output ps_rdy, // output
// output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm, // output
output for_pclk, // copy 10 bits form ipclk1x domain to pclk (alternating 2/3 iplck1x intervals)
output for_pclk_early, // valid with copy_to_pclk, 10 bits contain early data from 12 bits (per lane)
input [1:0] drp_cmd,
output drp_bit,
output drp_odd_bit
);
// localparam BUF_CLK_FB = BUF_IPCLK2X;
wire pclk_pre;
wire ipclk2x_pre;
wire ipclk1x_pre;
wire clk_fb_pre;
wire clk_fb;
wire prst = mrst;
wire clk_in;
wire clk_int;
reg pclk_r;
reg [4:0] iclk_r;
/*
wire set_phase_w = (LVDS_DELAY_CLK == "TRUE") ? 1'b0: set_phase;
wire [7:0] phase_w = (LVDS_DELAY_CLK == "TRUE") ? 8'b0: phase;
wire ps_rdy_w;
wire [7:0] ps_out_w;
assign ps_rdy = (LVDS_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (LVDS_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
*/
assign for_pclk = iclk_r[2];
assign for_pclk_early = iclk_r[2] && iclk_r[0];
generate
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
// variable termination
end else if (LVDS_UNTUNED_SPLIT == "40") begin
ibufds_ibufgds_40 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "50") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "60") begin
ibufds_ibufgds_60 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end
endgenerate
generate
if (LVDS_DELAY_CLK == "TRUE") begin // Avoid - delay output is routed using general routing resources even from the clock-capable
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) clk_dly_i(
.clk (mclk),
.rst (mrst),
// .set (set_phase),
// .ld (load),
/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?)
.set (apply),
.ld (set_phase),
.delay (phase[7:3]), // skip lsb, not MSB
.data_in (clk_int),
.data_out (clk_in)
);
end else begin // just testing placement
/*
reg fake_r;
always @ (posedge clk_int) begin
if (mrst) fake_r <= 0;
else fake_r <= !fake_r;
end
BUFG fake_clk_i (.O(clk_in), .I(fake_r));
*/
assign clk_in = clk_int;
end
endgenerate
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor)
generate
if (LVDS_MMCM == "TRUE") begin
mmcm_drp #(
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT2_PHASE (IPCLK1X_PHASE),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT1_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT2_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // /30 -> 27 MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 5), // /6 -> 135 MHz
.CLKOUT2_DIVIDE (2 *CLKFBOUT_MULT_SENSOR / 5), // /12 -> 67.5 MHz
.COMPENSATION ("ZHOLD"),
.REF_JITTER1 (SENS_REF_JITTER1),
.REF_JITTER2 (SENS_REF_JITTER2),
.SS_EN (SENS_SS_EN),
.SS_MODE (SENS_SS_MODE),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STARTUP_WAIT ("FALSE"),
.DRP_ADDRESS_LENGTH (DRP_ADDRESS_LENGTH),
.DRP_DATA_LENGTH (DRP_DATA_LENGTH)
) mmcm_or_pll_i (
.clkin1 (clk_in), // input 27MHz
.clkin2 (1'b0), // input
.sel_clk2 (1'b0), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.clkout0 (pclk_pre), // output -> 27 MHz
.clkout1 (ipclk2x_pre), // output 135 Mhz
.clkout2 (ipclk1x_pre), // output 67.5 MHz
.clkout3 (), // output
.clkout4 (), // output
.clkout5 (), // output
.clkout6 (), // output
.clkout0b (), // output
.clkout1b (), // output
.clkout2b (), // output
.clkout3b (), // output
.clkfbout (clk_fb_pre), // output
.clkfboutb (), // output
.locked (locked_pxd_mmcm), // output
.clkin_stopped (clkin_pxd_stopped_mmcm), // output
.clkfb_stopped (clkfb_pxd_stopped_mmcm), // output
.drp_clk (mclk), // input
.drp_cmd (drp_cmd), // input[1:0]
.drp_out_bit (drp_bit), // output
.drp_out_odd_bit (drp_odd_bit) // output
);
end else begin
pll_drp #(
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT_SENSOR), // 30
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT2_PHASE (IPCLK1X_PHASE),
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 5), // /6 -> 135 MHz
.CLKOUT2_DIVIDE (2 *CLKFBOUT_MULT_SENSOR / 5), // /12 -> 67.5 MHz
.REF_JITTER1 (SENS_REF_JITTER1),
.STARTUP_WAIT ("FALSE"),
.DRP_ADDRESS_LENGTH (DRP_ADDRESS_LENGTH),
.DRP_DATA_LENGTH (DRP_DATA_LENGTH)
) mmcm_or_pll_i (
.clkin (clk_in), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.clkout0 (pclk_pre), // output -> 27MHz
.clkout1 (ipclk2x_pre), // output 135 Mhz
.clkout2 (ipclk1x_pre), // output 67.5 MHz
.clkout3 (), // output
.clkout4 (), // output
.clkout5 (), // output
.clkfbout (clk_fb_pre), // output
.locked (locked_pxd_mmcm), // output
.drp_clk (mclk), // input
.drp_cmd (drp_cmd), // input[1:0]
.drp_out_bit (drp_bit), // output
.drp_out_odd_bit (drp_odd_bit) // output
);
assign clkin_pxd_stopped_mmcm = 0;
assign clkfb_pxd_stopped_mmcm = 0;
// assign ps_rdy_w = 1;
// assign ps_out_w = 0; // alternatively - register delay written
end
endgenerate
generate
if (BUF_CLK_FB == "BUFG") BUFG clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else if (BUF_CLK_FB == "BUFH") BUFH clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else if (BUF_CLK_FB == "BUFR") BUFR clk2x_i (.O(clk_fb), .I(clk_fb_pre), .CE(1'b1), .CLR(prst));
else if (BUF_CLK_FB == "BUFMR") BUFMR clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else if (BUF_CLK_FB == "BUFIO") BUFIO clk2x_i (.O(clk_fb), .I(clk_fb_pre));
else assign clk_fb = clk_fb_pre;
endgenerate
generate
if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFMR") begin
wire ipclk2xr_pre2;
BUFMR clk2x2_i (.O(ipclk2xr_pre2), .I(ipclk2x_pre));
BUFR clk2x_i (.O(ipclk2x), .I(ipclk2xr_pre2), .CE(1'b1), .CLR(prst));
end else if (BUF_IPCLK2X == "BUFMIO") begin
wire ipclk2x_pre2;
BUFMR clk2x2_i (.O(ipclk2x_pre2), .I(ipclk2x_pre));
BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre2));
end else assign ipclk2x = ipclk2x_pre;
endgenerate
generate
if (BUF_IPCLK1X == "BUFG") BUFG clk1x_i (.O(ipclk1x), .I(ipclk1x_pre));
else if (BUF_IPCLK1X == "BUFH") BUFH clk1x_i (.O(ipclk1x), .I(ipclk1x_pre));
else if (BUF_IPCLK1X == "BUFR") BUFR clk1x_i (.O(ipclk1x), .I(ipclk1x_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK1X == "BUFIO") BUFIO clk1x_i (.O(ipclk1x), .I(ipclk1x_pre));
else if (BUF_IPCLK2X == "BUFMR") begin
wire ipclk1xr_pre2;
BUFMR clk1x2_i (.O(ipclk1xr_pre2), .I(ipclk1x_pre));
BUFR clk1x_i (.O(ipclk1x), .I(ipclk1xr_pre2), .CE(1'b1), .CLR(prst));
end else if (BUF_IPCLK2X == "BUFMIO") begin
wire ipclk1x_pre2;
BUFMR clk1x2_i (.O(ipclk1x_pre2), .I(ipclk1x_pre));
BUFIO clk1x_i (.O(ipclk1x), .I(ipclk1x_pre2));
end else assign ipclk1x = ipclk1x_pre;
endgenerate
generate
if (BUF_PCLK == "BUFG") BUFG clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFH") BUFH clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFR") BUFR clk2x_i (.O(pclk), .I(pclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_PCLK == "BUFIO") BUFIO clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFMR") BUFMR clk2x_i (.O(pclk), .I(pclk_pre));
else assign pclk = pclk_pre;
endgenerate
always @(negedge pclk or posedge iclk_r[0]) begin
if (iclk_r[0]) pclk_r <= 0;
else pclk_r <= !prst;
end
always @ (posedge ipclk1x) begin
if (prst) iclk_r <=0;
else iclk_r <= {iclk_r[3:0], pclk_r};
end
endmodule
sensor/sens_103993_l3.v
View file @ ad1c2b04
......@@ -50,9 +50,12 @@ module sens_103993_l3#(
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK1X = "BUFR", // not used here
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_CLK_FB = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -71,9 +74,13 @@ module sens_103993_l3#(
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter DEGLITCH_DVALID = 1,
parameter DEGLITCH_HSYNC = 3,
parameter DEGLITCH_VSYNC = 7
)(
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
input prsts,
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
......@@ -104,18 +111,21 @@ module sens_103993_l3#(
wire ipclk2x;// re-generated HiSPi clock (270 MHa) 330 MHz)
wire [NUMLANES * 10-1:0] sns_d;
reg [15:0] pxd_out_r;
reg vsync_r;
reg hsync_r;
reg dvalid_r;
reg [15:0] pxd_out_r2;
// reg vsync_r;
// reg hsync_r;
// reg dvalid_r;
reg perr_r;
reg cp_r;
wire [15:0] pxd_w;
assign pxd_out = pxd_out_r;
assign vsync = vsync_r;
assign hsync = hsync_r;
assign dvalid = dvalid_r;
assign pxd_out = (DEGLITCH_DVALID>0)? pxd_out_r: pxd_out_r2;
// assign vsync = vsync_r;
// assign hsync = hsync_r;
// assign dvalid = dvalid_r;
assign perr = perr_r;
assign test_out = sns_d[29:22];
assign pxd_w = {sns_d[19:12],sns_d[9:2]};
sens_103993_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -124,9 +134,12 @@ module sens_103993_l3#(
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (PCLK_PHASE),
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_PCLK),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.BUF_CLK_FB (BUF_CLK_FB),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
......@@ -143,6 +156,7 @@ module sens_103993_l3#(
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
......@@ -195,14 +209,41 @@ module sens_103993_l3#(
.dout (sns_d) // output[29:0]
);
always @(posedge pclk) begin
pxd_out_r <= {sns_d[19:12],sns_d[9:2]};
vsync_r <= sns_d[1]; // input - active high
hsync_r <= sns_d[11]; // input - active high
dvalid_r <= sns_d[21]; // input - active hight
pxd_out_r <= pxd_w;
pxd_out_r2 <= pxd_out_r;
// vsync_r <= sns_d[1]; // input - active high
// hsync_r <= sns_d[11]; // input - active high
// dvalid_r <= sns_d[21]; // input - active hight
cp_r <= sns_d[0];
// perr_r <= ~ cp_r ^ (^pxd_out_r) ^ vsync_r ^ hsync_r ^ dvalid_r;
perr_r <= ~ (^sns_d[9:0]) ^ (^sns_d[19:11]) ^ (^sns_d[29:21]); //DS: XOR of all selected bits result in odd parity
end
deglitch #(
.CLOCKS(DEGLITCH_DVALID)
) deglitch_dvalid_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[21]), // input
.q(dvalid) // output
);
deglitch #(
.CLOCKS(DEGLITCH_HSYNC)
) deglitch_hsync_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[11]), // input
.q(hsync) // output
);
deglitch #(
.CLOCKS(DEGLITCH_VSYNC)
) deglitch_vsync_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[1]), // input
.q(vsync) // output
);
endmodule
sensor/sens_103993_lane.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> sens_103993_lane
* @file sens_103993_lane.v
* @date 2021-03-26
* @author eyesis
*
* @brief
*
* @copyright Copyright (c) 2021 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993_lane.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_lane.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_lane#(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
// parameter NUMLANES = 3,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input ld_idelay, // mclk synchronous load idelay value
input apply_idelay, // mclk synchronous set idealy value
input pclk, // 27 MHz
input ipclk2x, // 135 MHz
input ipclk1x, // 67.5 MHz
input rst, // reset// @posedge iclk
input for_pclk, // copy 10 bits form ipclk1x domain to pclk (alternating 2/3 iplck1x intervals)
input for_pclk_early, // valid with copy_to_pclk, 10 bits contain early data from 12 bits (per lane)
input din_p,
input din_n,
output [9:0] dout);
wire din;
wire din_dly;
wire [3:0] deser_w; // deserializer 4-bit output
reg [7:0] deser_r;
reg [9:0] dout_r;
reg [9:0] pre_dout_r;
assign dout=dout_r;
generate
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "40") begin
ibufds_ibufgds_40 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "50") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // inputpre_dout_r
);
end else if (LVDS_UNTUNED_SPLIT == "60") begin
ibufds_ibufgds_60 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din), // output
.I (din_p), // input
.IB (din_n) // input
);
end
endgenerate
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (apply_idelay),
.ld (ld_idelay),
.delay (dly_data[7:3]),
.data_in (din),
.data_out (din_dly)
);
iserdes_mem #(
.DYN_CLKDIV_INV_EN ("FALSE"),
.MSB_FIRST (1) // MSB is received first
) iserdes_pxd_i (
.iclk (ipclk2x), // source-synchronous clock
.oclk (ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
.oclk_div (ipclk1x), // oclk divided by 2, front aligned
.inv_clk_div (1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
.rst (rst), // reset
.d_direct (1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly (din_dly), // serial input from idelay
.dout (deser_w), // parallel data out
.comb_out() // output
);
always @ (posedge ipclk1x) begin
deser_r <= {deser_r[3:0],deser_w[3:0]};
// if (for_pclk) pre_dout_r <= for_pclk_early ? {deser_w[1:0],deser_r[7:0]} : {deser_w[3:0],deser_r[7:2]};
if (for_pclk) pre_dout_r <= for_pclk_early ? {deser_r[7:0],deser_w[3:2]} : {deser_r[5:0],deser_w[3:0]};
end
always @ (posedge pclk) begin
dout_r <= pre_dout_r;
end
endmodule
sensor/sens_103993_lanes.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> sens_103993_lanes
* @file sens_103993_lanes.v
* @date 2021-03-26
* @author eyesis
*
* @brief 3-lane deserializer for Boson640
*
* @copyright Copyright (c) 2021 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993_lanes.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_lanes.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_lanes #(
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
// parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000, /// new
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK1X = "BUFR", /// new
parameter BUF_CLK_FB = "BUFR", /// new
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter NUMLANES = 3,
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter DEGLITCH_DVALID = 1,
parameter DEGLITCH_HSYNC = 3,
parameter DEGLITCH_VSYNC = 7
)(
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
input prsts,
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
input sns_clkp,
input sns_clkn,
// output
output [15:0] pxd_out,
output vsync,
output hsync,
output dvalid,
// delay control inputs
input mclk,
input mrst,
input [NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input apply_idelay, // mclk synchronous set idelay value
input set_clk_phase, // mclk synchronous set idelay value
input rst_mmcm,
// MMCP output status
output perr, // parity error
// output ps_rdy, // output
// output [7:0] ps_out, // output[7:0] reg
output [7:0] test_out,
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm, // output
input [1:0] drp_cmd,
output drp_bit,
output drp_odd_bit
);
wire [NUMLANES * 10-1:0] sns_d;
wire ipclk2x;// re-generated clock (135 MHz)
wire ipclk1x;// re-generated clock (67.5 MHz)
reg [15:0] pxd_out_r;
reg [15:0] pxd_out_r2;
reg perr_r;
// reg cp_r;
wire [15:0] pxd_w;
wire for_pclk;
wire for_pclk_early;
assign pxd_out = (DEGLITCH_DVALID>0)? pxd_out_r: pxd_out_r2;
assign perr = perr_r;
assign test_out = sns_d[29:22];
assign pxd_w = {sns_d[19:12],sns_d[9:2]};
sens_103993_clock_25 #(
// .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (PCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.BUF_PCLK (BUF_PCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_CLK_FB (BUF_CLK_FB),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK),
.LVDS_MMCM (LVDS_MMCM),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD)
) sens_103993_clock_i ( // same instance name as in sens_103993_l3
.mclk (mclk), // input
.mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input
.apply (apply_idelay), // input
.rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input
.ipclk2x (ipclk2x), // output
.ipclk1x (ipclk1x), // output
.pclk (pclk), // output 27MHz
// .ps_rdy (ps_rdy), // output
// .ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pxd_mmcm), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output
.for_pclk (for_pclk), // output
.for_pclk_early (for_pclk_early), // output
.drp_cmd (drp_cmd), // input[1:0]
.drp_bit (drp_bit), // output
.drp_odd_bit (drp_odd_bit) // output
);
generate
genvar i;
for (i=0; i < NUMLANES; i=i+1) begin: lane_block
sens_103993_lane #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE), // "DONT_CARE"),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM), // "TRUE"),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT), // "FALSE"),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS), // "TRUE"),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE), // "0"),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD) // "DIFF_SSTL18_I")
) sens_103993_lane_i (
.mclk (mclk), // input
.mrst (mrst), // input
// .dly_data (dly_data[7 + 8*i +: 8]), // input[7:0] dly_data[3 + 8*i +: 5
.dly_data (dly_data[8*i +: 8]), // input[7:0] dly_data[3 + 8*i +: 5
.ld_idelay (set_idelay[i]), // input
.apply_idelay (apply_idelay), // input
.pclk (pclk), // input
.ipclk2x (ipclk2x), // input
.ipclk1x (ipclk1x), // input
.rst (mrst), // input
.for_pclk (for_pclk), // input
.for_pclk_early (for_pclk_early), // input
.din_p (sns_dp[2-i]), // input REVERSED order (matching PCB)
.din_n (sns_dn[2-i]), // input REVERSED order (matching PCB)
.dout (sns_d[10*i +: 10]) // output[9:0]
);
end
endgenerate
always @(posedge pclk) begin
pxd_out_r <= pxd_w;
pxd_out_r2 <= pxd_out_r;
// cp_r <= sns_d[0];
perr_r <= ~ (^sns_d[9:0]) ^ (^sns_d[19:11]) ^ (^sns_d[29:21]); //DS: XOR of all selected bits result in odd parity
end
deglitch #(
.CLOCKS(DEGLITCH_DVALID)
) deglitch_dvalid_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[21]), // input
.q(dvalid) // output
);
deglitch #(
.CLOCKS(DEGLITCH_HSYNC)
) deglitch_hsync_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[11]), // input
.q(hsync) // output
);
deglitch #(
.CLOCKS(DEGLITCH_VSYNC)
) deglitch_vsync_i (
.clk(pclk), // input
.rst(prsts), // input
.d(sns_d[1]), // input
.q(vsync) // output
);
endmodule
sensor/sensor_channel.v
View file @ ad1c2b04
......@@ -213,6 +213,7 @@ module sensor_channel#(
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_CTRL_DPR= 30, // 30:31 DRP command
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
......@@ -373,7 +374,8 @@ module sensor_channel#(
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
// parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -381,8 +383,8 @@ module sensor_channel#(
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
//IPCLK* will be used as PCLK*
parameter IPCLK_PHASE = 0.000,
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -390,15 +392,20 @@ module sensor_channel#(
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
// parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`ifdef LWIR
`else // all but LWIR
parameter BUF_IPCLK = "BUFR",
`else // all but LWIR
`ifdef BOSON
parameter BUF_PCLK = "BUFR",
parameter BUF_CLK_FB = "BUFR",
`endif
parameter BUF_IPCLK1X = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -1121,9 +1128,9 @@ module sensor_channel#(
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......@@ -1205,6 +1212,7 @@ module sensor_channel#(
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_CTRL_DPR (SENS_CTRL_DPR),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
......@@ -1224,14 +1232,17 @@ module sensor_channel#(
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
// .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (IPCLK_PHASE), // use IPCLK* for PCLK*
.PCLK_PHASE (PCLK_PHASE),
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_IPCLK), // use IPCLK* for PCLK*
.BUF_PCLK (BUF_PCLK),
.BUF_CLK_FB (BUF_CLK_FB),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......@@ -1469,10 +1480,10 @@ module sensor_channel#(
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......
sensor/sensors393.v
View file @ ad1c2b04
......@@ -184,7 +184,6 @@ module sensors393 #(
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
......@@ -195,6 +194,7 @@ module sensors393 #(
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_CTRL_DPR= 30, // 30:31 DRP command
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
......@@ -377,7 +377,7 @@ module sensors393 #(
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -385,7 +385,8 @@ module sensors393 #(
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter PCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
......@@ -393,7 +394,7 @@ module sensors393 #(
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK1X_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
......@@ -401,13 +402,23 @@ module sensors393 #(
`ifdef LWIR
`else
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
`ifdef BOSON
parameter BUF_PCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_PCLK_SENS1 = "BUFR", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS1 = "BUFR", // "BUFR",
parameter BUF_PCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_PCLK_SENS3 = "BUFR", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_CLK_FB_SENS3 = "BUFR", // "BUFR",
`endif
parameter BUF_IPCLK1X_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK1X_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK1X_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK1X_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
......@@ -794,6 +805,7 @@ module sensors393 #(
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_CTRL_DPR (SENS_CTRL_DPR),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
......@@ -943,13 +955,20 @@ module sensors393 #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
`ifdef BOSON
.PCLK_PHASE (PCLK_PHASE),
`endif
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK ((i & 2) ? ((i & 1) ? BUF_IPCLK_SENS3 : BUF_IPCLK_SENS2) : ((i & 1) ?BUF_IPCLK_SENS1 :BUF_IPCLK_SENS0 )),
.BUF_IPCLK2X ((i & 2) ? ((i & 1) ? BUF_IPCLK2X_SENS3 : BUF_IPCLK2X_SENS2) : ((i & 1) ?BUF_IPCLK2X_SENS1 :BUF_IPCLK2X_SENS0 )),
`ifdef BOSON
.BUF_PCLK ((i & 2) ? ((i & 1) ? BUF_PCLK_SENS3: BUF_PCLK_SENS2): ((i & 1) ?BUF_PCLK_SENS1: BUF_PCLK_SENS0)),
.BUF_CLK_FB ((i & 2) ? ((i & 1) ? BUF_CLK_FB_SENS3: BUF_CLK_FB_SENS2): ((i & 1) ?BUF_CLK_FB_SENS1: BUF_CLK_FB_SENS0)),
`endif
.BUF_IPCLK1X ((i & 2) ? ((i & 1) ? BUF_IPCLK1X_SENS3:BUF_IPCLK1X_SENS2):((i & 1) ?BUF_IPCLK1X_SENS1:BUF_IPCLK1X_SENS0)),
.BUF_IPCLK2X ((i & 2) ? ((i & 1) ? BUF_IPCLK2X_SENS3:BUF_IPCLK2X_SENS2):((i & 1) ?BUF_IPCLK2X_SENS1:BUF_IPCLK2X_SENS0)),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
......
util_modules/deglitch.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> deglitch
* @file deglitch.v
* @date 2021-03-24
* @author Andrey Filippov
*
* @brief Deglitch signal
*
* @copyright Copyright (c) 2021
*
* <b>License </b>
*
* deglitch.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* deglitch.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module deglitch #(
parameter CLOCKS = 1
)(
input clk,
input rst,
input d,
output q
);
localparam WIDTH = clogb2(CLOCKS + 1);
reg q_r;
assign q = q_r;
generate
if (CLOCKS == 0) begin
always @ (posedge clk) begin
if (rst) q_r <= 0;
else q_r <= d;
end
end else begin
reg [WIDTH-1:0] cntr;
always @ (posedge clk) begin
if (rst) q_r <= 0;
else if (cntr == 0) q_r <= d;
if (rst || (d == q_r) || (cntr == 0)) cntr <= CLOCKS;
else cntr <= cntr -1;
end
end
endgenerate
function integer clogb2;
input [31:0] value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfunction
endmodule
util_modules/drp_mmcm_pll.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b> drp_mmcm_pll
* @file drp_mmcm_pll.v
* @date 2021-03-29
* @author eyesis
*
* @brief MMCME2/PLLE2 DRP control
*
* @copyright Copyright (c) 2021 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* drp_mmcm_pll.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* drp_mmcm_pll.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
/*
Read operation:
Shift 7 address bits (may ignore responses, just maintain expected out_odd_bit), big endian (MSB first)
Send "execute" (after 7 bits)
Wait for flipping of out_odd_bit (out_bit will not change, ignore it)
read 16 bit of data by
- shifting 0 (or 1);
- waiting for flipping of out_odd_bit
- reading out_bit (big endian, MSB first)
issue "execute" - will just reset state machine to inoitial state (as there were 16 - not 7 or 23 bits)
Write operation
Shift 7 address bits and 16 data bits (23 total) (may ignore responses, just maintain expected out_odd_bit), big endian (MSB first)
Send execute (after 23 bits)
- waiting for flipping of out_odd_bit (in response to the 24 bit sent), out_bit will not change, ignore it
Use mclk as DCLK
*/
module drp_mmcm_pll#(
parameter DRP_ADDRESS_LENGTH = 7,
parameter DRP_DATA_LENGTH = 16
)(
// host interface
input dclk,
input mmcm_rst, // this module is reset by mmcm_rst=0
input [1:0] cmd, // 0 - NOP, 1 - shift 0, 2 - shift 1, 3 - execute
output out_bit, // output data ( ready after execute, data bit after shift 0/shift 1
output out_odd_bit, // alternates when new out_bit is available
// mmcme2/plle2 interface
output [DRP_ADDRESS_LENGTH-1:0] daddr,
output [DRP_DATA_LENGTH-1:0] di_drp,
input [DRP_DATA_LENGTH-1:0] do_drp,
input drdy, // single pulse!
output den,
output dwe
);
localparam DRP_FULL_LENGTH = DRP_ADDRESS_LENGTH + DRP_DATA_LENGTH;
reg out_odd_bit_r = 0;
reg [4:0] bit_cntr;
reg [1:0] cmd_r;
reg [DRP_FULL_LENGTH-1:0] sr;
reg [DRP_ADDRESS_LENGTH-1:0] daddr_r;
wire shift0_w;
wire shift1_w;
wire shift_w;
wire exec_w;
wire exec_wr_w;
wire exec_rd_w;
wire exec_nop_w;
reg exec_wr_r;
reg exec_rd_r;
reg den_r;
reg dwe_r;
// reg [1:0] den_r2;
reg drdy_r;
wire busy_w;
reg [1:0] rdy_r;
wire done; // single-clock rd/wr over
reg nxt_bit_r;
reg was_read;
assign out_odd_bit = out_odd_bit_r;
assign out_bit = sr[DRP_FULL_LENGTH-1];
assign daddr = daddr_r;
assign den = den_r;
assign dwe = dwe_r;
assign shift0_w = (cmd_r == 1);
assign shift1_w = (cmd_r == 2);
assign shift_w = shift0_w || shift1_w;
assign exec_w = (cmd_r == 3);
assign exec_wr_w = exec_w && (bit_cntr == 23);
assign exec_rd_w = exec_w && (bit_cntr == 7);
assign exec_nop_w = exec_w && (bit_cntr != 23) && (bit_cntr != 7);
assign di_drp = sr[DRP_DATA_LENGTH-1:0];
assign busy_w = !mmcm_rst || exec_wr_w || exec_rd_w || exec_wr_r || exec_rd_r || den_r; // || (|den_r2);
assign done = rdy_r[0] && !rdy_r[1];
always @ (posedge dclk) begin
exec_wr_r <= mmcm_rst && exec_wr_w;
exec_rd_r <= mmcm_rst && exec_rd_w;
if (!mmcm_rst) cmd_r <= 0;
else cmd_r <= cmd;
if (!mmcm_rst || exec_w) bit_cntr <= 0;
else if (shift_w) bit_cntr <= bit_cntr + 1;
if (!mmcm_rst) out_odd_bit_r <= 0;
else if (nxt_bit_r) out_odd_bit_r <= !out_odd_bit_r;
if (exec_wr_w) daddr_r <= sr[22:16];
else if (exec_rd_w) daddr_r <= sr[6:0];
den_r <= mmcm_rst && (exec_wr_r || exec_rd_r);
// den_r2 <= {den_r2[0], den_r};
dwe_r <= mmcm_rst && exec_wr_r;
drdy_r <= drdy;
rdy_r <= {rdy_r[0], ~busy_w & (drdy_r | rdy_r[0])};
nxt_bit_r <= mmcm_rst && (shift_w || exec_nop_w || done);
if (exec_wr_r) was_read <= 0;
else if (exec_rd_r) was_read <= 1;
if (shift_w) sr[DRP_FULL_LENGTH-1:0] <= {sr[DRP_FULL_LENGTH-2:0], shift1_w};
else if (was_read && done) sr[DRP_FULL_LENGTH-1:0] <= {do_drp, sr[DRP_ADDRESS_LENGTH-1:0]}; // keep lower bits
end
endmodule
wrap/mmcm_drp.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b>mmcm_drp
* @file mmcm_phase_cntr.v
* @date 2021-03-29
* @author Andrey Filippov
*
* @brief MMCME2_ADV with DRP control
*
* @copyright Copyright (c) 2014 Elphel, Inc.
*
* <b>License:</b>
*
* mmcm_phase_cntr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mmcm_phase_cntr.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// all counters are two-clock cycle nets
module mmcm_drp#(
// parameter PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_F = 5.000, // 2.0 to 64.0 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT6_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT6_DUTY_CYCLE= 0.5,
parameter CLKOUT4_CASCADE= "FALSE", // cascades the output6 divider to the input for output 4
parameter CLKFBOUT_USE_FINE_PS = "FALSE", // Enable variable fine pase shift. Enable 1/(56*Fvco) phase inceremnts, round-robin
parameter CLKOUT0_USE_FINE_PS = "FALSE", // Same fine phase shift for all outputs where this attribute is "TRUE"
parameter CLKOUT1_USE_FINE_PS = "FALSE", // Not compatible with fractional divide
parameter CLKOUT2_USE_FINE_PS = "FALSE",
parameter CLKOUT3_USE_FINE_PS = "FALSE",
parameter CLKOUT4_USE_FINE_PS = "FALSE",
parameter CLKOUT5_USE_FINE_PS = "FALSE",
parameter CLKOUT6_USE_FINE_PS = "FALSE",
parameter CLKOUT0_DIVIDE_F = 1.000, // CLK0 outout divide, floating 1.000..128.000
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter CLKOUT6_DIVIDE = 1,
parameter COMPENSATION= "ZHOLD", // "ZHOLD",BUF_IN","EXTERNAL","INTERNAL
// ZHOLD - provide negative hold time on I/O registers
// INTERNAL - using internal compensation no deley is compensated
// EXTERNAL - external to the FPGA network is being compensated
// BUF_IN - no compensation when clock input is driveen by BUFG/BUFH/BUFR or GT
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STARTUP_WAIT = "FALSE", // Delays "DONE" signal until MMCM is locked
parameter DRP_ADDRESS_LENGTH = 7,
parameter DRP_DATA_LENGTH = 16
)
(
input clkin1, // General clock input
input clkin2, // Alternative clock input
input sel_clk2, // Clock input select (inverted from MMCME2_ADV !!!)
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input (enables DRP control)
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkout6, // output 6, HPC BUFR/BUFIO not capable
output clkout0b, // output 0, inverted
output clkout1b, // output 1, inverted
output clkout2b, // output 2, inverted
output clkout3b, // output 3, inverted
output clkfbout, // dedicate feedback output
output clkfboutb, // inverted feedback output
output locked, // PLL locked output
output clkin_stopped,
output clkfb_stopped,
// interface for the DRP (2 input bits, 2 output bits)
input drp_clk, // connect to mclk in x393
input [1:0] drp_cmd, // 0 - NOP, 1 - shift 0, 2 - shift 1, 3 - execute
output drp_out_bit, // output data ( ready after execute, data bit after shift 0/shift 1
output drp_out_odd_bit // alternates when new out_bit is available
);
wire [DRP_ADDRESS_LENGTH-1:0] drp_addr;
wire drp_den;
wire drp_dwe;
wire drp_drdy;
wire [DRP_DATA_LENGTH-1:0] drp_di;
wire [DRP_DATA_LENGTH-1:0] drp_do;
drp_mmcm_pll #(
.DRP_ADDRESS_LENGTH (DRP_ADDRESS_LENGTH),
.DRP_DATA_LENGTH (DRP_DATA_LENGTH)
) drp_mmcm_pll_i (
.dclk (drp_clk), // input
.mmcm_rst (rst), // input
.cmd (drp_cmd), // input[1:0]
.out_bit (drp_out_bit), // output
.out_odd_bit (drp_out_odd_bit), // output
.daddr (drp_addr), // output[6:0]
.di_drp (drp_di), // output[15:0]
.do_drp (drp_do), // input[15:0]
.drdy (drp_drdy), // input
.den (drp_den), // output
.dwe (drp_dwe) // output
);
MMCME2_ADV #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKFBOUT_USE_FINE_PS(CLKFBOUT_USE_FINE_PS),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKIN2_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_USE_FINE_PS (CLKOUT0_USE_FINE_PS),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT1_USE_FINE_PS (CLKOUT1_USE_FINE_PS),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT2_USE_FINE_PS (CLKOUT2_USE_FINE_PS),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT3_USE_FINE_PS (CLKOUT3_USE_FINE_PS),
.CLKOUT4_CASCADE (CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT4_USE_FINE_PS (CLKOUT4_USE_FINE_PS),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.CLKOUT5_USE_FINE_PS (CLKOUT5_USE_FINE_PS),
.CLKOUT6_DIVIDE (CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE (CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE (CLKOUT6_PHASE),
.CLKOUT6_USE_FINE_PS (CLKOUT6_USE_FINE_PS),
.COMPENSATION (COMPENSATION),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.REF_JITTER2 (REF_JITTER2),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.STARTUP_WAIT (STARTUP_WAIT)
) MMCME2_ADV_i (
.CLKFBOUT (clkfbout), // output
.CLKFBOUTB (clkfboutb), // output
.CLKFBSTOPPED (clkfb_stopped), // output
.CLKINSTOPPED (clkin_stopped), // output
.CLKOUT0 (clkout0), // output
.CLKOUT0B (clkout0b), // output
.CLKOUT1 (clkout1), // output
.CLKOUT1B (clkout1b), // output
.CLKOUT2 (clkout2), // output
.CLKOUT2B (clkout2b), // output
.CLKOUT3 (clkout3), // output
.CLKOUT3B (clkout3b), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.CLKOUT6 (clkout6), // output
.LOCKED (locked), // output
.PSDONE (), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin1), // input
.CLKIN2 (clkin2), // input
.CLKINSEL (~sel_clk2), // input 0: Select CLKIN2, 1: Select CLKIN1 !!!!!!!!!!!!!
.PSCLK (1'b0), // psclk), // input
.PSEN (1'b0), // psen), // input
.PSINCDEC (1'b0), // psincdec), // input
.PWRDWN (pwrdwn), // input
.RST (rst), // input
.DADDR (drp_addr), // Dynamic reconfiguration address (input[6:0])
.DCLK (drp_clk), // Dynamic reconfiguration clock input
.DEN (drp_den), // Dynamic reconfiguration enable input
.DWE (drp_dwe), // Dynamic reconfiguration Write Enable input
.DRDY (drp_drdy), // Dynamic reconfiguration ready output
.DI (drp_di), // Dynamic reconfiguration data (input[15:0])
.DO (drp_do) // Dynamic reconfiguration data (output[15:0])
);
endmodule
wrap/pll_drp.v 0 → 100644
View file @ ad1c2b04
/*!
* <b>Module:</b>pll_base
* @file pll_drp.v
* @date 2021-03-29
* @author Andrey Filippov
*
* @brief PLLE2_ADV wrapper for PLL_BASE functionality with DRP contol
*
* @copyright Copyright (c) 2014 Elphel, Inc.
*
* <b>License:</b>
*
* pll_base.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pll_base.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module pll_drp#(
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", // "OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT = 1, // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT0_DIVIDE = 1, // CLK0 outout divide, integer 1..128
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE", // Delays "DONE" signal until MMCM is locked
parameter DRP_ADDRESS_LENGTH = 7,
parameter DRP_DATA_LENGTH = 16
)
(
input clkin, // General clock input
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkfbout, // dedicate feedback output
output locked, // PLL locked output
// interface for the DRP (2 input bits, 2 output bits)
input drp_clk, // connect to mclk in x393
input [1:0] drp_cmd, // 0 - NOP, 1 - shift 0, 2 - shift 1, 3 - execute
output drp_out_bit, // output data ( ready after execute, data bit after shift 0/shift 1
output drp_out_odd_bit // alternates when new out_bit is available
);
wire [DRP_ADDRESS_LENGTH-1:0] drp_addr;
wire drp_den;
wire drp_dwe;
wire drp_drdy;
wire [DRP_DATA_LENGTH-1:0] drp_di;
wire [DRP_DATA_LENGTH-1:0] drp_do;
drp_mmcm_pll #(
.DRP_ADDRESS_LENGTH (DRP_ADDRESS_LENGTH),
.DRP_DATA_LENGTH (DRP_DATA_LENGTH)
) drp_mmcm_pll_i (
.dclk (drp_clk), // input
.mmcm_rst (rst), // input
.cmd (drp_cmd), // input[1:0]
.out_bit (drp_out_bit), // output
.out_odd_bit (drp_out_odd_bit), // output
.daddr (drp_addr), // output[6:0]
.di_drp (drp_di), // output[15:0]
.do_drp (drp_do), // input[15:0]
.drdy (drp_drdy), // input
.den (drp_den), // output
.dwe (drp_dwe) // output
);
PLLE2_ADV #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_ADV_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst), // input
// Unused ports for advanced option
// Unused second clock input and select
.CLKIN2 (1'b0), // input
.CLKINSEL (1'b1), // input
// DRP I/O
.DADDR (drp_addr), // Dynamic reconfiguration address (input[6:0])
.DCLK (drp_clk), // Dynamic reconfiguration clock input
.DEN (drp_den), // Dynamic reconfiguration enable input
.DWE (drp_dwe), // Dynamic reconfiguration Write Enable input
.DRDY (drp_drdy), // Dynamic reconfiguration ready output
.DI (drp_di), // Dynamic reconfiguration data (input[15:0])
.DO (drp_do) // Dynamic reconfiguration data (output[15:0])
);
endmodule
x393.v
View file @ ad1c2b04
......@@ -1871,6 +1871,7 @@ assign axi_grst = axi_rst_pre;
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_CTRL_DPR (SENS_CTRL_DPR), // eventually use for all sensors, not just Boson
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
......@@ -2013,16 +2014,29 @@ assign axi_grst = axi_rst_pre;
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
`ifdef BOSON
.PCLK_PHASE (PCLK_PHASE),
`endif
.IPCLK1X_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.BUF_IPCLK_SENS0 (BUF_IPCLK_SENS0),
`ifdef BOSON
.BUF_PCLK_SENS0 (BUF_PCLK_SENS0),
.BUF_CLK_FB_SENS0 (BUF_CLK_FB_SENS0),
.BUF_PCLK_SENS1 (BUF_PCLK_SENS1),
.BUF_CLK_FB_SENS1 (BUF_CLK_FB_SENS1),
.BUF_PCLK_SENS2 (BUF_PCLK_SENS2),
.BUF_CLK_FB_SENS2 (BUF_CLK_FB_SENS2),
.BUF_PCLK_SENS3 (BUF_PCLK_SENS3),
.BUF_CLK_FB_SENS3 (BUF_CLK_FB_SENS3),
`endif
.BUF_IPCLK1X_SENS0 (BUF_IPCLK1X_SENS0),
.BUF_IPCLK2X_SENS0 (BUF_IPCLK2X_SENS0),
.BUF_IPCLK_SENS1 (BUF_IPCLK_SENS1),
.BUF_IPCLK1X_SENS1 (BUF_IPCLK1X_SENS1),
.BUF_IPCLK2X_SENS1 (BUF_IPCLK2X_SENS1),
.BUF_IPCLK_SENS2 (BUF_IPCLK_SENS2),
.BUF_IPCLK1X_SENS2 (BUF_IPCLK1X_SENS2),
.BUF_IPCLK2X_SENS2 (BUF_IPCLK2X_SENS2),
.BUF_IPCLK_SENS3 (BUF_IPCLK_SENS3),
.BUF_IPCLK1X_SENS3 (BUF_IPCLK1X_SENS3),
.BUF_IPCLK2X_SENS3 (BUF_IPCLK2X_SENS3),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......
x393_boson.bit
View file @ ad1c2b04
No preview for this file type
x393_boson.timing_summary_impl 0 → 100644
View file @ ad1c2b04
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_boson_utilization.report 0 → 100644
View file @ ad1c2b04
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Tue Mar 30 18:19:38 2021
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_boson_utilization.report
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
-------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 43590 | 0 | 78600 | 55.46 |
| LUT as Logic | 40218 | 0 | 78600 | 51.17 |
| LUT as Memory | 3372 | 0 | 26600 | 12.68 |
| LUT as Distributed RAM | 2834 | 0 | | |
| LUT as Shift Register | 538 | 0 | | |
| Slice Registers | 55947 | 0 | 157200 | 35.59 |
| Register as Flip Flop | 55947 | 0 | 157200 | 35.59 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 16 | Yes | - | Set |
| 676 | Yes | - | Reset |
| 1215 | Yes | Set | - |
| 54040 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16994 | 0 | 19650 | 86.48 |
| SLICEL | 11201 | 0 | | |
| SLICEM | 5793 | 0 | | |
| LUT as Logic | 40218 | 0 | 78600 | 51.17 |
| using O5 output only | 5 | | | |
| using O6 output only | 31260 | | | |
| using O5 and O6 | 8953 | | | |
| LUT as Memory | 3372 | 0 | 26600 | 12.68 |
| LUT as Distributed RAM | 2834 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2748 | | | |
| LUT as Shift Register | 538 | 0 | | |
| using O5 output only | 258 | | | |
| using O6 output only | 225 | | | |
| using O5 and O6 | 55 | | | |
| LUT Flip Flop Pairs | 25490 | 0 | 78600 | 32.43 |
| fully used LUT-FF pairs | 4916 | | | |
| LUT-FF pairs with one unused LUT output | 18340 | | | |
| LUT-FF pairs with one unused Flip Flop | 18216 | | | |
| Unique Control Sets | 5213 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 91 | 0 | 265 | 34.34 |
| RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 54 | | | |
| RAMB18 | 74 | 0 | 530 | 13.96 |
| RAMB18E1 only | 74 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 18 | 18 | 155 | 11.61 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 30 | 30 | 250 | 12.00 |
| IDELAYE2 only | 12 | 12 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 28 | 28 | 163 | 17.18 |
| ISERDES | 28 | 28 | | |
| OLOGIC | 44 | 44 | 163 | 26.99 |
| OUTFF_ODDR_Register | 1 | 1 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL | 15 | 0 | 32 | 46.88 |
| BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 3 | 0 | 5 | 60.00 |
| PLLE2_ADV | 3 | 0 | 5 | 60.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 8 | 0 | 20 | 40.00 |
+--------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 54040 | Flop & Latch |
| LUT3 | 11867 | LUT |
| LUT6 | 10465 | LUT |
| LUT2 | 8616 | LUT |
| LUT4 | 8437 | LUT |
| LUT5 | 8158 | LUT |
| RAMD32 | 4174 | Distributed Memory |
| CARRY4 | 2805 | CarryLogic |
| LUT1 | 1628 | LUT |
| RAMS32 | 1408 | Distributed Memory |
| FDSE | 1215 | Flop & Latch |
| FDCE | 676 | Flop & Latch |
| SRL16E | 489 | Distributed Memory |
| SRLC32E | 104 | Distributed Memory |
| DSP48E1 | 76 | Block Arithmetic |
| RAMB18E1 | 74 | Block Memory |
| OBUFT | 69 | IO |
| IBUF | 59 | IO |
| RAMB36E1 | 54 | Block Memory |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 30 | MuxFx |
| ISERDESE2 | 28 | IO |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| IBUFDS | 18 | IO |
| FDPE | 16 | Flop & Latch |
| BUFG | 15 | Clock |
| PULLUP | 12 | I/O |
| IDELAYE2 | 12 | IO |
| OBUF | 11 | IO |
| BUFR | 8 | Clock |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| PLLE2_ADV | 3 | Clock |
| MMCME2_ADV | 3 | Clock |
| INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| OBUFTDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| ODDR | 1 | IO |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
x393_placement-true.tcl 0 → 100644
View file @ ad1c2b04
#################################################################################
# Filename: x393_placement.tcl
# Date:2016-03-28
# Author: Andrey Filippov
# Description: Placementg constraints (selected by HISPI parameter in system_devines.vh)
#
# Copyright (c) 2016 Elphel, Inc.
# x393_placement.tcl is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_placement.tcl is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any encrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
cd ~/vdt/x393
set infile [open "system_defines.vh" r]
set HISPI 0
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)HISPI} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set HISPI 1
break
}
}
set LWIR 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)LWIR} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set LWIR 1
break
}
}
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile
if { $LWIR} {
puts "x393_placement.tcl: using LWIR sensors"
} elseif { $HISPI} {
puts "x393_placement.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else {
puts "x393_placement.tcl: using parallel sensors"
}
#Placement constraints (I/O pads)
set_property PACKAGE_PIN J4 [get_ports {SDRST}]
set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
set_property PACKAGE_PIN G4 [get_ports {SDWE}]
set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
set_property PACKAGE_PIN M7 [get_ports {SDODT}]
set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
set_property PACKAGE_PIN N7 [get_ports {DQSL}]
set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
set_property PACKAGE_PIN H7 [get_ports {DQSU}]
set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
set_property PACKAGE_PIN L5 [get_ports {SDDML}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
#not yet used, just for debugging
set_property PACKAGE_PIN M5 [get_ports {memclk}]
# ======== GPIO pins ===============
# inout [GPIO_N-1:0] gpio_pins,
set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}]
set_property PACKAGE_PIN A4 [get_ports {gpio_pins[1]}]
set_property PACKAGE_PIN A2 [get_ports {gpio_pins[2]}]
set_property PACKAGE_PIN A1 [get_ports {gpio_pins[3]}]
set_property PACKAGE_PIN C3 [get_ports {gpio_pins[4]}]
set_property PACKAGE_PIN D3 [get_ports {gpio_pins[5]}]
set_property PACKAGE_PIN D1 [get_ports {gpio_pins[6]}]
set_property PACKAGE_PIN C1 [get_ports {gpio_pins[7]}]
set_property PACKAGE_PIN C2 [get_ports {gpio_pins[8]}]
set_property PACKAGE_PIN B2 [get_ports {gpio_pins[9]}]
# =========Differential clock inputs ==========
# input ffclk0p, // Y12
# input ffclk0n, // Y11
# input ffclk1p, // W14
# input ffclk1n // W13
set_property PACKAGE_PIN Y12 [get_ports {ffclk0p}]
set_property PACKAGE_PIN Y11 [get_ports {ffclk0n}]
set_property PACKAGE_PIN W14 [get_ports {ffclk1p}]
set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
# ================= Sensor port 0 =================
# BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp40[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn40[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp40[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn40[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp40[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn40[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp40[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn40[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp40[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn40[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp5}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn5}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp76[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn76[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp76[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn76[7]}]
} elseif { $HISPI } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}]
} else {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
}
set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 =================
# BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp40[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn40[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp40[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn40[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp40[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn40[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp40[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn40[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp40[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn40[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp5}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn5}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp76[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn76[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp76[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn76[7]}]
} elseif { $HISPI } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}]
} else {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}]
}
set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 =================
# BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp40[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn40[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp40[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn40[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp40[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn40[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp40[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn40[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp40[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn40[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp5}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn5}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp76[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn76[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp76[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn76[7]}]
} elseif { $HISPI } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}]
} else {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}]
}
set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 =================
if { $BOSON } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp40[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn40[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp40[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn40[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp40[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn40[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp40[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn40[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp40[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn40[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp5}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn5}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp76[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn76[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp76[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn76[7]}]
} elseif { $HISPI } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}]
} else {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}]
}
set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
# ===================== SATA ======================
# bind gtx reference clock
set_property PACKAGE_PIN U6 [get_ports EXTCLK_P]
set_property PACKAGE_PIN U5 [get_ports EXTCLK_N]
# bind sata inputs/outputs
set_property PACKAGE_PIN AA5 [get_ports RXN]
set_property PACKAGE_PIN AA6 [get_ports RXP]
set_property PACKAGE_PIN AB3 [get_ports TXN]
set_property PACKAGE_PIN AB4 [get_ports TXP]
if { $BOSON } {
# set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/*E2_ADV_i"}]
set_msg_config -id "Vivado 12-180" -suppress
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
reset_msg_config -id "Vivado 12-180" -suppress
#debugging:
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
}
x393_placement.tcl
View file @ ad1c2b04
......@@ -473,3 +473,45 @@ set_property PACKAGE_PIN AA5 [get_ports RXN]
set_property PACKAGE_PIN AA6 [get_ports RXP]
set_property PACKAGE_PIN AB3 [get_ports TXN]
set_property PACKAGE_PIN AB4 [get_ports TXP]
if { $BOSON } {
# set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/*E2_ADV_i"}]
# set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/*E2_ADV_i"}]
if { $LWIR} {
set_msg_config -id "Vivado 12-180" -suppress
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[0]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y0 [get_cells -hier -filter {NAME=~"*sensor_channel_block[1]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[2]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
if {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/MMCME2_ADV_i"}]]!=0} {
set_property LOC MMCME2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/MMCME2_ADV_i"}]
} elseif {[llength [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/PLLE2_ADV_i"}]]!=0} {
set_property LOC PLLE2_ADV_X0Y1 [get_cells -hier -filter {NAME=~"*sensor_channel_block[3]*/mmcm_or_pll_i/PLLE2_ADV_i"}]
}
reset_msg_config -id "Vivado 12-180" -suppress
}
#debugging:
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[1].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ibufds_ibufgds0_i/clk_in]
}
x393_timing.tcl
View file @ ad1c2b04
......@@ -105,11 +105,16 @@ if { $BOSON} {
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk2x_pre ]
#only for lanes (not l3)
create_generated_clock -name iclk1x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
create_generated_clock -name iclk1x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
create_generated_clock -name iclk1x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
create_generated_clock -name iclk1x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_103993_i/sens_103993_l3_i/sens_103993_clock_i/ipclk1x_pre ]
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0 iclk1x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1 iclk1x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2 iclk1x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3 iclk1x3}
} elseif { $LWIR} {
# Nothing here yet
......
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