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x393
Commit ad0351ef authored by Andrey Filippov's avatar Andrey Filippov
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re-organized top structure

parent f35bb39d
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Showing with 3396 additions and 1842 deletions
.editor_defines.vh
View file @ ad0351ef
......@@ -2,41 +2,50 @@
// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
`define IVERILOG 1
`undef DEBUG_FIFO
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
// `define IVERILOG
// defines for memory channels
// chn 0 is read from memory
// chn 0 is read from memory and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is write to memory
`define def_enable_mem_chn1
`undef def_read_mem_chn1
`undef def_scanline_chn1
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is read from memory
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_scanline_chn2
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is write to memory
`define def_enable_mem_chn3
`undef def_read_mem_chn3
`define def_scanline_chn3
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is enabled
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_tiled_chn4
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is enabled
`define def_enable_mem_chn5
`undef def_read_mem_chn5
`define def_tiled_chn5
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
......
address_map.txt
View file @ ad0351ef
......@@ -142,9 +142,10 @@
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0,//8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1,//8 or less bits: status register address to use for memory controller
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR='h4,
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h6,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
......
axi/axibram_write.v
View file @ ad0351ef
......@@ -20,6 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
//`define DEBUG_FIFO 1
`undef DEBUG_FIFO
module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
......
includes/x393_parameters.vh
View file @ ad0351ef
......@@ -23,11 +23,20 @@
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
// parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
// parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
// parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
// parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
// parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h0800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_WR_ADDR = 'h0c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
......@@ -181,7 +190,7 @@
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
......@@ -194,17 +203,18 @@
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h6,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -217,7 +227,8 @@
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......@@ -228,16 +239,16 @@
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4
\ No newline at end of file
includes/x393_tasks01.vh
View file @ ad0351ef
......@@ -20,8 +20,10 @@
*******************************************************************************/
// Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task write_contol_register;
input [29:0] reg_addr;
// input integer reg_addr;
input [31:0] data;
begin
axi_write_single_w(CONTROL_ADDR+reg_addr, data);
......
includes/x393_tasks_mcntrl_buffers.vh
View file @ ad0351ef
......@@ -31,11 +31,11 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
begin
$display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_words, $time);
case (chn)
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
1: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
end
endcase
// write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
......@@ -84,12 +84,14 @@ task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
reg [29:0] start_addr;
begin
case (chn)
0: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
5: start_addr=MCONTR_BUF5_WR_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
end
endcase
write_block_buf (start_addr, num_words);
......@@ -106,7 +108,7 @@ task write_block_buf;
axi_write_addr_data(
i, // id
{start_word_address,2'b0}+( i << 2),
// (MCONTR_BUF1_WR_ADDR + (page <<8)+ i) << 2, // addr
// (MCONTR_BUF0_WR_ADDR + (page <<8)+ i) << 2, // addr
i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24),
4'hf, // len
1, // burst type - increment
......@@ -131,7 +133,8 @@ endtask
// read memory
task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
// input integer chn; // buffer channel
input [3:0] chn; // buffer channel
input [1:0] page;
input integer num_read; // number of words to read (will be rounded up to multiple of 16)
input wait_done;
......@@ -139,7 +142,9 @@ task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
begin
case (chn)
0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
1: start_addr=MCONTR_BUF1_RD_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for read buffer = %d @%t", chn, $time);
......
includes/x393_tasks_mcntrl_en_dis_priority.vh
View file @ ad0351ef
......@@ -57,10 +57,25 @@ endtask
task enable_memcntrl_channels;
input [15:0] chnen; // bit-per-channel, 1 - enable;
begin
ENABLED_CHANNELS = chnen; // currently enabled memory channels
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,chnen});
end
endtask
task enable_memcntrl_en_dis;
input [3:0] chn;
input en;
begin
if (en) begin
ENABLED_CHANNELS = ENABLED_CHANNELS | (1<<chn);
end else begin
ENABLED_CHANNELS = ENABLED_CHANNELS & ~(1<<chn);
end
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
end
endtask
task configure_channel_priority;
input [ 3:0] chn;
input [15:0] priority; // (higher is more important)
......
includes/x393_tasks_status.vh
View file @ ad0351ef
......@@ -60,13 +60,14 @@ endtask
read_and_wait_status (MCONTR_PHY_STATUS_REG_ADDR);
read_and_wait_status (MCONTR_TOP_STATUS_REG_ADDR);
read_and_wait_status (MCNTRL_PS_STATUS_REG_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR);
read_and_wait_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TILED_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR);
end
endtask
......@@ -86,14 +87,14 @@ endtask
program_status (MCONTR_PHY_16BIT_ADDR, MCONTR_PHY_STATUS_CNTRL, mode,seq_num); //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
program_status (MCONTR_TOP_16BIT_ADDR, MCONTR_TOP_16BIT_STATUS_CNTRL, mode,seq_num); //MCONTR_TOP_STATUS_REG_ADDR= 'h1,
program_status (MCNTRL_PS_ADDR, MCNTRL_PS_STATUS_CNTRL, mode,seq_num); //MCNTRL_PS_STATUS_REG_ADDR= 'h2,
program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN1_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN2_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TILED_CHN5_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN5_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f,
end
endtask
......
memctrl/cmd_encod_4mux.v 0 → 100644
View file @ ad0351ef
/*******************************************************************************
* Module: cmd_encod_4mux
* Date:2015-02-21
* Author: andrey
* Description: 4-to-1 mux to cmbine memory sequences sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_4mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_4mux.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmd_encod_4mux(
input rst,
input clk,
input start0, // this channel was started
input [31:0] enc_cmd0, // encoded commnad
input enc_wr0, // write encoded command
input enc_done0, // encoding finished
input start1, // this channel was started
input [31:0] enc_cmd1, // encoded commnad
input enc_wr1, // write encoded command
input enc_done1, // encoding finished
input start2, // this channel was started
input [31:0] enc_cmd2, // encoded commnad
input enc_wr2, // write encoded command
input enc_done2, // encoding finished
input start3, // this channel was started
input [31:0] enc_cmd3, // encoded commnad
input enc_wr3, // write encoded command
input enc_done3, // encoding finished
output reg start, // combined output was started (1 clk from |start*)
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
reg [3:0] select;
wire start_w= start0 | start1 |start2 | start3;
always @ (posedge rst or posedge clk) begin
if (rst) start <= 0;
else start <= start_w;
if (rst) select <= 0;
else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed
start3 & ~start2 & ~start1 & ~start0,
start2 & ~start1 & ~start0,
start1 & ~start0,
start0};
end
always @(posedge clk) begin
enc_cmd <= ({32{select[0]}} & enc_cmd0) |
({32{select[1]}} & enc_cmd1) |
({32{select[2]}} & enc_cmd2) |
({32{select[3]}} & enc_cmd3);
enc_wr <= (select[0] & enc_wr0) |
(select[1] & enc_wr1) |
(select[2] & enc_wr2) |
(select[3] & enc_wr3);
enc_done <= (select[0] & enc_done0) |
(select[1] & enc_done1) |
(select[2] & enc_done2) |
(select[3] & enc_done3);
end
endmodule
memctrl/cmd_encod_linear_mux.v
View file @ ad0351ef
......@@ -33,7 +33,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col0, // start memory column in 8-bursts
input [5:0] num128_0, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial0, // first of the two halves of a split tile (caused by memory page crossing)
input start0, // start generating commands
`ifdef def_read_mem_chn0
input start0_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn0
input start0_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn1
input [2:0] bank1, // bank address
......@@ -41,7 +46,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col1, // start memory column in 8-bursts
input [5:0] num128_1, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial1, // first of the two halves of a split tile (caused by memory page crossing)
input start1, // start generating commands
`ifdef def_read_mem_chn1
input start1_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn1
input start1_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn2
input [2:0] bank2, // bank address
......@@ -49,7 +59,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col2, // start memory column in 8-bursts
input [5:0] num128_2, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial2, // first of the two halves of a split tile (caused by memory page crossing)
input start2, // start generating commands
`ifdef def_read_mem_chn2
input start2_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn2
input start2_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn3
input [2:0] bank3, // bank address
......@@ -57,7 +72,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col3, // start memory column in 8-bursts
input [5:0] num128_3, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial3, // first of the two halves of a split tile (caused by memory page crossing)
input start3, // start generating commands
`ifdef def_read_mem_chn3
input start3_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn3
input start3_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn4
input [2:0] bank4, // bank address
......@@ -65,8 +85,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col4, // start memory column in 8-bursts
input [5:0] num128_4, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial4, // first of the two halves of a split tile (caused by memory page crossing)
input start4, // start generating commands
`ifdef def_read_mem_chn4
input start4_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn4
input start4_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn5
input [2:0] bank5, // bank address
......@@ -74,8 +98,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col5, // start memory column in 8-bursts
input [5:0] num128_5, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial5, // first of the two halves of a split tile (caused by memory page crossing)
input start5, // start generating commands
`ifdef def_read_mem_chn5
input start5_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn5
input start5_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn6
input [2:0] bank6, // bank address
......@@ -83,7 +111,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col6, // start memory column in 8-bursts
input [5:0] num128_6, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial6, // first of the two halves of a split tile (caused by memory page crossing)
input start6, // start generating commands
`ifdef def_read_mem_chn6
input start6_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn6
input start6_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn7
input [2:0] bank7, // bank address
......@@ -91,7 +124,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col7, // start memory column in 8-bursts
input [5:0] num128_7, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial7, // first of the two halves of a split tile (caused by memory page crossing)
input start7, // start generating commands
`ifdef def_read_mem_chn7
input start7_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn7
input start7_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn8
input [2:0] bank8, // bank address
......@@ -99,7 +137,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col8, // start memory column in 8-bursts
input [5:0] num128_8, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial8, // first of the two halves of a split tile (caused by memory page crossing)
input start8, // start generating commands
`ifdef def_read_mem_chn8
input start8_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn8
input start8_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn9
input [2:0] bank9, // bank address
......@@ -107,7 +150,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col9, // start memory column in 8-bursts
input [5:0] num128_9, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial9, // first of the two halves of a split tile (caused by memory page crossing)
input start9, // start generating commands
`ifdef def_read_mem_chn9
input start9_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn9
input start9_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn10
input [2:0] bank10, // bank address
......@@ -115,7 +163,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col10, // start memory column in 8-bursts
input [5:0] num128_10, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial10, // first of the two halves of a split tile (caused by memory page crossing)
input start10, // start generating commands
`ifdef def_read_mem_chn10
input start10_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn10
input start10_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn11
input [2:0] bank11, // bank address
......@@ -123,7 +176,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col11, // start memory column in 8-bursts
input [5:0] num128_11, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial11, // first of the two halves of a split tile (caused by memory page crossing)
input start11, // start generating commands
`ifdef def_read_mem_chn11
input start11_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn11
input start11_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn12
input [2:0] bank12, // bank address
......@@ -131,7 +189,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col12, // start memory column in 8-bursts
input [5:0] num128_12, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial12, // first of the two halves of a split tile (caused by memory page crossing)
input start12, // start generating commands
`ifdef def_read_mem_chn12
input start12_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn12
input start12_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn13
input [2:0] bank13, // bank address
......@@ -139,7 +202,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col13, // start memory column in 8-bursts
input [5:0] num128_13, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial13, // first of the two halves of a split tile (caused by memory page crossing)
input start13, // start generating commands
`ifdef def_read_mem_chn13
input start13_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn13
input start13_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn14
input [2:0] bank14, // bank address
......@@ -147,7 +215,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col14, // start memory column in 8-bursts
input [5:0] num128_14, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial14, // first of the two halves of a split tile (caused by memory page crossing)
input start14, // start generating commands
`ifdef def_read_mem_chn14
input start14_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn14
input start14_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_scanline_chn15
input [2:0] bank15, // bank address
......@@ -155,7 +228,12 @@ module cmd_encod_linear_mux#(
input [COLADDR_NUMBER-4:0] start_col15, // start memory column in 8-bursts
input [5:0] num128_15, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input partial15, // first of the two halves of a split tile (caused by memory page crossing)
input start15, // start generating commands
`ifdef def_read_mem_chn15
input start15_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn15
input start15_wr, // start generating memory write channel commands
`endif
`endif
output [2:0] bank, // bank address
output [ADDRESS_NUMBER-1:0] row, // memory row
......@@ -181,7 +259,7 @@ module cmd_encod_linear_mux#(
wire start_rd_w; // start generating commands
wire start_wr_w; // start generating commands
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+2+1;
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+1;
localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0;
assign bank = bank_r;
assign row = row_r;
......@@ -190,137 +268,384 @@ module cmd_encod_linear_mux#(
assign partial= partial_r;
assign start_rd = start_rd_r;
assign start_wr = start_wr_r;
localparam [15:0] CHN_RD_MEM={
`ifdef def_read_mem_chn15
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn14
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn13
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn12
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn11
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn10
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn9
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn8
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn7
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn6
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn5
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn4
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn3
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn2
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn1
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn0
1'b1};
`else
1'b0};
`endif
assign start_rd_w= 0
`ifdef def_scanline_chn0
`ifdef def_read_mem_chn0
| start0_rd
`endif
`endif
`ifdef def_scanline_chn1
`ifdef def_read_mem_chn1
| start1_rd
`endif
`endif
`ifdef def_scanline_chn2
`ifdef def_read_mem_chn2
| start2_rd
`endif
`endif
`ifdef def_scanline_chn3
`ifdef def_read_mem_chn3
| start3_rd
`endif
`endif
`ifdef def_scanline_chn4
`ifdef def_read_mem_chn4
| start4_rd
`endif
`endif
`ifdef def_scanline_chn5
`ifdef def_read_mem_chn5
| start5_rd
`endif
`endif
`ifdef def_scanline_chn6
`ifdef def_read_mem_chn6
| start6_rd
`endif
`endif
`ifdef def_scanline_chn7
`ifdef def_read_mem_chn7
| start7_rd
`endif
`endif
`ifdef def_scanline_chn8
`ifdef def_read_mem_chn8
| start8_rd
`endif
`endif
`ifdef def_scanline_chn9
`ifdef def_read_mem_chn9
| start9_rd
`endif
`endif
`ifdef def_scanline_chn10
`ifdef def_read_mem_chn10
| start10_rd
`endif
`endif
`ifdef def_scanline_chn11
`ifdef def_read_mem_chn11
| start11_rd
`endif
`endif
`ifdef def_scanline_chn12
`ifdef def_read_mem_chn12
| start12_rd
`endif
`endif
`ifdef def_scanline_chn13
`ifdef def_read_mem_chn13
| start13_rd
`endif
`endif
`ifdef def_scanline_chn14
`ifdef def_read_mem_chn14
| start14_rd
`endif
`endif
`ifdef def_scanline_chn15
`ifdef def_read_mem_chn15
| start15_rd
`endif
`endif
;
assign start_wr_w= 0
`ifdef def_scanline_chn0
`ifdef def_write_mem_chn0
| start0_wr
`endif
`endif
`ifdef def_scanline_chn1
`ifdef def_write_mem_chn1
| start1_wr
`endif
`endif
`ifdef def_scanline_chn2
`ifdef def_write_mem_chn2
| start2_wr
`endif
`endif
`ifdef def_scanline_chn3
`ifdef def_write_mem_chn3
| start3_wr
`endif
`endif
`ifdef def_scanline_chn4
`ifdef def_write_mem_chn4
| start4_wr
`endif
`endif
`ifdef def_scanline_chn5
`ifdef def_write_mem_chn5
| start5_wr
`endif
`endif
`ifdef def_scanline_chn6
`ifdef def_write_mem_chn6
| start6_wr
`endif
`endif
`ifdef def_scanline_chn7
`ifdef def_write_mem_chn7
| start7_wr
`endif
`endif
`ifdef def_scanline_chn8
`ifdef def_write_mem_chn8
| start8_wr
`endif
`endif
`ifdef def_scanline_chn9
`ifdef def_write_mem_chn9
| start9_wr
`endif
`endif
`ifdef def_scanline_chn10
`ifdef def_write_mem_chn10
| start10_wr
`endif
`endif
`ifdef def_scanline_chn11
`ifdef def_write_mem_chn11
| start11_wr
`endif
`endif
`ifdef def_scanline_chn12
`ifdef def_write_mem_chn12
| start12_wr
`endif
`endif
`ifdef def_scanline_chn13
`ifdef def_write_mem_chn13
| start13_wr
`endif
`endif
`ifdef def_scanline_chn14
`ifdef def_write_mem_chn14
| start14_wr
`endif
`endif
`ifdef def_scanline_chn15
`ifdef def_write_mem_chn15
| start15_wr
`endif
`endif
;
`ifdef def_scanline_chn0
wire start0=0 |
`ifdef def_read_mem_chn0
| start0_rd
`endif
`ifdef def_write_mem_chn0
| start0_wr
`endif
;
`endif
`ifdef def_scanline_chn1
wire start1=0 |
`ifdef def_read_mem_chn1
| start1_rd
`endif
`ifdef def_write_mem_chn1
| start1_wr
`endif
;
`endif
`ifdef def_scanline_chn2
wire start2=0 |
`ifdef def_read_mem_chn2
| start2_rd
`endif
`ifdef def_write_mem_chn2
| start2_wr
`endif
;
`endif
`ifdef def_scanline_chn3
wire start3=0 |
`ifdef def_read_mem_chn3
| start3_rd
`endif
`ifdef def_write_mem_chn3
| start3_wr
`endif
;
`endif
`ifdef def_scanline_chn4
wire start4=0 |
`ifdef def_read_mem_chn4
| start4_rd
`endif
`ifdef def_write_mem_chn4
| start4_wr
`endif
;
`endif
`ifdef def_scanline_chn5
wire start5=0 |
`ifdef def_read_mem_chn5
| start5_rd
`endif
`ifdef def_write_mem_chn5
| start5_wr
`endif
;
`endif
`ifdef def_scanline_chn6
wire start6=0 |
`ifdef def_read_mem_chn6
| start6_rd
`endif
`ifdef def_write_mem_chn6
| start6_wr
`endif
;
`endif
`ifdef def_scanline_chn7
wire start7=0 |
`ifdef def_read_mem_chn7
| start7_rd
`endif
`ifdef def_write_mem_chn7
| start7_wr
`endif
;
`endif
`ifdef def_scanline_chn8
wire start8=0 |
`ifdef def_read_mem_chn8
| start8_rd
`endif
`ifdef def_write_mem_chn8
| start8_wr
`endif
;
`endif
`ifdef def_scanline_chn9
wire start9=0 |
`ifdef def_read_mem_chn9
| start9_rd
`endif
`ifdef def_write_mem_chn9
| start9_wr
`endif
;
`endif
`ifdef def_scanline_chn10
wire start10=0 |
`ifdef def_read_mem_chn10
| start10_rd
`endif
`ifdef def_write_mem_chn10
| start10_wr
`endif
;
`endif
`ifdef def_scanline_chn11
wire start11=0 |
`ifdef def_read_mem_chn11
| start11_rd
`endif
`ifdef def_write_mem_chn11
| start11_wr
`endif
;
`endif
`ifdef def_scanline_chn12
wire start12=0 |
`ifdef def_read_mem_chn12
| start12_rd
`endif
`ifdef def_write_mem_chn12
| start12_wr
`endif
;
`endif
`ifdef def_scanline_chn13
wire start13=0 |
`ifdef def_read_mem_chn13
| start13_rd
`endif
`ifdef def_write_mem_chn13
| start13_wr
`endif
;
`endif
`ifdef def_scanline_chn14
wire start14=0 |
`ifdef def_read_mem_chn14
| start14_rd
`endif
`ifdef def_write_mem_chn14
| start14_wr
`endif
;
`endif
`ifdef def_scanline_chn15
wire start15=0 |
`ifdef def_read_mem_chn15
| start15_rd
`endif
`ifdef def_write_mem_chn15
| start15_wr
`endif
;
`endif
assign {bank_w, row_w, start_col_w, num128_w, partial_w, start_rd_w, start_wr_w} = 0
assign {bank_w, row_w, start_col_w, num128_w, partial_w} = 0
`ifdef def_scanline_chn0
| (start0?{bank0, row0, start_col0, num128_0, partial0, CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
| (start0?{bank0, row0, start_col0, num128_0, partial0}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn1
| (start1?{bank1, row1, start_col1, num128_1, partial1, CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
| (start1?{bank1, row1, start_col1, num128_1, partial1}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn2
| (start2?{bank2, row2, start_col2, num128_2, partial2, CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
| (start2?{bank2, row2, start_col2, num128_2, partial2}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn3
| (start3?{bank3, row3, start_col3, num128_3, partial3, CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
| (start3?{bank3, row3, start_col3, num128_3, partial3}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn4
| (start4?{bank4, row4, start_col4, num128_4, partial4, CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
| (start4?{bank4, row4, start_col4, num128_4, partial4}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn5
| (start5?{bank5, row5, start_col5, num128_5, partial5, CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
| (start5?{bank5, row5, start_col5, num128_5, partial5}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn6
| (start6?{bank6, row6, start_col6, num128_6, partial6, CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
| (start6?{bank6, row6, start_col6, num128_6, partial6}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn7
| (start7?{bank7, row7, start_col7, num128_7, partial7, CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
| (start7?{bank7, row7, start_col7, num128_7, partial7}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn8
| (start8?{bank8, row8, start_col8, num128_8, partial8, CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
| (start8?{bank8, row8, start_col8, num128_8, partial8}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn9
| (start9?{bank9, row9, start_col9, num128_9, partial9, CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
| (start9?{bank9, row9, start_col9, num128_9, partial9}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn10
| (start10?{bank10, row10, start_col10, num128_10, partial10, CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
| (start10?{bank10, row10, start_col10, num128_10, partial10}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn11
| (start11?{bank11, row11, start_col11, num128_11, partial11, CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
| (start11?{bank11, row11, start_col11, num128_11, partial11}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn12
| (start12?{bank12, row12, start_col12, num128_12, partial12, CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
| (start12?{bank12, row12, start_col12, num128_12, partial12}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn13
| (start13?{bank13, row13, start_col13, num128_13, partial13, CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
| (start13?{bank13, row13, start_col13, num128_13, partial13}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn14
| (start14?{bank14, row14, start_col14, num128_14, partial14, CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
| (start14?{bank14, row14, start_col14, num128_14, partial14}:PAR_DEFAULT)
`endif
`ifdef def_scanline_chn15
| (start15?{bank15, row15, start_col15, num128_15, partial15, CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
| (start15?{bank15, row15, start_col15, num128_15, partial15}:PAR_DEFAULT)
`endif
;
always @ (posedge clk) begin
......
memctrl/cmd_encod_linear_rw.v 0 → 100644
View file @ ad0351ef
/*******************************************************************************
* Module: cmd_encod_linear_rw
* Date:2015-02-21
* Author: andrey
* Description: Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_linear_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_linear_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmd_encod_linear_rw#(
// parameter BASEADDR = 0,
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
) (
input rst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
// input cmd_stb, // strobe (with first byte) for the command a/d
input [2:0] bank_in, // bank address
input [ADDRESS_NUMBER-1:0] row_in, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bursts
input [NUM_XFER_BITS-1:0] num128_in, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input skip_next_page_in, // do not reset external buffer (continue)
input start_rd, // start generating commands by cmd_encod_linear_rd
input start_wr, // start generating commands by cmd_encod_linear_wr
output reg start, // this channel was started (1 clk from start_rd || start_wr
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
wire [31:0] enc_cmd_rd; // encoded commnad
wire enc_wr_rd; // write encoded command
wire enc_done_rd; // encoding finished
wire [31:0] enc_cmd_wr; // encoded commnad
wire enc_wr_wr; // write encoded command
wire enc_done_wr; // encoding finished
reg select_wr;
cmd_encod_linear_rd #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_linear_rd_i (
.rst (rst), // input
.clk (clk), // input
.bank_in (bank_in), // input[2:0]
.row_in (row_in), // input[14:0]
.start_col (start_col), // input[6:0]
.num128_in (num128_in), // input[5:0]
.skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
);
cmd_encod_linear_wr #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_linear_wr_i (
.rst (rst), // input
.clk (clk), // input
.bank_in (bank_in), // input[2:0]
.row_in (row_in), // input[14:0]
.start_col (start_col), // input[6:0]
.num128_in (num128_in), // input[5:0]
.skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input
.enc_cmd (enc_cmd_wr), // output[31:0] reg
.enc_wr (enc_wr_wr), // output reg
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
always @(posedge clk) begin
enc_cmd <= select_wr? enc_cmd_wr: enc_cmd_rd;
enc_wr <= select_wr? enc_wr_wr: enc_wr_rd;
enc_done <= select_wr? enc_done_wr: enc_done_rd;
end
endmodule
memctrl/cmd_encod_tiled_32_rw.v 0 → 100644
View file @ ad0351ef
/*******************************************************************************
* Module: cmd_encod_tiled_32_rw
* Date:2015-02-21
* Author: andrey
* Description: Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_tiled_32_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_tiled_32_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmd_encod_tiled_32_rw #(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
) (
input rst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
input [ADDRESS_NUMBER-1:0] start_row, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bit bursts
input [FRAME_WIDTH_BITS:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows_in_m1, // number of rows to read minus 1
input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start_rd, // start generating commands by cmd_encod_linear_rd
input start_wr, // start generating commands by cmd_encod_linear_wr
output reg start, // this channel was started (1 clk from start_rd || start_wr
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
wire [31:0] enc_cmd_rd; // encoded commnad
wire enc_wr_rd; // write encoded command
wire enc_done_rd; // encoding finished
wire [31:0] enc_cmd_wr; // encoded commnad
wire enc_wr_wr; // write encoded command
wire enc_done_wr; // encoding finished
reg select_wr;
cmd_encod_tiled_32_rd #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
);
cmd_encod_tiled_32_wr #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input
.enc_cmd (enc_cmd_wr), // output[31:0] reg
.enc_wr (enc_wr_wr), // output reg
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
always @(posedge clk) begin
enc_cmd <= select_wr? enc_cmd_wr: enc_cmd_rd;
enc_wr <= select_wr? enc_wr_wr: enc_wr_rd;
enc_done <= select_wr? enc_done_wr: enc_done_rd;
end
endmodule
memctrl/cmd_encod_tiled_mux.v
View file @ ad0351ef
......@@ -40,7 +40,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols0, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open0, // keep banks open (for <=8 banks only
input partial0, // first of the two halves of a split tile (caused by memory page crossing)
input start0, // start generating commands
`ifdef def_read_mem_chn0
input start0_rd, // start generating memory read channel commands with 16-byte wide columns
input start0_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn0
input start0_wr, // start generating memory write channel commands with 16-byte wide columns
input start0_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn1
input [2:0] bank1, // bank address
......@@ -51,7 +58,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open1, // keep banks open (for <=8 banks only
input partial1, // first of the two halves of a split tile (caused by memory page crossing)
input start1, // start generating commands
`ifdef def_read_mem_chn1
input start1_rd, // start generating memory read channel commands with 16-byte wide columns
input start1_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn1
input start1_wr, // start generating memory write channel commands with 16-byte wide columns
input start1_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn2
input [2:0] bank2, // bank address
......@@ -62,7 +76,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols2, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open2, // keep banks open (for <=8 banks only
input partial2, // first of the two halves of a split tile (caused by memory page crossing)
input start2, // start generating commands
`ifdef def_read_mem_chn2
input start2_rd, // start generating memory read channel commands with 16-byte wide columns
input start2_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn2
input start2_wr, // start generating memory write channel commands with 16-byte wide columns
input start2_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn3
input [2:0] bank3, // bank address
......@@ -73,7 +94,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols3, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open3, // keep banks open (for <=8 banks only
input partial3, // first of the two halves of a split tile (caused by memory page crossing)
input start3, // start generating commands
`ifdef def_read_mem_chn3
input start3_rd, // start generating memory read channel commands with 16-byte wide columns
input start3_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn3
input start3_wr, // start generating memory write channel commands with 16-byte wide columns
input start3_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn4
input [2:0] bank4, // bank address
......@@ -84,7 +112,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols4, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open4, // keep banks open (for <=8 banks only
input partial4, // first of the two halves of a split tile (caused by memory page crossing)
input start4, // start generating commands
`ifdef def_read_mem_chn4
input start4_rd, // start generating memory read channel commands with 16-byte wide columns
input start4_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn4
input start4_wr, // start generating memory write channel commands with 16-byte wide columns
input start4_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn5
input [2:0] bank5, // bank address
......@@ -95,7 +130,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols5, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open5, // keep banks open (for <=8 banks only
input partial5, // first of the two halves of a split tile (caused by memory page crossing)
input start5, // start generating commands
`ifdef def_read_mem_chn5
input start5_rd, // start generating memory read channel commands with 16-byte wide columns
input start5_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn5
input start5_wr, // start generating memory write channel commands with 16-byte wide columns
input start5_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn6
input [2:0] bank6, // bank address
......@@ -106,7 +148,12 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols6, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open6, // keep banks open (for <=8 banks only
input partial6, // first of the two halves of a split tile (caused by memory page crossing)
input start6, // start generating commands
`ifdef def_read_mem_chn6
input start6_rd, // start generating memory read channel commands
`endif
`ifdef def_write_mem_chn6
input start6_wr, // start generating memory write channel commands
`endif
`endif
`ifdef def_tiled_chn7
input [2:0] bank7, // bank address
......@@ -117,7 +164,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols7, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open7, // keep banks open (for <=8 banks only
input partial7, // first of the two halves of a split tile (caused by memory page crossing)
input start7, // start generating commands
`ifdef def_read_mem_chn7
input start7_rd, // start generating memory read channel commands with 16-byte wide columns
input start7_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn7
input start7_wr, // start generating memory write channel commands with 16-byte wide columns
input start7_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn8
input [2:0] bank8, // bank address
......@@ -128,7 +182,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols8, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open8, // keep banks open (for <=8 banks only
input partial8, // first of the two halves of a split tile (caused by memory page crossing)
input start8, // start generating commands
`ifdef def_read_mem_chn8
input start8_rd, // start generating memory read channel commands with 16-byte wide columns
input start8_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn8
input start8_wr, // start generating memory write channel commands with 16-byte wide columns
input start8_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn9
input [2:0] bank9, // bank address
......@@ -139,7 +200,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols9, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open9, // keep banks open (for <=8 banks only
input partial9, // first of the two halves of a split tile (caused by memory page crossing)
input start9, // start generating commands
`ifdef def_read_mem_chn9
input start9_rd, // start generating memory read channel commands with 16-byte wide columns
input start9_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn9
input start9_wr, // start generating memory write channel commands with 16-byte wide columns
input start9_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn10
input [2:0] bank10, // bank address
......@@ -150,7 +218,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols10, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open10, // keep banks open (for <=8 banks only
input partial10, // first of the two halves of a split tile (caused by memory page crossing)
input start10, // start generating commands
`ifdef def_read_mem_chn10
input start10_rd, // start generating memory read channel commands with 16-byte wide columns
input start10_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn10
input start10_wr, // start generating memory write channel commands with 16-byte wide columns
input start10_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn11
input [2:0] bank11, // bank address
......@@ -161,7 +236,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols11, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open11, // keep banks open (for <=8 banks only
input partial11, // first of the two halves of a split tile (caused by memory page crossing)
input start11, // start generating commands
`ifdef def_read_mem_chn11
input start11_rd, // start generating memory read channel commands with 16-byte wide columns
input start11_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn11
input start11_wr, // start generating memory write channel commands with 16-byte wide columns
input start11_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn12
input [2:0] bank12, // bank address
......@@ -172,7 +254,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols12, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open12, // keep banks open (for <=8 banks only
input partial12, // first of the two halves of a split tile (caused by memory page crossing)
input start12, // start generating commands
`ifdef def_read_mem_chn12
input start12_rd, // start generating memory read channel commands with 16-byte wide columns
input start12_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn12
input start12_wr, // start generating memory write channel commands with 16-byte wide columns
input start12_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn13
input [2:0] bank13, // bank address
......@@ -183,7 +272,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols13, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open13, // keep banks open (for <=8 banks only
input partial13, // first of the two halves of a split tile (caused by memory page crossing)
input start13, // start generating commands
`ifdef def_read_mem_chn13
input start13_rd, // start generating memory read channel commands with 16-byte wide columns
input start13_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn13
input start13_wr, // start generating memory write channel commands with 16-byte wide columns
input start13_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn14
input [2:0] bank14, // bank address
......@@ -194,7 +290,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols14, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open14, // keep banks open (for <=8 banks only
input partial14, // first of the two halves of a split tile (caused by memory page crossing)
input start14, // start generating commands
`ifdef def_read_mem_chn14
input start14_rd, // start generating memory read channel commands with 16-byte wide columns
input start14_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn14
input start14_wr, // start generating memory write channel commands with 16-byte wide columns
input start14_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
`ifdef def_tiled_chn15
input [2:0] bank15, // bank address
......@@ -205,7 +308,14 @@ module cmd_encod_tiled_mux #(
input [MAX_TILE_HEIGHT-1:0] num_cols15, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open15, // keep banks open (for <=8 banks only
input partial15, // first of the two halves of a split tile (caused by memory page crossing)
input start15, // start generating commands
`ifdef def_read_mem_chn15
input start15_rd, // start generating memory read channel commands with 16-byte wide columns
input start15_rd32, // start generating memory read channel commands with 32-byte wide columns
`endif
`ifdef def_write_mem_chn15
input start15_wr, // start generating memory write channel commands with 16-byte wide columns
input start15_wr32, // start generating memory write channel commands with 32-byte wide columns
`endif
`endif
output [2:0] bank, // bank address
output [ADDRESS_NUMBER-1:0] row, // memory row
......@@ -215,8 +325,10 @@ module cmd_encod_tiled_mux #(
output [MAX_TILE_HEIGHT-1:0] num_cols, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // keep banks open (for <=8 banks only
output partial, // first of the two halves of a split tile (caused by memory page crossing)
output start_rd, // start generating commands in cmd_encod_linear_rd
output start_wr // start generating commands in cmd_encod_linear_wr
output start_rd, // start generating commands in cmd_encod_linear_rd with 16-byte wide columns
output start_wr, // start generating commands in cmd_encod_linear_wr with 16-byte wide columns
output start_rd32, // start generating commands in cmd_encod_linear_rd with 32-byte wide columns
output start_wr32 // start generating commands in cmd_encod_linear_wr with 32-byte wide columns
);
reg [2:0] bank_r; // bank address
reg [ADDRESS_NUMBER-1:0] row_r; // memory row
......@@ -226,8 +338,10 @@ module cmd_encod_tiled_mux #(
reg [MAX_TILE_HEIGHT-1:0] num_cols_r; // number of 16-pixel columns to read (rows first_r; then columns) - 1
reg keep_open_r; // keep banks open (for <=8 banks only
reg partial_r; // partial tile
reg start_rd_r; // start generating commands in cmd_encod_linear_rd
reg start_wr_r; // start generating commands in cmd_encod_linear_wr
reg start_rd_r; // start generating commands in cmd_encod_linear_rd with 16-byte wide columns
reg start_wr_r; // start generating commands in cmd_encod_linear_wr with 16-byte wide columns
reg start_rd32_r; // start generating commands in cmd_encod_linear_rd with 32-byte wide columns
reg start_wr32_r; // start generating commands in cmd_encod_linear_wr with 32-byte wide columns
wire [2:0] bank_w; // bank address
wire [ADDRESS_NUMBER-1:0] row_w; // memory row
......@@ -237,11 +351,13 @@ module cmd_encod_tiled_mux #(
wire [MAX_TILE_HEIGHT-1:0] num_cols_w; // number of 16-pixel columns to read (rows first_r; then columns) - 1
wire keep_open_w; // keep banks open (for <=8 banks only
wire partial_w; // partila tile (first half)
wire start_rd_w; // start generating commands in cmd_encod_linear_rd
wire start_wr_w; // start generating commands in cmd_encod_linear_wr
wire start_rd_w; // start generating commands in cmd_encod_linear_rd with 16-byte wide columns
wire start_wr_w; // start generating commands in cmd_encod_linear_wr with 16-byte wide columns
wire start_rd32_w; // start generating commands in cmd_encod_linear_rd with 32-byte wide columns
wire start_wr32_w; // start generating commands in cmd_encod_linear_wr with 32-byte wide columns
localparam PAR_WIDTH=(3)+(ADDRESS_NUMBER)+(COLADDR_NUMBER-3)+(FRAME_WIDTH_BITS+1)+(MAX_TILE_WIDTH)+(MAX_TILE_HEIGHT)+(1)+(1)+(2);
localparam PAR_WIDTH=(3)+(ADDRESS_NUMBER)+(COLADDR_NUMBER-3)+(FRAME_WIDTH_BITS+1)+(MAX_TILE_WIDTH)+(MAX_TILE_HEIGHT)+(1)+(1);
localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0;
assign bank = bank_r;
assign row = row_r;
......@@ -253,137 +369,384 @@ module cmd_encod_tiled_mux #(
assign partial = partial_r; // partial tile
assign start_rd = start_rd_r;
assign start_wr = start_wr_r;
localparam [15:0] CHN_RD_MEM={
`ifdef def_read_mem_chn15
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn14
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn13
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn12
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn11
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn10
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn9
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn8
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn7
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn6
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn5
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn4
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn3
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn2
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn1
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn0
1'b1};
`else
1'b0};
`endif
assign start_rd32 = start_rd32_r;
assign start_wr32 = start_wr32_r;
assign {start_rd_w,start_rd32_w}= 2'b0
`ifdef def_tiled_chn0
`ifdef def_read_mem_chn0
| {start0_rd,start0_rd32}
`endif
`endif
`ifdef def_tiled_chn1
`ifdef def_read_mem_chn1
| {start1_rd,start1_rd32}
`endif
`endif
`ifdef def_tiled_chn2
`ifdef def_read_mem_chn2
| {start2_rd,start2_rd32}
`endif
`endif
`ifdef def_tiled_chn3
`ifdef def_read_mem_chn3
| {start3_rd,start3_rd32}
`endif
`endif
`ifdef def_tiled_chn4
`ifdef def_read_mem_chn4
| {start4_rd,start4_rd32}
`endif
`endif
`ifdef def_tiled_chn5
`ifdef def_read_mem_chn5
| {start5_rd,start5_rd32}
`endif
`endif
`ifdef def_tiled_chn6
`ifdef def_read_mem_chn6
| {start6_rd,start6_rd32}
`endif
`endif
`ifdef def_tiled_chn7
`ifdef def_read_mem_chn7
| {start7_rd,start7_rd32}
`endif
`endif
`ifdef def_tiled_chn8
`ifdef def_read_mem_chn8
| {start8_rd,start8_rd32}
`endif
`endif
`ifdef def_tiled_chn9
`ifdef def_read_mem_chn9
| {start9_rd,start9_rd32}
`endif
`endif
`ifdef def_tiled_chn10
`ifdef def_read_mem_chn10
| {start10_rd,start10_rd32}
`endif
`endif
`ifdef def_tiled_chn11
`ifdef def_read_mem_chn11
| {start11_rd,start11_rd32}
`endif
`endif
`ifdef def_tiled_chn12
`ifdef def_read_mem_chn12
| {start12_rd,start12_rd32}
`endif
`endif
`ifdef def_tiled_chn13
`ifdef def_read_mem_chn13
| {start13_rd,start13_rd32}
`endif
`endif
`ifdef def_tiled_chn14
`ifdef def_read_mem_chn14
| {start14_rd,start14_rd32}
`endif
`endif
`ifdef def_tiled_chn15
`ifdef def_read_mem_chn15
| {start15_rd,start15_rd32}
`endif
`endif
;
assign {start_wr_w, start_wr32_w}= 2'b0
`ifdef def_tiled_chn0
`ifdef def_write_mem_chn0
| {start0_wr,start0_wr32}
`endif
`endif
`ifdef def_tiled_chn1
`ifdef def_write_mem_chn1
| {start1_wr,start1_wr32}
`endif
`endif
`ifdef def_tiled_chn2
`ifdef def_write_mem_chn2
| {start2_wr,start2_wr32}
`endif
`endif
`ifdef def_tiled_chn3
`ifdef def_write_mem_chn3
| {start3_wr,start3_wr32}
`endif
`endif
`ifdef def_tiled_chn4
`ifdef def_write_mem_chn4
| {start4_wr,start4_wr32}
`endif
`endif
`ifdef def_tiled_chn5
`ifdef def_write_mem_chn5
| {start5_wr,start5_wr32}
`endif
`endif
`ifdef def_tiled_chn6
`ifdef def_write_mem_chn6
| {start6_wr,start6_wr32}
`endif
`endif
`ifdef def_tiled_chn7
`ifdef def_write_mem_chn7
| {start7_wr,start7_wr32}
`endif
`endif
`ifdef def_tiled_chn8
`ifdef def_write_mem_chn8
| {start8_wr,start8_wr32}
`endif
`endif
`ifdef def_tiled_chn9
`ifdef def_write_mem_chn9
| {start9_wr,start9_wr32}
`endif
`endif
`ifdef def_tiled_chn10
`ifdef def_write_mem_chn10
| {start10_wr,start10_wr32}
`endif
`endif
`ifdef def_tiled_chn11
`ifdef def_write_mem_chn11
| {start11_wr,start11_wr32}
`endif
`endif
`ifdef def_tiled_chn12
`ifdef def_write_mem_chn12
| {start12_wr,start12_wr32}
`endif
`endif
`ifdef def_tiled_chn13
`ifdef def_write_mem_chn13
| {start13_wr,start13_wr32}
`endif
`endif
`ifdef def_tiled_chn14
`ifdef def_write_mem_chn14
| {start14_wr,start14_wr32}
`endif
`endif
`ifdef def_tiled_chn15
`ifdef def_write_mem_chn15
| {start15_wr,start15_wr32}
`endif
`endif
;
`ifdef def_tiled_chn0
wire start0=0 |
`ifdef def_read_mem_chn0
| start0_rd | start0_rd32
`endif
`ifdef def_write_mem_chn0
| start0_wr | start0_wr32
`endif
;
`endif
`ifdef def_tiled_chn1
wire start1=0 |
`ifdef def_read_mem_chn1
| start1_rd | start1_rd32
`endif
`ifdef def_write_mem_chn1
| start1_wr | start1_wr32
`endif
;
`endif
`ifdef def_tiled_chn2
wire start2=0 |
`ifdef def_read_mem_chn2
| start2_rd | start2_rd32
`endif
`ifdef def_write_mem_chn2
| start2_wr | start2_wr32
`endif
;
`endif
`ifdef def_tiled_chn3
wire start3=0 |
`ifdef def_read_mem_chn3
| start3_rd | start3_rd32
`endif
`ifdef def_write_mem_chn3
| start3_wr | start3_wr32
`endif
;
`endif
`ifdef def_tiled_chn4
wire start4=0 |
`ifdef def_read_mem_chn4
| start4_rd | start4_rd32
`endif
`ifdef def_write_mem_chn4
| start4_wr | start4_wr32
`endif
;
`endif
`ifdef def_tiled_chn5
wire start5=0 |
`ifdef def_read_mem_chn5
| start5_rd | start5_rd32
`endif
`ifdef def_write_mem_chn5
| start5_wr | start5_wr32
`endif
;
`endif
`ifdef def_tiled_chn6
wire start6=0 |
`ifdef def_read_mem_chn6
| start6_rd | start6_rd32
`endif
`ifdef def_write_mem_chn6
| start6_wr | start6_wr32
`endif
;
`endif
`ifdef def_tiled_chn7
wire start7=0 |
`ifdef def_read_mem_chn7
| start7_rd | start7_rd32
`endif
`ifdef def_write_mem_chn7
| start7_wr | start7_wr32
`endif
;
`endif
`ifdef def_tiled_chn8
wire start8=0 |
`ifdef def_read_mem_chn8
| start8_rd | start8_rd32
`endif
`ifdef def_write_mem_chn8
| start8_wr | start8_wr32
`endif
;
`endif
`ifdef def_tiled_chn9
wire start9=0 |
`ifdef def_read_mem_chn9
| start9_rd | start9_rd32
`endif
`ifdef def_write_mem_chn9
| start9_wr | start9_wr32
`endif
;
`endif
`ifdef def_tiled_chn10
wire start10=0 |
`ifdef def_read_mem_chn10
| start10_rd | start10_rd32
`endif
`ifdef def_write_mem_chn10
| start10_wr | start10_wr32
`endif
;
`endif
`ifdef def_tiled_chn11
wire start11=0 |
`ifdef def_read_mem_chn11
| start11_rd | start11_rd32
`endif
`ifdef def_write_mem_chn11
| start11_wr | start11_wr32
`endif
;
`endif
`ifdef def_tiled_chn12
wire start12=0 |
`ifdef def_read_mem_chn12
| start12_rd | start12_rd32
`endif
`ifdef def_write_mem_chn12
| start12_wr | start12_wr32
`endif
;
`endif
`ifdef def_tiled_chn13
wire start13=0 |
`ifdef def_read_mem_chn13
| start13_rd | start13_rd32
`endif
`ifdef def_write_mem_chn13
| start13_wr | start13_wr32
`endif
;
`endif
`ifdef def_tiled_chn14
wire start14=0 |
`ifdef def_read_mem_chn14
| start14_rd | start14_rd32
`endif
`ifdef def_write_mem_chn14
| start14_wr | start14_wr32
`endif
;
`endif
`ifdef def_tiled_chn15
wire start15=0 |
`ifdef def_read_mem_chn15
| start15_rd | start15_rd32
`endif
`ifdef def_write_mem_chn15
| start15_wr | start15_wr32
`endif
;
`endif
assign {bank_w, row_w, col_w, rowcol_inc_w, num_rows_w, num_cols_w, keep_open_w, partial_w, start_rd_w, start_wr_w} = 0
assign {bank_w, row_w, col_w, rowcol_inc_w, num_rows_w, num_cols_w, keep_open_w, partial_w} = 0
`ifdef def_tiled_chn0
| (start0?{bank0, row0, col0, rowcol_inc0, num_rows0, num_cols0, keep_open0, partial0, CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
| (start0?{bank0, row0, col0, rowcol_inc0, num_rows0, num_cols0, keep_open0, partial0}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn1
| (start1?{bank1, row1, col1, rowcol_inc1, num_rows1, num_cols1, keep_open1, partial1, CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
| (start1?{bank1, row1, col1, rowcol_inc1, num_rows1, num_cols1, keep_open1, partial1}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn2
| (start2?{bank2, row2, col2, rowcol_inc2, num_rows2, num_cols2, keep_open2, partial2, CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
| (start2?{bank2, row2, col2, rowcol_inc2, num_rows2, num_cols2, keep_open2, partial2}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn3
| (start3?{bank3, row3, col3, rowcol_inc3, num_rows3, num_cols3, keep_open3, partial3, CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
| (start3?{bank3, row3, col3, rowcol_inc3, num_rows3, num_cols3, keep_open3, partial3}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn4
| (start4?{bank4, row4, col4, rowcol_inc4, num_rows4, num_cols4, keep_open4, partial4, CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
| (start4?{bank4, row4, col4, rowcol_inc4, num_rows4, num_cols4, keep_open4, partial4}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn5
| (start5?{bank5, row5, col5, rowcol_inc5, num_rows5, num_cols5, keep_open5, partial5, CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
| (start5?{bank5, row5, col5, rowcol_inc5, num_rows5, num_cols5, keep_open5, partial5}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn6
| (start6?{bank6, row6, col6, rowcol_inc6, num_rows6, num_cols6, keep_open6, partial6, CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
| (start6?{bank6, row6, col6, rowcol_inc6, num_rows6, num_cols6, keep_open6, partial6}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn7
| (start7?{bank7, row7, col7, rowcol_inc7, num_rows7, num_cols7, keep_open7, partial7, CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
| (start7?{bank7, row7, col7, rowcol_inc7, num_rows7, num_cols7, keep_open7, partial7}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn8
| (start8?{bank8, row8, col8, rowcol_inc8, num_rows8, num_cols8, keep_open8, partial8, CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
| (start8?{bank8, row8, col8, rowcol_inc8, num_rows8, num_cols8, keep_open8, partial8}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn9
| (start9?{bank9, row9, col9, rowcol_inc9, num_rows9, num_cols9, keep_open9, partial9, CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
| (start9?{bank9, row9, col9, rowcol_inc9, num_rows9, num_cols9, keep_open9, partial9}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn10
| (start10?{bank10, row10, col10, rowcol_inc10, num_rows10, num_cols10, keep_open10, partial10, CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
| (start10?{bank10, row10, col10, rowcol_inc10, num_rows10, num_cols10, keep_open10, partial10}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn11
| (start11?{bank11, row11, col11, rowcol_inc11, num_rows11, num_cols11, keep_open11, partial11, CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
| (start11?{bank11, row11, col11, rowcol_inc11, num_rows11, num_cols11, keep_open11, partial11}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn12
| (start12?{bank12, row12, col12, rowcol_inc12, num_rows12, num_cols12, keep_open12, partial12, CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
| (start12?{bank12, row12, col12, rowcol_inc12, num_rows12, num_cols12, keep_open12, partial12}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn13
| (start13?{bank13, row13, col13, rowcol_inc13, num_rows13, num_cols13, keep_open13, partial13, CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
| (start13?{bank13, row13, col13, rowcol_inc13, num_rows13, num_cols13, keep_open13, partial13}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn14
| (start14?{bank14, row14, col14, rowcol_inc14, num_rows14, num_cols14, keep_open14, partial14, CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
| (start14?{bank14, row14, col14, rowcol_inc14, num_rows14, num_cols14, keep_open14, partial14}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn15
| (start15?{bank15, row15, col15, rowcol_inc15, num_rows15, num_cols15, keep_open15, partial15, CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
| (start15?{bank15, row15, col15, rowcol_inc15, num_rows15, num_cols15, keep_open15, partial15}:PAR_DEFAULT)
`endif
;
always @ (posedge clk) begin
......@@ -399,6 +762,8 @@ module cmd_encod_tiled_mux #(
end
start_rd_r <= start_rd_w;
start_wr_r <= start_wr_w;
start_rd32_r <= start_rd32_w;
start_wr32_r <= start_wr32_w;
end
......
memctrl/cmd_encod_tiled_rw.v 0 → 100644
View file @ ad0351ef
/*******************************************************************************
* Module: cmd_encod_tiled_rw
* Date:2015-02-21
* Author: andrey
* Description: Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_tiled_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_tiled_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmd_encod_tiled_rw #(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
) (
input rst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
input [ADDRESS_NUMBER-1:0] start_row, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bit bursts
input [FRAME_WIDTH_BITS:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows_in_m1, // number of rows to read minus 1
input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start_rd, // start generating commands by cmd_encod_linear_rd
input start_wr, // start generating commands by cmd_encod_linear_wr
output reg start, // this channel was started (1 clk from start_rd || start_wr
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
wire [31:0] enc_cmd_rd; // encoded commnad
wire enc_wr_rd; // write encoded command
wire enc_done_rd; // encoding finished
wire [31:0] enc_cmd_wr; // encoded commnad
wire enc_wr_wr; // write encoded command
wire enc_done_wr; // encoding finished
reg select_wr;
cmd_encod_tiled_rd #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_rd), // input
.enc_cmd (enc_cmd_rd), // output[31:0] reg
.enc_wr (enc_wr_rd), // output reg
.enc_done (enc_done_rd) // output reg
);
cmd_encod_tiled_wr #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
.start_col (start_col), // input[6:0]
.rowcol_inc_in (rowcol_inc_in), // input[13:0] // [21:0]
.num_rows_in_m1 (num_rows_in_m1), // input[5:0]
.num_cols_in_m1 (num_cols_in_m1), // input[5:0]
.keep_open_in (keep_open_in), // input
.skip_next_page_in (skip_next_page_in), // input
.start (start_wr), // input
.enc_cmd (enc_cmd_wr), // output[31:0] reg
.enc_wr (enc_wr_wr), // output reg
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
always @(posedge clk) begin
enc_cmd <= select_wr? enc_cmd_wr: enc_cmd_rd;
enc_wr <= select_wr? enc_wr_wr: enc_wr_rd;
enc_done <= select_wr? enc_done_wr: enc_done_rd;
end
endmodule
memctrl/mcntrl393.v
View file @ ad0351ef
......@@ -30,11 +30,20 @@ module mcntrl393 #(
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
// parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
// parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
// parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
// parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
// parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h0800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_WR_ADDR = 'h0c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
//command interface parameters
......@@ -164,7 +173,7 @@ module mcntrl393 #(
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
......@@ -178,18 +187,19 @@ module mcntrl393 #(
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
// parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h6,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h150,
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -202,7 +212,8 @@ module mcntrl393 #(
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......@@ -259,6 +270,14 @@ module mcntrl393 #(
// Channels 2 and 3 control signals
// TODO: move line_unfinished and suspend to internals of this module (and control comparator modes)
input frame_start_chn1, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn1, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn1, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done_chn1, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn1, // suspend transfers (from external line number comparator)
input frame_start_chn2, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn2, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn2, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
......@@ -282,14 +301,6 @@ module mcntrl393 #(
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn4, // suspend transfers (from external line number comparator)
// Channel 5 (tiled write)
input frame_start_chn5, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn5, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn5, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done_chn5, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn5, // suspend transfers (from external line number comparator)
// DDR3 interface
......@@ -340,83 +351,79 @@ module mcntrl393 #(
// wire seq_wr0; // not used
wire seq_set0;
wire seq_done0;
// wire rpage_nxt_chn0;
wire buf_wr_chn0;
wire buf_wpage_nxt_chn0;
wire buf_run0;
wire [63:0] buf_wdata_chn0;
wire buf_wrun0;
wire buf_rd_chn0;
wire buf_rpage_nxt_chn0;
wire [63:0] buf_rdata_chn0;
wire want_rq1;
wire need_rq1;
wire channel_pgm_en1;
wire seq_done1;
wire rpage_nxt_chn1;
wire buf_run1;
wire page_nxt_chn1;
wire buf_wr_chn1;
wire buf_wpage_nxt_chn1;
wire [63:0] buf_wdata_chn1;
wire buf_rd_chn1;
wire rpage_nxt_chn1;
wire [63:0] buf_rdata_chn1;
wire want_rq2;
wire need_rq2;
wire channel_pgm_en2;
wire [31:0] seq_data2x; // may be shared with other channel
wire seq_wr2x; // may be shared with other channel
wire seq_set2x; // may be shared with other channel
wire seq_done2;
// wire rpage_nxt_chn2;
wire page_nxt_chn2;
wire buf_wr_chn2;
wire buf_wpage_nxt_chn2;
wire [63:0] buf_wdata_chn2;
wire buf_rd_chn2;
wire rpage_nxt_chn2;
wire [63:0] buf_rdata_chn2;
wire want_rq3;
wire need_rq3;
wire channel_pgm_en3;
wire [31:0] seq_data3x; // may be shared with other channel
wire seq_wr3x; // may be shared with other channel
wire seq_set3x; // may be shared with other channel
wire seq_done3;
wire rpage_nxt_chn3;
wire page_nxt_chn3;
wire buf_wr_chn3;
wire buf_wpage_nxt_chn3;
wire [63:0] buf_wdata_chn3;
wire buf_rd_chn3;
wire rpage_nxt_chn3;
wire [63:0] buf_rdata_chn3;
wire want_rq4;
wire need_rq4;
wire channel_pgm_en4;
// wire seq_tiled_start_rd;
wire [31:0] seq_data4x; // may be shared with other channel
wire seq_wr4x; // may be shared with other channel
wire seq_set4x; // may be shared with other channel
wire seq_done4;
wire rpage_nxt_chn4;
wire page_nxt_chn4;
wire buf_wr_chn4;
wire buf_wpage_nxt_chn4;
wire [63:0] buf_wdata_chn4;
wire buf_rd_chn4;
wire rpage_nxt_chn4;
wire [63:0] buf_rdata_chn4;
wire want_rq5;
wire need_rq5;
wire channel_pgm_en5;
wire [31:0] seq_data5x; // may be shared with other channel
wire seq_wr5x; // may be shared with other channel
wire seq_set5x; // may be shared with other channel
wire seq_done5;
wire rpage_nxt_chn5;
wire buf_rd_chn5;
wire [63:0] buf_rdata_chn5;
// Command tree - insert register layer if needed
wire [7:0] cmd_mcontr_ad;
wire cmd_mcontr_stb;
wire [7:0] cmd_ps_pio_ad;
wire cmd_ps_pio_stb;
wire [7:0] cmd_scanline_chn2_ad;
wire cmd_scanline_chn2_stb;
wire [7:0] cmd_scanline_chn1_ad;
wire cmd_scanline_chn1_stb;
wire [7:0] cmd_scanline_chn3_ad;
wire cmd_scanline_chn3_stb;
wire [7:0] cmd_tiled_chn2_ad;
wire cmd_tiled_chn2_stb;
wire [7:0] cmd_tiled_chn4_ad;
wire cmd_tiled_chn4_stb;
wire [7:0] cmd_tiled_chn5_ad;
wire cmd_tiled_chn5_stb;
// Status tree:
......@@ -428,42 +435,52 @@ module mcntrl393 #(
wire status_ps_pio_rq; // PS PIO channels status request
wire status_ps_pio_start; // PS PIO channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn2_ad; // PL scanline channel2 (memory read) status byte-wide address/data
wire status_scanline_chn2_rq; // PL scanline channel2 (memory read) channels status request
wire status_scanline_chn2_start; // PL scanline channel2 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn1_ad; // PL scanline channel1 (memory read) status byte-wide address/data
wire status_scanline_chn1_rq; // PL scanline channel1 (memory read) channels status request
wire status_scanline_chn1_start; // PL scanline channel1 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn3_ad; // PL scanline channel3 (memory read) status byte-wide address/data
wire status_scanline_chn3_rq; // PL scanline channel3 (memory read) channels status request
wire status_scanline_chn3_start; // PL scanline channel3 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn2_ad; // PL tiled channel2 (memory read) status byte-wide address/data
wire status_tiled_chn2_rq; // PL tiled channel2 (memory read) channels status request
wire status_tiled_chn2_start; // PL tiled channel2 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn4_ad; // PL tiled channel4 (memory read) status byte-wide address/data
wire status_tiled_chn4_rq; // PL tiled channel4 (memory read) channels status request
wire status_tiled_chn4_start; // PL tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn5_ad; // PL tiled channel5 (memory read) status byte-wide address/data
wire status_tiled_chn5_rq; // PL tiled channel5 (memory read) channels status request
wire status_tiled_chn5_start; // PL tiled channel5 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
// combinatorial early signals
wire select_cmd0_w;
wire select_buf0_w;
wire select_buf1_w;
wire select_buf2_w;
wire select_buf3_w;
wire select_buf4_w;
wire select_buf5_w;
wire select_buf0rd_w;
wire select_buf0wr_w;
wire select_buf1rd_w;
wire select_buf1wr_w;
wire select_buf2rd_w;
wire select_buf2wr_w;
wire select_buf3rd_w;
wire select_buf3wr_w;
wire select_buf4rd_w;
wire select_buf4wr_w;
// registered selects
reg select_cmd0;
reg select_buf0;
reg select_buf1;
reg select_buf2;
reg select_buf3;
reg select_buf4;
reg select_buf5;
reg select_buf0_d; // delayed by 1 clock, for combining with regen?
reg select_buf2_d;
reg select_buf4_d;
reg select_buf0rd;
reg select_buf0wr;
reg select_buf1rd;
reg select_buf1wr;
reg select_buf2rd;
reg select_buf2wr;
reg select_buf3rd;
reg select_buf3wr;
reg select_buf4rd;
reg select_buf4wr;
reg select_buf0rd_d; // delayed by 1 clock, for combining with regen?
reg select_buf1rd_d;
reg select_buf2rd_d;
reg select_buf3rd_d;
reg select_buf4rd_d;
reg axird_selected_r; // this module provides output
......@@ -471,51 +488,62 @@ module mcntrl393 #(
reg [BUFFER_DEPTH32-1:0] buf_waddr;
reg [31:0] buf_wdata;
reg cmd_we;
reg buf1_we;
reg buf3_we;
reg buf5_we;
reg buf0wr_we;
reg buf1wr_we;
reg buf2wr_we;
reg buf3wr_we;
reg buf4wr_we;
wire [BUFFER_DEPTH32-1:0] buf_raddr;
wire [31:0] buf0_data;
wire [31:0] buf2_data;
wire [31:0] buf4_data;
wire [31:0] buf1rd_data;
wire [31:0] buf2rd_data;
wire [31:0] buf3rd_data;
wire [31:0] buf4rd_data;
wire buf0_rd;
wire buf0_regen;
wire buf2_rd;
wire buf2_regen;
wire buf4_rd;
wire buf4_regen;
// common for channels 2 and 3
wire buf1rd_rd;
wire buf1rd_regen;
wire buf2rd_rd;
wire buf2rd_regen;
wire buf3rd_rd;
wire buf3rd_regen;
wire buf4rd_rd;
wire buf4rd_regen;
// common for channels 1 and 3
wire [2:0] lin_rw_bank; // memory bank
wire [ADDRESS_NUMBER-1:0] lin_rw_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_col; // start memory column in 8-bursts
wire [5:0] lin_rw_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_xfer_partial; // do not increment page in the end, continue current
wire lin_rd_start; // start generating commands for read sequence
wire lin_wr_start; // start generating commands for write sequence
wire [2:0] lin_rd_chn2_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_rd_chn2_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rd_chn2_col; // start memory column in 8-bursts
wire [5:0] lin_rd_chn2_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rd_chn2_partial; // do not increment page in the end, continue current
wire lin_rd_chn2_start; // start generating commands
wire lin_rw_start_rd; // start generating commands for read sequence
wire lin_rw_start_wr; // start generating commands for write sequence
wire [2:0] lin_rw_chn1_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_rw_chn1_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_chn1_col; // start memory column in 8-bursts
wire [5:0] lin_rw_chn1_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_chn1_partial; // do not increment page in the end, continue current
wire lin_rw_chn1_start_rd; // start generating commands
wire lin_rw_chn1_start_wr; // start generating commands
// wire [1:0] xfer_page2; // "internal" buffer page
wire xfer_reset_page2_pos; // "internal" buffer page reset, @posedge mclk
reg xfer_reset_page2_neg; // "internal" buffer page reset, @negedge mclk
wire xfer_reset_page1_wr; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page1_rd; // "internal" buffer page reset, @negedge mclk
wire [2:0] lin_wr_chn3_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_wr_chn3_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_wr_chn3_col; // start memory column in 8-bursts
wire [5:0] lin_wr_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_wr_chn3_partial; // do not increment page in the end, continue current
wire lin_wr_chn3_start; // start generating commands
wire [2:0] lin_rw_chn3_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_rw_chn3_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_rw_chn3_col; // start memory column in 8-bursts
wire [5:0] lin_rw_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rw_chn3_partial; // do not increment page in the end, continue current
wire lin_rw_chn3_start_rd; // start generating commands
wire lin_rw_chn3_start_wr; // start generating commands
// wire [1:0] xfer_page3; // "internal" buffer page
wire xfer_reset_page3; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page3_wr; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page3_rd; // "internal" buffer page reset, @negedge mclk
// common for tiled r/w - channels 2 and 4
wire [2:0] tiled_rw_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_col; // start memory column in 8-bursts
......@@ -524,112 +552,172 @@ module mcntrl393 #(
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rw_keep_open; // start generating commands
wire tiled_rw_xfer_partial; // start generating commands
wire tiled_rd_start; // start generating commands
wire tiled_wr_start; // start generating commands
wire [2:0] tiled_rd_chn4_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rd_chn4_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rd_chn4_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rd_chn4_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rd_chn4_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rd_chn4_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rd_chn4_keep_open; // start generating commands
wire tiled_rd_chn4_xfer_partial; // start generating commands
wire tiled_rd_chn4_start; // start generating commands
wire xfer_reset_page4_pos; // "internal" buffer page reset, @posedge mclk
reg xfer_reset_page4_neg; // "internal" buffer page reset, @negedge mclk
wire [2:0] tiled_wr_chn5_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_wr_chn5_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_wr_chn5_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_wr_chn5_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_wr_chn5_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_wr_chn5_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_wr_chn5_keep_open; // start generating commands
wire tiled_wr_chn5_xfer_partial; // start generating commands
wire tiled_wr_chn5_start; // start generating commands
wire xfer_reset_page5; // "internal" buffer page reset, @posedge mclk
wire [2:0] tiled_rw_chn2_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_chn2_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_chn2_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rw_chn2_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rw_chn2_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_chn2_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rw_chn2_keep_open; // start generating commands
wire tiled_rw_chn2_xfer_partial; // start generating commands
wire tiled_rw_chn2_start_rd16; // start generating commands, read, 16-byte column tiles
wire tiled_rw_chn2_start_wr16; // start generating commands, write, 16-byte column tiles
wire tiled_rw_chn2_start_rd32; // start generating commands, read, 32-byte column tiles
wire tiled_rw_chn2_start_wr32; // start generating commands, write, 32-byte column tiles
wire xfer_reset_page2_wr; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page2_rd; // "internal" buffer page reset, @negedge mclk
wire [2:0] tiled_rw_chn4_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_chn4_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_chn4_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rw_chn4_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rw_chn4_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_chn4_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rw_chn4_keep_open; // start generating commands
wire tiled_rw_chn4_xfer_partial; // start generating commands
wire tiled_rw_chn4_start_rd16; // start generating commands
wire tiled_rw_chn4_start_wr16; // start generating commands
wire tiled_rw_chn4_start_rd32; // start generating commands
wire tiled_rw_chn4_start_wr32; // start generating commands
wire xfer_reset_page4_wr; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page4_rd; // "internal" buffer page reset, @negedge mclk
//====================== new signals ==============================
wire [31:0] seq_data; // combine data to be written to the memory controller sequencer
wire seq_wr; // strobe to write seq_data
wire seq_set; // finalize write to command sequencer (or PS data address if no seq_wr was present
// from encod_linear_rw
wire encod_linear_start_out; // pulse before encod_linear_rw outputs any data
wire [31:0] encod_linear_cmd; // command sequencer data
wire encod_linear_wr; // command sequencer data strobe
wire encod_linear_done;// end of command sequnece
// from encod_tiled_rw
wire encod_tiled16_start_out; // pulse before encod_tiled_rw outputs any data
wire [31:0] encod_tiled16_cmd;
wire encod_tiled16_wr;
wire encod_tiled16_done;
// from encod_tiled_32_rw
wire encod_tiled32_start_out; // pulse before encod_tiled_32_rw outputs any data
wire [31:0] encod_tiled32_cmd;
wire encod_tiled32_wr;
wire encod_tiled32_done;
wire tiled_rw_start_rd16; // start cmd_encod_tiled_32_rw generating command sequence in read mode
wire tiled_rw_start_wr16; // start cmd_encod_tiled_32_rw generating command sequence in write mode
wire tiled_rw_start_rd32; // start cmd_encod_tiled_32_rw generating command sequence in read mode
wire tiled_rw_start_wr32; // start cmd_encod_tiled_32_rw generating command sequence in write mode
// Command tree - insert register layer(s) if needed, now just direct assignments
assign cmd_mcontr_ad= cmd_ad;
assign cmd_mcontr_stb= cmd_stb;
assign cmd_ps_pio_ad= cmd_ad;
assign cmd_ps_pio_stb= cmd_stb;
assign cmd_scanline_chn2_ad= cmd_ad;
assign cmd_scanline_chn2_stb=cmd_stb;
assign cmd_scanline_chn1_ad= cmd_ad;
assign cmd_scanline_chn1_stb=cmd_stb;
assign cmd_scanline_chn3_ad= cmd_ad;
assign cmd_scanline_chn3_stb=cmd_stb;
assign cmd_tiled_chn2_ad= cmd_ad;
assign cmd_tiled_chn2_stb= cmd_stb;
assign cmd_tiled_chn4_ad= cmd_ad;
assign cmd_tiled_chn4_stb= cmd_stb;
assign cmd_tiled_chn5_ad= cmd_ad;
assign cmd_tiled_chn5_stb= cmd_stb;
// For now - combinatorial, maybe add registers (modify axibram_read)
assign buf_raddr=axird_raddr;
assign axird_rdata = (select_buf0 ? buf0_data : 32'b0) | (select_buf2 ? buf2_data : 32'b0) | (select_buf4 ? buf4_data : 32'b0);
assign axird_rdata = (select_buf0rd ? buf0_data : 32'b0) |
(select_buf1rd ? buf1rd_data : 32'b0) |
(select_buf2rd ? buf2rd_data : 32'b0) |
(select_buf3rd ? buf3rd_data : 32'b0) |
(select_buf4rd ? buf4rd_data : 32'b0);
assign buf0_rd= axird_ren && select_buf0rd;
assign buf0_regen= axird_regen && select_buf0rd_d;
assign buf1rd_rd= axird_ren && select_buf1rd;
assign buf1rd_regen= axird_regen && select_buf1rd_d;
assign buf2rd_rd= axird_ren && select_buf2rd;
assign buf2rd_regen= axird_regen && select_buf2rd_d;
assign buf3rd_rd= axird_ren && select_buf3rd;
assign buf3rd_regen= axird_regen && select_buf3rd_d;
assign buf4rd_rd= axird_ren && select_buf4rd;
assign buf4rd_regen= axird_regen && select_buf4rd_d;
assign buf0_rd= axird_ren && select_buf0;
assign buf0_regen= axird_regen && select_buf0_d;
assign buf2_rd= axird_ren && select_buf2;
assign buf2_regen= axird_regen && select_buf2_d;
assign buf4_rd= axird_ren && select_buf4;
assign buf4_regen= axird_regen && select_buf4_d;
assign page_ready_chn2=seq_done2;
assign page_ready_chn3=seq_done3; // TODO - check if it should not be rpage_next
assign page_ready_chn4=rpage_nxt_chn4;
assign page_ready_chn5=rpage_nxt_chn5; // ??? yes - seq_done is for every page
assign page_ready_chn1=page_nxt_chn1; //seq_done2;
assign page_ready_chn2=page_nxt_chn2; //seq_done2;
assign page_ready_chn3=page_nxt_chn3; //seq_done3; // TODO - check if it should not be rpage_next
assign page_ready_chn4=page_nxt_chn4; //rpage_nxt_chn4;
assign axird_selected=axird_selected_r;
assign select_cmd0_w = ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf0_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf1_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf2_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf3_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf4_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf5_w = ((axiwr_pre_awaddr ^ MCONTR_BUF5_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf0rd_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf0wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF0_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf1rd_w = ((axird_pre_araddr ^ MCONTR_BUF1_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf1wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf2rd_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf2wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF2_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf3rd_w = ((axird_pre_araddr ^ MCONTR_BUF3_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf3wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf4rd_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf4wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF4_WR_ADDR) & MCONTR_WR_MASK)==0;
always @ (posedge axi_rst or posedge axi_clk) begin
if (axi_rst) select_cmd0 <= 0;
else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
if (axi_rst) select_buf0 <= 0;
else if (axird_start_burst) select_buf0 <= select_buf0_w;
if (axi_rst) select_buf1 <= 0;
else if (axiwr_start_burst) select_buf1 <= select_buf1_w;
if (axi_rst) select_buf2 <= 0;
else if (axird_start_burst) select_buf2 <= select_buf2_w;
if (axi_rst) select_buf3 <= 0;
else if (axiwr_start_burst) select_buf3 <= select_buf3_w;
if (axi_rst) select_buf0rd <= 0;
else if (axird_start_burst) select_buf0rd <= select_buf0rd_w;
if (axi_rst) select_buf0wr <= 0;
else if (axird_start_burst) select_buf0wr <= select_buf0wr_w;
if (axi_rst) select_buf4 <= 0;
else if (axird_start_burst) select_buf4 <= select_buf4_w;
if (axi_rst) select_buf1rd <= 0;
else if (axird_start_burst) select_buf1rd <= select_buf1rd_w;
if (axi_rst) select_buf1wr <= 0;
else if (axird_start_burst) select_buf1wr <= select_buf1wr_w;
if (axi_rst) select_buf2rd <= 0;
else if (axird_start_burst) select_buf2rd <= select_buf2rd_w;
if (axi_rst) select_buf2wr <= 0;
else if (axird_start_burst) select_buf2wr <= select_buf2wr_w;
if (axi_rst) select_buf3rd <= 0;
else if (axird_start_burst) select_buf3rd <= select_buf3rd_w;
if (axi_rst) select_buf3wr <= 0;
else if (axird_start_burst) select_buf3wr <= select_buf3wr_w;
if (axi_rst) select_buf4rd <= 0;
else if (axird_start_burst) select_buf4rd <= select_buf4rd_w;
if (axi_rst) select_buf4wr <= 0;
else if (axird_start_burst) select_buf4wr <= select_buf4wr_w;
if (axi_rst) select_buf5 <= 0;
else if (axiwr_start_burst) select_buf5 <= select_buf5_w;
if (axi_rst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf2_w ||select_buf4_w;
else if (axird_start_burst) axird_selected_r <= select_buf0rd_w || select_buf1rd_w ||
select_buf2rd_w || select_buf3rd_w || select_buf4rd_w;
end
always @ (posedge axi_clk) begin
if (axiwr_wen) buf_wdata <= axiwr_data;
if (axiwr_wen) buf_waddr <= axiwr_waddr;
cmd_we <= axiwr_wen && select_cmd0;
buf1_we <= axiwr_wen && select_buf1;
buf3_we <= axiwr_wen && select_buf3;
buf5_we <= axiwr_wen && select_buf5;
buf0wr_we <= axiwr_wen && select_buf0wr;
buf1wr_we <= axiwr_wen && select_buf1wr;
buf2wr_we <= axiwr_wen && select_buf2wr;
buf3wr_we <= axiwr_wen && select_buf3wr;
buf4wr_we <= axiwr_wen && select_buf4wr;
select_buf0_d <= select_buf0;
select_buf2_d <= select_buf2;
select_buf4_d <= select_buf4;
select_buf0rd_d <= select_buf0rd;
select_buf1rd_d <= select_buf1rd;
select_buf2rd_d <= select_buf2rd;
select_buf3rd_d <= select_buf3rd;
select_buf4rd_d <= select_buf4rd;
end
//axiwr_waddr
status_router16 status_router16_mctrl_top_i (
......@@ -641,18 +729,18 @@ module mcntrl393 #(
.db_in1 (status_ps_pio_ad), // input[7:0]
.rq_in1 (status_ps_pio_rq), // input
.start_in1 (status_ps_pio_start), // output
.db_in2 (status_scanline_chn2_ad), // input[7:0]
.rq_in2 (status_scanline_chn2_rq), // input
.start_in2 (status_scanline_chn2_start), // output
.db_in2 (status_scanline_chn1_ad), // input[7:0]
.rq_in2 (status_scanline_chn1_rq), // input
.start_in2 (status_scanline_chn1_start), // output
.db_in3 (status_scanline_chn3_ad), // input[7:0]
.rq_in3 (status_scanline_chn3_rq), // input
.start_in3 (status_scanline_chn3_start), // output
.db_in4 (status_tiled_chn4_ad), // input[7:0]
.rq_in4 (status_tiled_chn4_rq), // input
.start_in4 (status_tiled_chn4_start), // output
.db_in5 (status_tiled_chn5_ad), // input[7:0]
.rq_in5 (status_tiled_chn5_rq), // input
.start_in5 (status_tiled_chn5_start), // output
.db_in4 (status_tiled_chn2_ad), // input[7:0]
.rq_in4 (status_tiled_chn2_rq), // input
.start_in4 (status_tiled_chn2_start), // output
.db_in5 (status_tiled_chn4_ad), // input[7:0]
.rq_in5 (status_tiled_chn4_rq), // input
.start_in5 (status_tiled_chn4_start), // output
.db_in6 (8'b0), // input[7:0]
.rq_in6 (1'b0), // input
.start_in6 (), // output
......@@ -689,317 +777,136 @@ module mcntrl393 #(
.start_out (status_start) // input
);
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.MCNTRL_TILED_WRITE_MODE (1'b0)
) mcntrl_tiled_rw_chn4_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn4_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn4_stb), // input
.status_ad (status_tiled_chn4_ad), // output[7:0]
.status_rq (status_tiled_chn4_rq), // output
.status_start (status_tiled_chn4_start), // input
.frame_start (frame_start_chn4), // input
.next_page (next_page_chn4), // input
.frame_done (frame_done_chn4), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input
.xfer_want (want_rq4), // output
.xfer_need (need_rq4), // output
.xfer_grant (channel_pgm_en4), // input
.xfer_start (tiled_rd_chn4_start), // output
.xfer_bank (tiled_rd_chn4_bank), // output[2:0]
.xfer_row (tiled_rd_chn4_row), // output[14:0]
.xfer_col (tiled_rd_chn4_col), // output[6:0]
.rowcol_inc (tiled_rd_chn4_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rd_chn4_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rd_chn4_num_cols_m1), // output[5:0]
.keep_open (tiled_rd_chn4_keep_open), // output
.xfer_partial (tiled_rd_chn4_xfer_partial), // output
.xfer_page_done (seq_done4), // input
.xfer_page_rst (xfer_reset_page4_pos) // output
);
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.MCNTRL_TILED_WRITE_MODE (1'b1)
) mcntrl_tiled_rw_chn5_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn5_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn5_stb), // input
.status_ad (status_tiled_chn5_ad), // output[7:0]
.status_rq (status_tiled_chn5_rq), // output
.status_start (status_tiled_chn5_start), // input
.frame_start (frame_start_chn5), // input
.next_page (next_page_chn5), // input
.frame_done (frame_done_chn5), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn5), // output[15:0]
.suspend (suspend_chn5), // input
.xfer_want (want_rq5), // output
.xfer_need (need_rq5), // output
.xfer_grant (channel_pgm_en5), // input
.xfer_start (tiled_wr_chn5_start), // output
.xfer_bank (tiled_wr_chn5_bank), // output[2:0]
.xfer_row (tiled_wr_chn5_row), // output[14:0]
.xfer_col (tiled_wr_chn5_col), // output[6:0]
.rowcol_inc (tiled_wr_chn5_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_wr_chn5_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_wr_chn5_num_cols_m1), // output[5:0]
.keep_open (tiled_wr_chn5_keep_open), // output
.xfer_partial (tiled_wr_chn5_xfer_partial), // output
.xfer_page_done (seq_done5), // input
.xfer_page_rst (xfer_reset_page5) // output
);
cmd_encod_tiled_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT)
) cmd_encod_tiled_mux_i (
.clk (mclk), // input
.bank4 (tiled_rd_chn4_bank), // input[2:0]
.row4 (tiled_rd_chn4_row), // input[14:0]
.col4 (tiled_rd_chn4_col), // input[6:0]
.rowcol_inc4 (tiled_rd_chn4_rowcol_inc), // input[13:0]
.num_rows4 (tiled_rd_chn4_num_rows_m1), // input[5:0]
.num_cols4 (tiled_rd_chn4_num_cols_m1), // input[5:0]
.keep_open4 (tiled_rd_chn4_keep_open), // input
.partial4 (tiled_rd_chn4_xfer_partial), // input
.start4 (tiled_rd_chn4_start), // input
.bank5 (tiled_wr_chn5_bank), // input[2:0]
.row5 (tiled_wr_chn5_row), // input[14:0]
.col5 (tiled_wr_chn5_col), // input[6:0]
.rowcol_inc5 (tiled_wr_chn5_rowcol_inc), // input[13:0]
.num_rows5 (tiled_wr_chn5_num_rows_m1), // input[5:0]
.num_cols5 (tiled_wr_chn5_num_cols_m1), // input[5:0]
.keep_open5 (tiled_wr_chn5_keep_open), // input
.partial5 (tiled_wr_chn5_xfer_partial), // input
.start5 (tiled_wr_chn5_start), // input
.bank (tiled_rw_bank), // output[2:0]
.row (tiled_rw_row), // output[14:0]
.col (tiled_rw_col), // output[6:0]
.rowcol_inc (tiled_rw_rowcol_inc), // output[13:0]
.num_rows (tiled_rw_num_rows_m1), // output[5:0]
.num_cols (tiled_rw_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_keep_open), // output
.partial (tiled_rw_xfer_partial), // output
.start_rd (tiled_rd_start), // output
.start_wr (tiled_wr_start) // output
);
// with external defines, does not search module definition when creating closure for iverilog
// TODO: fix
`define USE_CMD_ENCOD_TILED_32_RD
`ifdef USE_CMD_ENCOD_TILED_32_RD
cmd_encod_tiled_32_rd #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_rd_start), // input
.enc_cmd (seq_data4x), // output[31:0] reg
.enc_wr (seq_wr4x), // output reg
.enc_done (seq_set4x) // output reg
);
`else
cmd_encod_tiled_rd #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_rd_start), // input
.enc_cmd (seq_data4x), // output[31:0] reg
.enc_wr (seq_wr4x), // output reg
.enc_done (seq_set4x) // output reg
);
`endif
`define USE_CMD_ENCOD_TILED_32_WR
`ifdef USE_CMD_ENCOD_TILED_32_WR
cmd_encod_tiled_32_wr #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_wr_start), // input
.enc_cmd (seq_data5x), // output[31:0] reg
.enc_wr (seq_wr5x), // output reg
.enc_done (seq_set5x) // output reg
);
`else
cmd_encod_tiled_wr #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_wr_start), // input
.enc_cmd (seq_data5x), // output[31:0] reg
.enc_wr (seq_wr5x), // output reg
.enc_done (seq_set5x) // output reg
);
`endif
//
// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
// Port 2 (read DDR to AXI) buffer, linear
always @ (negedge mclk) begin
xfer_reset_page2_neg <= xfer_reset_page2_pos;
xfer_reset_page4_neg <= xfer_reset_page4_pos;
end
mcntrl_1kx32r chn2_buf_i (
// Port 1rd (read DDR to AXI) buffer, linear
mcntrl_1kx32r chn1rd_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
.ext_rd (buf1rd_rd), // input
.ext_regen (buf1rd_regen), // input
.ext_data_out (buf1rd_data), // output[31:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page1_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt_chn1), // input
.page (), // output[1:0]
.we (buf_wr_chn1), // input
.data_in (buf_wdata_chn1) // input[63:0]
);
// Port 1wr (write DDR from AXI) buffer, linear
mcntrl_1kx32w chn1wr_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
.ext_we (buf1wr_we), // input
.ext_data_in (buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page1_wr), // input @ posedge mclk
.page_next (rpage_nxt_chn1), // input
.page (), // output[1:0]
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
// Port 2rd (read DDR to AXI) buffer, tiled
mcntrl_1kx32r chn2rd_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
.ext_rd (buf2_rd), // input
.ext_regen (buf2_regen), // input
.ext_data_out (buf2_data), // output[31:0]
.ext_rd (buf2rd_rd), // input
.ext_regen (buf2rd_regen), // input
.ext_data_out (buf2rd_data), // output[31:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page2_neg), // input TODO: Generate @ negedge mclk on frame start
.wpage_set (xfer_reset_page2_rd), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt_chn2), // input
.page (), // output[1:0]
.we (buf_wr_chn2), // input
.data_in (buf_wdata_chn2) // input[63:0]
);
// Port 2wr (write DDR from AXI) buffer, tiled
mcntrl_1kx32w chn2wr_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
.ext_we (buf2wr_we), // input
.ext_data_in (buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page2_wr), // input @ posedge mclk
.page_next (rpage_nxt_chn2), // input
.page (), // output[1:0]
.rd (buf_rd_chn2), // input
.data_out (buf_rdata_chn2) // output[63:0]
);
//-----------
// Port 3rd (read DDR to AXI) buffer, linear
mcntrl_1kx32r chn3rd_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
.ext_rd (buf3rd_rd), // input
.ext_regen (buf3rd_regen), // input
.ext_data_out (buf3rd_data), // output[31:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page3_rd), // input @ negedge mclk
.page_next (buf_wpage_nxt_chn3), // input
.page (), // output[1:0]
.we (buf_wr_chn3), // input
.data_in (buf_wdata_chn3) // input[63:0]
);
// Port 3 (write DDR from AXI) buffer, linear
mcntrl_1kx32w chn3_buf_i (
// Port 3wr (write DDR from AXI) buffer, linear
mcntrl_1kx32w chn3wr_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
.ext_we (buf3_we), // input
.ext_we (buf3wr_we), // input
.ext_data_in (buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page3), // input TODO: Generate @ posedge mclk on frame start
.rpage_set (xfer_reset_page3_wr), // input @ posedge mclk
.page_next (rpage_nxt_chn3), // input
.page (), // output[1:0]
.rd (buf_rd_chn3), // input
.data_out (buf_rdata_chn3) // output[63:0]
);
// Port 4 (read DDR to AXI) buffer, tiled
mcntrl_1kx32r chn4_buf_i (
// Port 4rd (read DDR to AXI) buffer, tiled
mcntrl_1kx32r chn4rd_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
.ext_rd (buf4_rd), // input
.ext_regen (buf4_regen), // input
.ext_data_out (buf4_data), // output[31:0]
.ext_rd (buf4rd_rd), // input
.ext_regen (buf4rd_regen), // input
.ext_data_out (buf4rd_data), // output[31:0]
.wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page4_neg), // input TODO: Generate @ negedge mclk on frame start
.wpage_set (xfer_reset_page4_rd), // input @ negedge mclk
.page_next (buf_wpage_nxt_chn4), // input
.page (), // output[1:0]
.we (buf_wr_chn4), // input
.data_in (buf_wdata_chn4) // input[63:0]
);
// Port 5 (write DDR from AXI) buffer, tiled
mcntrl_1kx32w chn5_buf_i (
// Port 4wr (write DDR from AXI) buffer, tiled
mcntrl_1kx32w chn4wr_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
.ext_we (buf5_we), // input
.ext_we (buf4wr_we), // input
.ext_data_in (buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page5), // input TODO: Generate @ posedge mclk on frame start
.page_next (rpage_nxt_chn5), // input
.rpage_set (xfer_reset_page4_wr), // input @ posedge mclk
.page_next (rpage_nxt_chn4), // input
.page (), // output[1:0]
.rd (buf_rd_chn5), // input
.data_out (buf_rdata_chn5) // output[63:0]
.rd (buf_rd_chn4), // input
.data_out (buf_rdata_chn4) // output[63:0]
);
mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
......@@ -1007,7 +914,7 @@ module mcntrl393 #(
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_SCANLINE_ADDR (MCNTRL_SCANLINE_CHN2_ADDR),
.MCNTRL_SCANLINE_ADDR (MCNTRL_SCANLINE_CHN1_ADDR),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
.MCNTRL_SCANLINE_STATUS_CNTRL (MCNTRL_SCANLINE_STATUS_CNTRL),
......@@ -1016,34 +923,36 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_WRITE_MODE (1'b0)
) mcntrl_linear_rw_chn2_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_scanline_chn2_ad), // input[7:0]
.cmd_stb (cmd_scanline_chn2_stb), // input
.status_ad (status_scanline_chn2_ad), // output[7:0]
.status_rq (status_scanline_chn2_rq), // output
.status_start (status_scanline_chn2_start), // input
.frame_start (frame_start_chn2), // input
.next_page (next_page_chn2), // input
.frame_done (frame_done_chn2), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input
.xfer_want (want_rq2), // output
.xfer_need (need_rq2), // output
.xfer_grant (channel_pgm_en2), // input
.xfer_start (lin_rd_chn2_start), // output
.xfer_bank (lin_rd_chn2_bank), // output[2:0]
.xfer_row (lin_rd_chn2_row), // output[14:0]
.xfer_col (lin_rd_chn2_col), // output[6:0]
.xfer_num128 (lin_rd_chn2_num128), // output[5:0]
.xfer_partial (lin_rd_chn2_partial), // output
.xfer_done (seq_done2), // input: sequence over
.xfer_reset_page (xfer_reset_page2_pos) // output
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
) mcntrl_linear_rw_chn1_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_scanline_chn1_ad), // input[7:0]
.cmd_stb (cmd_scanline_chn1_stb), // input
.status_ad (status_scanline_chn1_ad), // output[7:0]
.status_rq (status_scanline_chn1_rq), // output
.status_start (status_scanline_chn1_start), // input
.frame_start (frame_start_chn1), // input
.next_page (next_page_chn1), // input
.frame_done (frame_done_chn1), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn1), // output[15:0]
.suspend (suspend_chn1), // input
.xfer_want (want_rq1), // output
.xfer_need (need_rq1), // output
.xfer_grant (channel_pgm_en1), // input
.xfer_start_rd (lin_rw_chn1_start_rd), // output
.xfer_start_wr (lin_rw_chn1_start_wr), // output
.xfer_bank (lin_rw_chn1_bank), // output[2:0]
.xfer_row (lin_rw_chn1_row), // output[14:0]
.xfer_col (lin_rw_chn1_col), // output[6:0]
.xfer_num128 (lin_rw_chn1_num128), // output[5:0]
.xfer_partial (lin_rw_chn1_partial), // output
.xfer_done (seq_done1), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page1_wr), // output
.xfer_page_rst_rd (xfer_reset_page1_rd) // output
);
mcntrl_linear_rw #(
......@@ -1063,106 +972,146 @@ module mcntrl393 #(
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_WRITE_MODE (1'b1)
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET)
) mcntrl_linear_rw_chn3_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_scanline_chn3_ad), // input[7:0]
.cmd_stb (cmd_scanline_chn3_stb), // input
.status_ad (status_scanline_chn3_ad), // output[7:0]
.status_rq (status_scanline_chn3_rq), // output
.status_start (status_scanline_chn3_start), // input
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_scanline_chn3_ad), // input[7:0]
.cmd_stb (cmd_scanline_chn3_stb), // input
.status_ad (status_scanline_chn3_ad), // output[7:0]
.status_rq (status_scanline_chn3_rq), // output
.status_start (status_scanline_chn3_start), // input
.frame_start (frame_start_chn3), // input
.next_page (next_page_chn3), // input
.frame_done (frame_done_chn3), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn3), // output[15:0]
.suspend (suspend_chn3), // input
.xfer_want (want_rq3), // output
.xfer_need (need_rq3), // output
.xfer_grant (channel_pgm_en3), // input
.xfer_start (lin_wr_chn3_start), // output
.xfer_bank (lin_wr_chn3_bank), // output[2:0]
.xfer_row (lin_wr_chn3_row), // output[14:0]
.xfer_col (lin_wr_chn3_col), // output[6:0]
.xfer_num128 (lin_wr_chn3_num128), // output[5:0]
.xfer_partial (lin_wr_chn3_partial), // output
.xfer_done (seq_done3), // input : sequence over
// .xfer_page (xfer_page3) // output[1:0]
.xfer_reset_page (xfer_reset_page3) // output
.xfer_want (want_rq3), // output
.xfer_need (need_rq3), // output
.xfer_grant (channel_pgm_en3), // input
.xfer_start_rd (lin_rw_chn3_start_rd), // output
.xfer_start_wr (lin_rw_chn3_start_wr), // output
.xfer_bank (lin_rw_chn3_bank), // output[2:0]
.xfer_row (lin_rw_chn3_row), // output[14:0]
.xfer_col (lin_rw_chn3_col), // output[6:0]
.xfer_num128 (lin_rw_chn3_num128), // output[5:0]
.xfer_partial (lin_rw_chn3_partial), // output
.xfer_done (seq_done3), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page3_wr), // output
.xfer_page_rst_rd (xfer_reset_page3_rd) // output
);
cmd_encod_linear_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER)
) cmd_encod_linear_mux_i (
.clk (mclk), // input
.bank2 (lin_rd_chn2_bank), // input[2:0]
.row2 (lin_rd_chn2_row), // input[14:0]
.start_col2 (lin_rd_chn2_col), // input[6:0]
.num128_2 (lin_rd_chn2_num128), // input[5:0]
.partial2 (lin_rd_chn2_partial), // input
.start2 (lin_rd_chn2_start), // input
.bank3 (lin_wr_chn3_bank), // input[2:0]
.row3 (lin_wr_chn3_row), // input[14:0]
.start_col3 (lin_wr_chn3_col), // input[6:0]
.num128_3 (lin_wr_chn3_num128), // input[5:0]
.partial3 (lin_wr_chn3_partial), // input
.start3 (lin_wr_chn3_start), // input
.bank (lin_rw_bank), // output[2:0]
.row (lin_rw_row), // output[14:0]
.start_col (lin_rw_col), // output[6:0]
.num128 (lin_rw_num128), // output[5:0]
.partial (lin_rw_xfer_partial), // output
.start_rd (lin_rd_start), // output
.start_wr (lin_wr_start) // output
);
cmd_encod_linear_rd #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_linear_rd_i (
.rst (rst), // input
.clk (mclk), // input
.bank_in (lin_rw_bank), // input[2:0]
.row_in (lin_rw_row), // input[14:0]
.start_col (lin_rw_col), // input[6:0]
.num128_in (lin_rw_num128), // input[5:0]
.skip_next_page_in (lin_rw_xfer_partial), // input
.start (lin_rd_start), // input
.enc_cmd (seq_data2x), // output[31:0] reg
.enc_wr (seq_wr2x), // output reg
.enc_done (seq_set2x) // output reg
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_CHN2_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN2_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl_tiled_rw_chn2_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn2_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn2_stb), // input
.status_ad (status_tiled_chn2_ad), // output[7:0]
.status_rq (status_tiled_chn2_rq), // output
.status_start (status_tiled_chn2_start), // input
.frame_start (frame_start_chn2), // input
.next_page (next_page_chn2), // input
.frame_done (frame_done_chn2), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input
.xfer_want (want_rq2), // output
.xfer_need (need_rq2), // output
.xfer_grant (channel_pgm_en2), // input
.xfer_start_rd (tiled_rw_chn2_start_rd16), // output
.xfer_start_wr (tiled_rw_chn2_start_wr16), // output
.xfer_start32_rd (tiled_rw_chn2_start_rd32), // output
.xfer_start32_wr (tiled_rw_chn2_start_wr32), // output
.xfer_bank (tiled_rw_chn2_bank), // output[2:0]
.xfer_row (tiled_rw_chn2_row), // output[14:0]
.xfer_col (tiled_rw_chn2_col), // output[6:0]
.rowcol_inc (tiled_rw_chn2_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rw_chn2_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rw_chn2_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_chn2_keep_open), // output
.xfer_partial (tiled_rw_chn2_xfer_partial), // output
.xfer_page_done (seq_done2), // input
.xfer_page_rst_wr (xfer_reset_page2_wr), // output
.xfer_page_rst_rd (xfer_reset_page2_rd) // output
);
cmd_encod_linear_wr #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) cmd_encod_linear_wr_i (
.rst (rst), // input
.clk (mclk), // input
.bank_in (lin_rw_bank), // input[2:0]
.row_in (lin_rw_row), // input[14:0]
.start_col (lin_rw_col), // input[6:0]
.num128_in (lin_rw_num128), // input[5:0]
.skip_next_page_in (lin_rw_xfer_partial), // input
.start (lin_wr_start), // input
.enc_cmd (seq_data3x), // output[31:0] reg
.enc_wr (seq_wr3x), // output reg
.enc_done (seq_set3x) // output reg
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET)
) mcntrl_tiled_rw_chn4_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn4_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn4_stb), // input
.status_ad (status_tiled_chn4_ad), // output[7:0]
.status_rq (status_tiled_chn4_rq), // output
.status_start (status_tiled_chn4_start), // input
.frame_start (frame_start_chn4), // input
.next_page (next_page_chn4), // input
.frame_done (frame_done_chn4), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn4), // output[15:0]
.suspend (suspend_chn4), // input
.xfer_want (want_rq4), // output
.xfer_need (need_rq4), // output
.xfer_grant (channel_pgm_en4), // input
.xfer_start_rd (tiled_rw_chn4_start_rd16), // output
.xfer_start_wr (tiled_rw_chn4_start_wr16), // output
.xfer_start32_rd (tiled_rw_chn4_start_rd32), // output
.xfer_start32_wr (tiled_rw_chn4_start_wr32), // output
.xfer_bank (tiled_rw_chn4_bank), // output[2:0]
.xfer_row (tiled_rw_chn4_row), // output[14:0]
.xfer_col (tiled_rw_chn4_col), // output[6:0]
.rowcol_inc (tiled_rw_chn4_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_rw_chn4_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_rw_chn4_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_chn4_keep_open), // output
.xfer_partial (tiled_rw_chn4_xfer_partial), // output
.xfer_page_done (seq_done4), // input
.xfer_page_rst_wr (xfer_reset_page4_wr), // output
.xfer_page_rst_rd (xfer_reset_page4_rd) // output
);
mcntrl_ps_pio #(
// PS-controlled launch of the memory controller sequences
mcntrl_ps_pio #(
.MCNTRL_PS_ADDR (MCNTRL_PS_ADDR), //'h100),
.MCNTRL_PS_MASK (MCNTRL_PS_MASK), //'h3e0),
.MCNTRL_PS_STATUS_REG_ADDR (MCNTRL_PS_STATUS_REG_ADDR), //'h2),
......@@ -1186,29 +1135,212 @@ module mcntrl393 #(
.port0_data (buf0_data), // output[31:0]
.port1_clk (axi_clk), // input
.port1_we (buf1_we), // input
.port1_we (buf0wr_we), // input
.port1_addr (buf_waddr), // input[9:0]
.port1_data (buf_wdata), // input[31:0]
.want_rq0 (want_rq0), // output reg
.need_rq0 (need_rq0), // output reg
.channel_pgm_en0 (channel_pgm_en0), // input
.seq_data0 (seq_data0), // output[9:0]
.seq_set0 (seq_set0), // output
.seq_done0 (seq_done0), // input
.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // input @negedge mclk
.buf_run0 (buf_run0), // input
.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk
.want_rq1 (want_rq1), // output reg
.need_rq1 (need_rq1), // output reg
.channel_pgm_en1 (channel_pgm_en1), // input
.seq_done1 (seq_done1), // input
.rpage_nxt_chn1 (rpage_nxt_chn1), // input
.buf_run1 (buf_run1), // input
.buf_rd_chn1 (buf_rd_chn1), // input
.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
.want_rq (want_rq0), // output reg
.need_rq (need_rq0), // output reg
.channel_pgm_en (channel_pgm_en0), // input
.seq_data (seq_data0), // output[9:0]
.seq_set (seq_set0), // output
.seq_done (seq_done0), // input
.buf_wr (buf_wr_chn0), // input @negedge mclk
.buf_wpage_nxt (buf_wpage_nxt_chn0), // input @negedge mclk
.buf_run (buf_run0), // input
.buf_wrun (buf_wrun0), // input
.buf_wdata (buf_wdata_chn0), // input[63:0]@negedge mclk
.buf_rpage_nxt (buf_rpage_nxt_chn0), // input @negedge mclk
.buf_rd (buf_rd_chn0), // input
.buf_rdata (buf_rdata_chn0) // output[63:0]
);
// multiplexer for scanline read/write (multiple channels can share it)
cmd_encod_linear_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER)
) cmd_encod_linear_mux_i (
.clk (mclk), // input
.bank1 (lin_rw_chn1_bank), // input[2:0]
.row1 (lin_rw_chn1_row), // input[14:0]
.start_col1 (lin_rw_chn1_col), // input[6:0]
.num128_1 (lin_rw_chn1_num128), // input[5:0]
.partial1 (lin_rw_chn1_partial), // input
.start1_rd (lin_rw_chn1_start_rd), // input
.start1_wr (lin_rw_chn1_start_wr), // input
.bank3 (lin_rw_chn3_bank), // input[2:0]
.row3 (lin_rw_chn3_row), // input[14:0]
.start_col3 (lin_rw_chn3_col), // input[6:0]
.num128_3 (lin_rw_chn3_num128), // input[5:0]
.partial3 (lin_rw_chn3_partial), // input
.start3_rd (lin_rw_chn3_start_rd), // input
.start3_wr (lin_rw_chn3_start_wr), // input
.bank (lin_rw_bank), // output[2:0]
.row (lin_rw_row), // output[14:0]
.start_col (lin_rw_col), // output[6:0]
.num128 (lin_rw_num128), // output[5:0]
.partial (lin_rw_xfer_partial), // output
.start_rd (lin_rw_start_rd), // output
.start_wr (lin_rw_start_wr) // output
);
// encoder for scanline read/write
cmd_encod_linear_rw #(
.ADDRESS_NUMBER(ADDRESS_NUMBER),
.COLADDR_NUMBER(COLADDR_NUMBER),
.NUM_XFER_BITS(NUM_XFER_BITS),
.CMD_PAUSE_BITS(CMD_PAUSE_BITS),
.CMD_DONE_BIT(CMD_DONE_BIT)
) cmd_encod_linear_rw_i (
.rst (rst), // input
.clk (mclk), // input
.bank_in (lin_rw_bank), // input[2:0]
.row_in (lin_rw_row), // input[14:0]
.start_col (lin_rw_col), // input[6:0]
.num128_in (lin_rw_num128), // input[5:0]
.skip_next_page_in (lin_rw_xfer_partial), // input
.start_rd (lin_rw_start_rd), // input
.start_wr (lin_rw_start_wr), // input
.start (encod_linear_start_out), // output reg
.enc_cmd (encod_linear_cmd), // output[31:0] reg
.enc_wr (encod_linear_wr), // output reg
.enc_done (encod_linear_done) // output reg
);
// multiplexer for tiles read/write (multiple channels can share it)
cmd_encod_tiled_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT)
) cmd_encod_tiled_mux_i (
.clk (mclk), // input
.bank2 (tiled_rw_chn2_bank), // input[2:0]
.row2 (tiled_rw_chn2_row), // input[14:0]
.col2 (tiled_rw_chn2_col), // input[6:0]
.rowcol_inc2 (tiled_rw_chn2_rowcol_inc), // input[13:0]
.num_rows2 (tiled_rw_chn2_num_rows_m1), // input[5:0]
.num_cols2 (tiled_rw_chn2_num_cols_m1), // input[5:0]
.keep_open2 (tiled_rw_chn2_keep_open), // input
.partial2 (tiled_rw_chn2_xfer_partial), // input
.start2_rd (tiled_rw_chn2_start_rd16), // input
.start2_wr (tiled_rw_chn2_start_wr16), // input
.start2_rd32 (tiled_rw_chn2_start_rd32), // input
.start2_wr32 (tiled_rw_chn2_start_wr32), // input
.bank4 (tiled_rw_chn4_bank), // input[2:0]
.row4 (tiled_rw_chn4_row), // input[14:0]
.col4 (tiled_rw_chn4_col), // input[6:0]
.rowcol_inc4 (tiled_rw_chn4_rowcol_inc), // input[13:0]
.num_rows4 (tiled_rw_chn4_num_rows_m1), // input[5:0]
.num_cols4 (tiled_rw_chn4_num_cols_m1), // input[5:0]
.keep_open4 (tiled_rw_chn4_keep_open), // input
.partial4 (tiled_rw_chn4_xfer_partial), // input
.start4_rd (tiled_rw_chn4_start_rd16), // input
.start4_wr (tiled_rw_chn4_start_wr16), // input
.start4_rd32 (tiled_rw_chn4_start_rd32), // input
.start4_wr32 (tiled_rw_chn4_start_wr32), // input
.bank (tiled_rw_bank), // output[2:0]
.row (tiled_rw_row), // output[14:0]
.col (tiled_rw_col), // output[6:0]
.rowcol_inc (tiled_rw_rowcol_inc), // output[13:0]
.num_rows (tiled_rw_num_rows_m1), // output[5:0]
.num_cols (tiled_rw_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_keep_open), // output
.partial (tiled_rw_xfer_partial), // output
.start_rd (tiled_rw_start_rd16), // output
.start_wr (tiled_rw_start_wr16), // output
.start_rd32 (tiled_rw_start_rd32), // output
.start_wr32 (tiled_rw_start_wr32) // output
);
// encoder for tile read/write using 16-byte wide columns
cmd_encod_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
) cmd_encod_tiled_16_rw_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start_rd (tiled_rw_start_rd16), // input
.start_wr (tiled_rw_start_wr16), // input
.start (encod_tiled16_start_out), // output reg
.enc_cmd (encod_tiled16_cmd), // output[31:0] reg
.enc_wr (encod_tiled16_wr), // output reg
.enc_done (encod_tiled16_done) // output reg
);
// encoder for tile read/write using 32-byte wide columns
cmd_encod_tiled_32_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
) cmd_encod_tiled_32_rw_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start_rd (tiled_rw_start_rd32), // input
.start_wr (tiled_rw_start_wr32), // input
.start (encod_tiled32_start_out), // output reg
.enc_cmd (encod_tiled32_cmd), // output[31:0] reg
.enc_wr (encod_tiled32_wr), // output reg
.enc_done (encod_tiled32_done) // output reg
);
// Combine sequencer data from multiple sourecs
cmd_encod_4mux cmd_encod_4mux_i (
.rst (rst), // input
.clk (mclk), // input
// from ps pio
.start0 (channel_pgm_en0), // start_seq_ps_pio), // input
.enc_cmd0 ({22'b0,seq_data0}), // input[31:0]
.enc_wr0 (1'b0), // input
.enc_done0 (seq_set0), // input
// from encod_linear_rw
.start1 (encod_linear_start_out), // input
.enc_cmd1 (encod_linear_cmd), // input[31:0]
.enc_wr1 (encod_linear_wr), // input
.enc_done1 (encod_linear_done), // input
// from encod_tiled_rw
.start2 (encod_tiled16_start_out), // input
.enc_cmd2 (encod_tiled16_cmd), // input[31:0]
.enc_wr2 (encod_tiled16_wr), // input
.enc_done2 (encod_tiled16_done), // input
// from encod_tiled_32_rw
.start3 (encod_tiled32_start_out), // input
.enc_cmd3 (encod_tiled32_cmd), // input[31:0]
.enc_wr3 (encod_tiled32_wr), // input
.enc_done3 (encod_tiled32_done), // input
.start (), // output reg not used - may be needed for cascading. Pulse before any data output
.enc_cmd (seq_data), // output[31:0] reg
.enc_wr (seq_wr), // output reg
.enc_done (seq_set) // output reg
);
......@@ -1296,82 +1428,81 @@ module mcntrl393 #(
.cmd0_we (cmd_we), // input
.cmd0_addr (buf_waddr), // input[9:0]
.cmd0_data (buf_wdata), // input[31:0]
.seq_data (seq_data), // input[31:0]
.seq_wr (seq_wr), // not used: seq_wr0), // input
.seq_set (seq_set), // input
.want_rq0 (want_rq0), // input
.need_rq0 (need_rq0), // input
.channel_pgm_en0 (channel_pgm_en0), // output reg
.seq_data0 ({22'b0,seq_data0}), // input[31:0]
.seq_wr0 (1'b0), // not used: seq_wr0), // input
.seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.rpage_nxt_chn0 (), //rpage_nxt_chn0), not used
.page_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0),
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.buf_wrun0 (buf_wrun0),
.buf_rd_chn0 (buf_rd_chn0), // output
.buf_rpage_nxt_chn0 (buf_rpage_nxt_chn0), // output
.buf_rdata_chn0 (buf_rdata_chn0), // input[63:0]
.want_rq1 (want_rq1), // input
.need_rq1 (need_rq1), // input
.channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_data1 ({22'b0,seq_data0}), // input[31:0] // same as for channel 0
.seq_wr1 (1'b0), // not used: seq_wr1), // input
.seq_set1 (seq_set0), // seq_set0 from channel 0 (shared in ps_pio), // input
.seq_done1 (seq_done1), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_run1 (buf_run1),
.page_nxt_chn1 (page_nxt_chn1), //rpage_nxt_chn0), not used
.buf_run1 (), //buf_run1),
.buf_wr_chn1 (buf_wr_chn1), // output
.buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.buf_wdata_chn1 (buf_wdata_chn1), // output[63:0]
.buf_wrun1 (), //buf_wrun1),
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rpage_nxt_chn1 (rpage_nxt_chn1), // buf_rpage_nxt_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
.need_rq2 (need_rq2), // input
.channel_pgm_en2 (channel_pgm_en2), // output reg
.seq_data2 (seq_data2x), // input[31:0]
.seq_wr2 (seq_wr2x), // input
.seq_set2 (seq_set2x), // input
.seq_done2 (seq_done2), // output
.rpage_nxt_chn2 (), // not used rpage_nxt_chn2), // output
.buf_run2 (),
.page_nxt_chn2 (page_nxt_chn2), //rpage_nxt_chn0), not used
.buf_run2 (), //buf_run2),
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.buf_wrun2 (), //buf_wrun2),
.buf_rd_chn2 (buf_rd_chn2), // output
.buf_rpage_nxt_chn2 (rpage_nxt_chn2), // buf_rpage_nxt_chn2), // output
.buf_rdata_chn2 (buf_rdata_chn2), // input[63:0]
.want_rq3 (want_rq3), // input
.need_rq3 (need_rq3), // input
.channel_pgm_en3 (channel_pgm_en3), // output reg
.seq_data3 (seq_data3x), // input[31:0]
.seq_wr3 (seq_wr3x), // input
.seq_set3 (seq_set3x), // input
.seq_done3 (seq_done3), // output
.rpage_nxt_chn3 (rpage_nxt_chn3), // output
.buf_run3 (),
.page_nxt_chn3 (page_nxt_chn3), //rpage_nxt_chn0), not used
.buf_run3 (), //buf_run3),
.buf_wr_chn3 (buf_wr_chn3), // output
.buf_wpage_nxt_chn3 (buf_wpage_nxt_chn3), // output
.buf_wdata_chn3 (buf_wdata_chn3), // output[63:0]
.buf_wrun3 (), //buf_wrun3),
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_rpage_nxt_chn3 (rpage_nxt_chn3), // buf_rpage_nxt_chn3), // output
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
.need_rq4 (need_rq4), // input
.channel_pgm_en4 (channel_pgm_en4), // output reg
.seq_data4 (seq_data4x), // input[31:0]
.seq_wr4 (seq_wr4x), // input
.seq_set4 (seq_set4x), // input
.seq_done4 (seq_done4), // output
.rpage_nxt_chn4 (rpage_nxt_chn4), // output
.buf_run4 (),
.page_nxt_chn4 (page_nxt_chn4), //rpage_nxt_chn0), not used
.buf_run4 (), //buf_run4),
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.want_rq5 (want_rq5), // input
.need_rq5 (need_rq5), // input
.channel_pgm_en5 (channel_pgm_en5), // output reg
.seq_data5 (seq_data5x), // input[31:0]
.seq_wr5 (seq_wr5x), // input
.seq_set5 (seq_set5x), // input
.seq_done5 (seq_done5), // output
.rpage_nxt_chn5 (rpage_nxt_chn5), // output
.buf_run5 (),
.buf_rd_chn5 (buf_rd_chn5), // output
.buf_rdata_chn5 (buf_rdata_chn5), // input[63:0]
.buf_wrun4 (), //buf_wrun4),
.buf_rd_chn4 (buf_rd_chn4), // output
.buf_rpage_nxt_chn4 (rpage_nxt_chn4), // buf_rpage_nxt_chn4), // output
.buf_rdata_chn4 (buf_rdata_chn4), // input[63:0]
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
......
memctrl/mcntrl393_test01.v
View file @ ad0351ef
......@@ -24,18 +24,18 @@ module mcntrl393_test01#(
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4
)(
input rst,
input mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
......@@ -46,6 +46,13 @@ module mcntrl393_test01#(
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
output frame_start_chn1, // input
output next_page_chn1, // input
input page_ready_chn1, // output
input frame_done_chn1, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1, // output[15:0]
output suspend_chn1, // input
output frame_start_chn2, // input
output next_page_chn2, // input
input page_ready_chn2, // output
......@@ -65,14 +72,7 @@ module mcntrl393_test01#(
input page_ready_chn4, // output
input frame_done_chn4, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4, // output[15:0]
output suspend_chn4, // input
output frame_start_chn5, // input
output next_page_chn5, // input
input page_ready_chn5, // output
input frame_done_chn5, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5, // output[15:0]
output suspend_chn5 // input
output suspend_chn4 // input
);
localparam PAGE_BITS=4; // number of LSB to indicate pages read/written
......@@ -80,6 +80,10 @@ module mcntrl393_test01#(
wire cmd_we;
wire [3:0] cmd_a;
wire [7:0] cmd_data;
wire [STATUS_PAYLOAD_BITS-1:0] status_chn1;
wire [7:0] status_chn1_ad;
wire status_chn1_rq;
wire status_chn1_start; // input
wire [STATUS_PAYLOAD_BITS-1:0] status_chn2;
wire [7:0] status_chn2_ad;
wire status_chn2_rq;
......@@ -92,78 +96,78 @@ module mcntrl393_test01#(
wire [7:0] status_chn4_ad;
wire status_chn4_rq;
wire status_chn4_start; // input
wire [STATUS_PAYLOAD_BITS-1:0] status_chn5;
wire [7:0] status_chn5_ad;
wire status_chn5_rq;
wire status_chn5_start; // input
reg [PAGE_BITS-1:0] page_chn1;
reg [PAGE_BITS-1:0] page_chn2;
reg [PAGE_BITS-1:0] page_chn3;
reg [PAGE_BITS-1:0] page_chn4;
reg [PAGE_BITS-1:0] page_chn5;
reg frame_start_chn1_r;
reg frame_start_chn2_r;
reg frame_start_chn3_r;
reg frame_start_chn4_r;
reg frame_start_chn5_r;
reg next_page_chn1_r;
reg next_page_chn2_r;
reg next_page_chn3_r;
reg next_page_chn4_r;
reg next_page_chn5_r;
reg suspend_chn1_r;
reg suspend_chn2_r;
reg suspend_chn3_r;
reg suspend_chn4_r;
reg suspend_chn5_r;
wire set_chn1_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN1_MODE); // set mode register for channel 1
wire set_chn1_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN1_STATUS_CNTRL); // control status reporting for channel 1
wire set_chn2_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_MODE); // set mode register for channel 2
wire set_chn2_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_STATUS_CNTRL); // control status reporting for channel 2
wire set_chn3_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_MODE); // set mode register for channel 3
wire set_chn3_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_STATUS_CNTRL); // control status reporting for channel 3
wire set_chn4_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_MODE); // set mode register for channel 4
wire set_chn4_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_STATUS_CNTRL); // control status reporting for channel 4
wire set_chn5_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN5_MODE); // set mode register for channel 5
wire set_chn5_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN5_STATUS_CNTRL); // control status reporting for channel 5
wire cmd_frame_start_w=cmd_data[0];
wire cmd_next_page_w= cmd_data[1];
wire cmd_suspend_w= cmd_data[2];
reg frame_busy_chn1;
reg frame_busy_chn2;
reg frame_busy_chn3;
reg frame_busy_chn4;
reg frame_busy_chn5;
reg frame_finished_chn1;
reg frame_finished_chn2;
reg frame_finished_chn3;
reg frame_finished_chn4;
reg frame_finished_chn5;
assign frame_start_chn1 = frame_start_chn1_r;
assign frame_start_chn2 = frame_start_chn2_r;
assign frame_start_chn3 = frame_start_chn3_r;
assign frame_start_chn4 = frame_start_chn4_r;
assign frame_start_chn5 = frame_start_chn5_r;
assign next_page_chn1 = next_page_chn1_r;
assign next_page_chn2 = next_page_chn2_r;
assign next_page_chn3 = next_page_chn3_r;
assign next_page_chn4 = next_page_chn4_r;
assign next_page_chn5 = next_page_chn5_r;
assign suspend_chn1 = suspend_chn1_r;
assign suspend_chn2 = suspend_chn2_r;
assign suspend_chn3 = suspend_chn3_r;
assign suspend_chn4 = suspend_chn4_r;
assign suspend_chn5 = suspend_chn5_r;
assign status_chn1={page_chn1,line_unfinished_chn1,frame_finished_chn1, frame_busy_chn1};
assign status_chn2={page_chn2,line_unfinished_chn2,frame_finished_chn2, frame_busy_chn2};
assign status_chn3={page_chn3,line_unfinished_chn3,frame_finished_chn3, frame_busy_chn3};
assign status_chn4={page_chn4,line_unfinished_chn4,frame_finished_chn4, frame_busy_chn4};
assign status_chn5={page_chn5,line_unfinished_chn5,frame_finished_chn5, frame_busy_chn5};
always @ (posedge mclk) begin
frame_start_chn1_r <= set_chn1_mode && cmd_frame_start_w;
frame_start_chn2_r <= set_chn2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chn3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chn4_mode && cmd_frame_start_w;
frame_start_chn5_r <= set_chn5_mode && cmd_frame_start_w;
next_page_chn1_r <= set_chn1_mode && cmd_next_page_w;
next_page_chn2_r <= set_chn2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chn3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chn4_mode && cmd_next_page_w;
next_page_chn5_r <= set_chn5_mode && cmd_next_page_w;
end
always @ (posedge rst or posedge mclk) begin
if (rst) page_chn1 <= 0;
else if (frame_start_chn1_r) page_chn1 <= 0;
else if (page_ready_chn1) page_chn1 <= page_chn1 + 1;
if (rst) page_chn2 <= 0;
else if (frame_start_chn2_r) page_chn2 <= 0;
else if (page_ready_chn2) page_chn2 <= page_chn2 + 1;
......@@ -176,9 +180,9 @@ module mcntrl393_test01#(
else if (frame_start_chn4_r) page_chn4 <= 0;
else if (page_ready_chn4) page_chn4 <= page_chn4 + 1;
if (rst) page_chn5 <= 0;
else if (frame_start_chn5_r) page_chn5 <= 0;
else if (page_ready_chn5) page_chn5 <= page_chn5 + 1;
if (rst) suspend_chn1_r <= 0;
else if (set_chn1_mode) suspend_chn1_r <= cmd_suspend_w;
if (rst) suspend_chn2_r <= 0;
else if (set_chn2_mode) suspend_chn2_r <= cmd_suspend_w;
......@@ -189,8 +193,9 @@ module mcntrl393_test01#(
if (rst) suspend_chn4_r <= 0;
else if (set_chn4_mode) suspend_chn4_r <= cmd_suspend_w;
if (rst) suspend_chn5_r <= 0;
else if (set_chn5_mode) suspend_chn5_r <= cmd_suspend_w;
if (rst) frame_busy_chn1 <= 0;
else if ( frame_start_chn1_r && !frame_done_chn1) frame_busy_chn1 <= 1;
else if (!frame_start_chn1_r && frame_done_chn1) frame_busy_chn1 <= 0;
if (rst) frame_busy_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_busy_chn2 <= 1;
......@@ -204,10 +209,10 @@ module mcntrl393_test01#(
else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;
else if (!frame_start_chn4_r && frame_done_chn4) frame_busy_chn4 <= 0;
if (rst) frame_busy_chn5 <= 0;
else if ( frame_start_chn5_r && !frame_done_chn5) frame_busy_chn5 <= 1;
else if (!frame_start_chn5_r && frame_done_chn5) frame_busy_chn5 <= 0;
if (rst) frame_finished_chn1 <= 0;
else if ( frame_start_chn1_r && !frame_done_chn1) frame_finished_chn1 <= 0;
else if (!frame_start_chn1_r && frame_done_chn1) frame_finished_chn1 <= 1;
if (rst) frame_finished_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_finished_chn2 <= 0;
else if (!frame_start_chn2_r && frame_done_chn2) frame_finished_chn2 <= 1;
......@@ -219,21 +224,17 @@ module mcntrl393_test01#(
if (rst) frame_finished_chn4 <= 0;
else if ( frame_start_chn4_r && !frame_done_chn4) frame_finished_chn4 <= 0;
else if (!frame_start_chn4_r && frame_done_chn4) frame_finished_chn4 <= 1;
if (rst) frame_finished_chn5 <= 0;
else if ( frame_start_chn5_r && !frame_done_chn5) frame_finished_chn5 <= 0;
else if (!frame_start_chn5_r && frame_done_chn5) frame_finished_chn5 <= 1;
end
always @ (posedge mclk) begin
frame_start_chn1_r <= set_chn1_mode && cmd_frame_start_w;
frame_start_chn2_r <= set_chn2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chn3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chn4_mode && cmd_frame_start_w;
frame_start_chn5_r <= set_chn5_mode && cmd_frame_start_w;
next_page_chn1_r <= set_chn1_mode && cmd_next_page_w;
next_page_chn2_r <= set_chn2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chn3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chn4_mode && cmd_next_page_w;
next_page_chn5_r <= set_chn5_mode && cmd_next_page_w;
end
cmd_deser #(
......@@ -256,23 +257,37 @@ module mcntrl393_test01#(
status_router4 status_router4_i (
.rst (rst), // input
.clk (mclk), // input
.db_in0 (status_chn2_ad), // input[7:0]
.rq_in0 (status_chn2_rq), // input
.start_in0 (status_chn2_start), // output
.db_in1 (status_chn3_ad), // input[7:0]
.rq_in1 (status_chn3_rq), // input
.start_in1 (status_chn3_start), // output
.db_in2 (status_chn4_ad), // input[7:0]
.rq_in2 (status_chn4_rq), // input
.start_in2 (status_chn4_start), // output
.db_in3 (status_chn5_ad), // input[7:0]
.rq_in3 (status_chn5_rq), // input
.start_in3 (status_chn5_start), // output
.db_in0 (status_chn1_ad), // input[7:0]
.rq_in0 (status_chn1_rq), // input
.start_in0 (status_chn1_start), // output
.db_in1 (status_chn2_ad), // input[7:0]
.rq_in1 (status_chn2_rq), // input
.start_in1 (status_chn2_start), // output
.db_in2 (status_chn3_ad), // input[7:0]
.rq_in2 (status_chn3_rq), // input
.start_in2 (status_chn3_start), // output
.db_in3 (status_chn4_ad), // input[7:0]
.rq_in3 (status_chn4_rq), // input
.start_in3 (status_chn4_start), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn1_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn1_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn1), // input[25:0]
.ad (status_chn1_ad), // output[7:0]
.rq (status_chn1_rq), // output
.start (status_chn1_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
......@@ -316,18 +331,5 @@ module mcntrl393_test01#(
.start (status_chn4_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN5_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn5_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn5_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn5), // input[25:0]
.ad (status_chn5_ad), // output[7:0]
.rq (status_chn5_rq), // output
.start (status_chn5_start) // input
);
endmodule
memctrl/mcntrl_linear_rw.v
View file @ ad0351ef
......@@ -20,7 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
// TODO: ADD MCNTRL_SCANLINE_FRAME_PAGE_RESET to caller
module mcntrl_linear_rw #(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
......@@ -29,7 +29,7 @@ module mcntrl_linear_rw #(
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_ADDR= 'h120,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write,enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
......@@ -44,7 +44,8 @@ module mcntrl_linear_rw #(
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
// parameter MCNTRL_SCANLINE_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
)(
input rst,
input mclk,
......@@ -67,16 +68,16 @@ module mcntrl_linear_rw #(
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
output xfer_start, // initiate a transfer (next cycle after xfer_grant)
output xfer_start_rd, // initiate a transfer (next cycle after xfer_grant)
output xfer_start_wr, // initiate a transfer (next cycle after xfer_grant)
output [2:0] xfer_bank, // bank address
output [ADDRESS_NUMBER-1:0] xfer_row, // memory row
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
output [NUM_XFER_BITS-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output xfer_partial, // partial tile (first of 2) , sequencer will not generate page_next at the end of block
input xfer_done, // transfer to/from the buffer finished
output xfer_reset_page // reset internal buffer page to zero
// output [1:0] xfer_page // page number for transfer (goes to channel buffer memory-side adderss)
output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge
output xfer_page_rst_rd // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
);
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
......@@ -109,17 +110,23 @@ module mcntrl_linear_rw #(
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r; // 1 hot started by xfer start only (not by parameter change)
reg [2:0] xfer_start_r; // 1 hot started by xfer start only (not by parameter change)
reg xfer_start_rd_r;
reg xfer_start_wr_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channle (continue ones in progress)
wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off
reg xfer_reset_page_r;
// reg xfer_reset_page_r;
reg xfer_page_rst_r=1;
reg xfer_page_rst_pos=1;
reg xfer_page_rst_neg=1;
reg [2:0] page_cntr;
wire cmd_wrmem=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
reg busy_r;
reg want_r;
......@@ -150,8 +157,8 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
// reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write_mode,enable,!reset}
reg [3:0] mode_reg;//mode register: {extra_pages[1:0],enable,!reset}
// reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write,enable,!reset}
reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
// reg [FRAME_WIDTH_BITS:0] frame_width; // (programmed) 0- max
......@@ -177,7 +184,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[3:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[4:0]; // [4:0];
if (rst) start_addr <= 0;
else if (set_start_addr_w) start_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
......@@ -212,10 +219,15 @@ module mcntrl_linear_rw #(
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
// assign xfer_num128= xfer_num128_m1_r[NUM_XFER_BITS-1:0];
assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
assign xfer_start= xfer_start_r[0];
// assign xfer_start= xfer_start_r[0];
assign xfer_start_rd= xfer_start_rd_r;
assign xfer_start_wr= xfer_start_wr_r;
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
// assign xfer_page= xfer_page_r;
assign xfer_reset_page = xfer_reset_page_r;
// assign xfer_reset_page = xfer_reset_page_r;
assign xfer_page_rst_wr= xfer_page_rst_r;
assign xfer_page_rst_rd= xfer_page_rst_neg;
assign xfer_partial= xfer_limited_by_mem_page_r;
assign frame_done= frame_done_r;
......@@ -234,8 +246,8 @@ module mcntrl_linear_rw #(
assign line_unfinished=line_unfinished_r[1];
assign chn_en = &mode_reg[1:0]; // enable requests by channle (continue ones in progress)
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
// assign cmd_wrmem = mode_reg[4];// 0: read from memory, 1:write to memory
assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
......@@ -257,27 +269,6 @@ module mcntrl_linear_rw #(
next_y <= curr_y + 1;
row_left <= window_width - curr_x; // 14 bits - 13 bits
end
/*
if (recalc_r[1]) begin // cycle 2
mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?
(1<<NUM_XFER_BITS):
row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
end
if (recalc_r[2]) begin // cycle 3
xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_xfer;
xfer_num128_r<= continued_xfer?
{EXTRA_BITS,leftover}:
(xfer_limited_by_mem_page?
mem_page_left[NUM_XFER_BITS:0]:
lim_by_xfer[NUM_XFER_BITS:0]);
leftover <= remainder_in_xfer[NUM_XFER_BITS-1:0];
end
if (recalc_r[3]) begin // cycle 4
last_in_row <= last_in_row_w; //(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
end
*/
// registers to be absorbed in DSP block
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2
frame_full_width_r <= frame_full_width;
......@@ -362,6 +353,12 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (rst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem;
if (rst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (rst) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
......@@ -378,7 +375,12 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
xfer_reset_page_r <= chn_rst; // || frame_start ; // TODO: Check if it is better to reset page on frame start?
// xfer_reset_page_r <= chn_rst; // || frame_start ; // TODO: Check if it is better to reset page on frame start?
if (rst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start & cmd_wrmem):1'b0);
if (rst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_SCANLINE_FRAME_PAGE_RESET ? (frame_start & ~cmd_wrmem):1'b0);
// increment x,y (two cycles)
......@@ -417,7 +419,9 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (xfer_grant && cmd_wrmem) line_unfinished_r[1] <= line_unfinished_r[0];
end
always @ (negedge mclk) begin
xfer_page_rst_neg <= xfer_page_rst_pos;
end
cmd_deser #(
.ADDR (MCNTRL_SCANLINE_ADDR),
.ADDR_MASK (MCNTRL_SCANLINE_MASK),
......
memctrl/mcntrl_ps_pio.v
View file @ ad0351ef
......@@ -53,33 +53,27 @@ module mcntrl_ps_pio#(
input [31:0] port1_data,
// memory controller interface
// read port 0
output reg want_rq0,
output reg need_rq0,
input channel_pgm_en0,
output [9:0] seq_data0, // only address
output seq_set0,
input seq_done0,
input buf_wr_chn0,
input buf_wpage_nxt_chn0,
input buf_run0, // @ negedge, use to force page nimber in the buffer (use fifo)
input [63:0] buf_wdata_chn0,
// write port 1
output reg want_rq1,
output reg need_rq1,
input channel_pgm_en1,
input seq_done1,
input rpage_nxt_chn1,
input buf_run1, // @ posedge, use to force page nimber in the buffer (use fifo)
input buf_rd_chn1,
output [63:0] buf_rdata_chn1
output reg want_rq,
output reg need_rq,
input channel_pgm_en,
output [9:0] seq_data, // only address
output seq_set,
input seq_done,
input buf_wr,
input buf_wpage_nxt,
input buf_run, // @ posedge, use to force page nimber in the buffer (use fifo)
input buf_wrun, // @ negedge, use to force page nimber in the buffer (use fifo)
input [63:0] buf_wdata,
input buf_rpage_nxt,
input buf_rd, //buf_rd_chn1,
output [63:0] buf_rdata // buf_rdata_chn1
);
localparam CMD_WIDTH=15;
localparam CMD_FIFO_DEPTH=4;
localparam PAGE_FIFO_DEPTH = 4;// fifo depth to hold page numbers for channels (2 bits should be OK now)
localparam PAGE_CNTR_BITS = 4;
wire channel_pgm_en=channel_pgm_en0 || channel_pgm_en1;
wire seq_done= seq_done0 || seq_done1;
reg [PAGE_CNTR_BITS-1:0] pending_pages;
......@@ -104,31 +98,38 @@ module mcntrl_ps_pio#(
wire short_busy; // does not include memory transaction
wire start;
//reg [1:0] page;
reg [1:0] page_neg;
reg [1:0] cmd_set_d;
// command bit fields
wire [9:0] cmd_seq_a= cmd_out[9:0];
wire [1:0] cmd_page= cmd_out[11:10];
wire cmd_need= cmd_out[12];
wire cmd_chn= cmd_out[13];
wire cmd_wr= cmd_out[13]; // chn= cmd_out[13]; command write, not read
wire cmd_wait= cmd_out[14]; // wait cmd finished before proceeding
reg cmd_set;
reg cmd_wait_r;
reg channel_pgm_en0_neg;
wire [1:0] page_out_chn0;
wire [1:0] page_out_chn1;
wire [1:0] page_out;
reg nreset_page_fifo;
reg nreset_page_fifo_neg;
// wire page_fifo0_nempty_neg;
// wire page_fifo1_nempty;
// reg page_fifo0_nempty;
wire cmd_wr_out;
reg [1:0] page_out_r;
reg [1:0] page_out_r_negedge;
reg page_r_set;
reg page_w_set_early;
reg page_w_set_early_negedge;
reg en_page_w_set;
reg page_w_set_negedge;
assign short_busy= want_rq0 || need_rq0 ||want_rq1 || need_rq1 || cmd_set; // cmd_set - advance FIFO
// assign short_busy= want_rq || need_rq ||want_rq1 || need_rq1 || cmd_set; // cmd_set - advance FIFO
assign short_busy= want_rq || need_rq || cmd_set; // cmd_set - advance FIFO
assign busy= short_busy || (pending_pages != 0); // mem_run;
assign start= chn_en && !short_busy && cmd_nempty && ((pending_pages == 0) || !cmd_wait_r); //(!mem_run || !cmd_wait_r); // do not wait memory transaction if wait
assign seq_data0= cmd_seq_a;
assign seq_set0=cmd_set;
assign seq_data= cmd_seq_a;
assign seq_set=cmd_set;
assign status_data= {cmd_half_full,cmd_nempty | busy};
assign set_cmd_w = cmd_we && (cmd_a== MCNTRL_PS_CMD);
assign set_status_w = cmd_we && (cmd_a== MCNTRL_PS_STATUS_CNTRL);
......@@ -149,25 +150,16 @@ module mcntrl_ps_pio#(
else if (set_en_rst) en_reset <= cmd_data[1:0];
if (rst) begin
want_rq0 <= 0;
need_rq0 <= 0;
want_rq1 <= 0;
need_rq1 <= 0;
want_rq <= 0;
need_rq <= 0;
end else if (chn_rst || channel_pgm_en) begin
want_rq0 <= 0;
need_rq0 <= 0;
want_rq1 <= 0;
need_rq1 <= 0;
want_rq <= 0;
need_rq <= 0;
end else if (start) begin
want_rq0 <= !cmd_chn;
need_rq0 <= !cmd_chn && cmd_need;
want_rq1 <= cmd_chn;
need_rq1 <= cmd_chn && cmd_need;
want_rq <= 1; // !cmd_chn;
need_rq <= cmd_need; // !cmd_chn && cmd_need;
end
// if (rst) mem_run <=0;
// else if (chn_rst || seq_done) mem_run <=0;
// else if (channel_pgm_en) mem_run <=1;
if (rst) cmd_set <= 0;
else if (chn_rst) cmd_set <= 0;
......@@ -175,19 +167,10 @@ module mcntrl_ps_pio#(
if (rst) cmd_set_d <= 0;
else cmd_set_d <= {cmd_set_d[0],cmd_set& ~cmd_chn}; // only for channel0 (memory read)
// if (rst) page_fifo0_nempty <= 0;
// else page_fifo0_nempty <=page_fifo0_nempty_neg;
// else cmd_set_d <= {cmd_set_d[0],cmd_set& ~cmd_chn}; // only for channel0 (memory read)
else cmd_set_d <= {cmd_set_d[0],cmd_set & ~cmd_wr}; // only for channel0 (memory read)
end
always @ (negedge mclk) begin
page_neg <= cmd_page; // page;
// wpage_set_chn0_neg <= cmd_set_d[1];
nreset_page_fifo_neg <= nreset_page_fifo;
channel_pgm_en0_neg <= channel_pgm_en0;
end
cmd_deser #(
.ADDR (MCNTRL_PS_ADDR),
......@@ -251,12 +234,12 @@ fifo_same_clock #(
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.wpage_in (page_out_chn0), // page_neg), // input[1:0]
.wpage_set (buf_run0), //wpage_set_chn0_neg), // input
.page_next (buf_wpage_nxt_chn0), // input
.wpage_in (page_out_r_negedge), // page_neg), // input[1:0]
.wpage_set (page_w_set_negedge), //wpage_set_chn0_neg), // input
.page_next (buf_wpage_nxt), // input
.page (), // output[1:0]
.we (buf_wr_chn0), // input
.data_in (buf_wdata_chn0) // input[63:0]
.we (buf_wr), // input
.data_in (buf_wdata) // input[63:0]
);
// Port 1 (write DDR from AXI) buffer
......@@ -264,45 +247,51 @@ fifo_same_clock #(
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
.ext_data_in (port1_data), // input[31:0]
.rclk (mclk), // input
.rpage_in (page_out_chn1), //page), // input[1:0]
.rpage_set (buf_run1), // rpage_set_chn1), // input
.page_next (rpage_nxt_chn1), // input
.rpage_in (page_out_r), //page), // input[1:0]
.rpage_set (page_r_set), // rpage_set_chn1), // input
.page_next (buf_rpage_nxt), // input
.page (), // output[1:0]
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
fifo_same_clock #(
.DATA_WIDTH(2),
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo0_i (
.rst (rst),
.clk (!mclk), // negedge
.sync_rst (!nreset_page_fifo_neg), // synchronously reset fifo;
.we (channel_pgm_en0_neg),
.re (buf_run0),
.data_in (page_neg),
.data_out (page_out_chn0),
.nempty (), //page_fifo0_nempty_neg),
.half_full ()
.rd (buf_rd), // input
.data_out (buf_rdata) // output[63:0]
);
fifo_same_clock #(
.DATA_WIDTH(2),
.DATA_WIDTH(3),
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo1_i (
.rst (rst),
.clk (mclk), // posedge
.sync_rst (!nreset_page_fifo), // synchronously reset fifo;
.we (channel_pgm_en1),
.re (buf_run1),
.data_in (cmd_page), //page),
.data_out (page_out_chn1),
.we (channel_pgm_en),
.re (buf_run),
.data_in ({cmd_wr,cmd_page}), //page),
.data_out ({cmd_wr_out,page_out}),
.nempty (), //page_fifo1_nempty),
.half_full ()
);
always @ (posedge rst or posedge mclk) begin
if (rst) page_out_r <= 0;
else if (buf_run) page_out_r <= page_out;
end
always @ (posedge mclk) begin
page_r_set <= cmd_wr_out && buf_run; // page_out_r, page_r_set - output to buffer
page_w_set_early <= !cmd_wr_out && buf_run;
end
always @ (negedge mclk) begin
nreset_page_fifo_neg <= nreset_page_fifo;
page_w_set_early_negedge <= page_w_set_early;
page_out_r_negedge <= page_out_r;
if (!nreset_page_fifo_neg || buf_wrun) en_page_w_set <= 0;
else if (page_w_set_early_negedge) en_page_w_set <= 1;
page_w_set_negedge <= en_page_w_set && buf_wrun;
end
endmodule
memctrl/mcntrl_tiled_rw.v
View file @ ad0351ef
......@@ -30,7 +30,7 @@ module mcntrl_tiled_rw#(
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
......@@ -47,8 +47,8 @@ module mcntrl_tiled_rw#(
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MCNTRL_TILED_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0 // reset internal page number to zero at the frame start (false - only when hard/soft reset)
// parameter MCNTRL_TILED_WRITE_MODE = 1'b0 // module is configured to write tiles to external memory (false - read tiles)
)(
input rst,
input mclk,
......@@ -71,7 +71,11 @@ module mcntrl_tiled_rw#(
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
output xfer_start, // initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid
// output xfer_start, // initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid
output xfer_start_rd, // initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid
output xfer_start_wr, // initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid
output xfer_start32_rd, // initiate a transfer to 32-byte wide colums scanning in each tile
output xfer_start32_wr, // initiate a transfer to 32-byte wide colums scanning in each tile
output [2:0] xfer_bank, // start bank address
output [ADDRESS_NUMBER-1:0] xfer_row, // memory row
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
......@@ -81,7 +85,8 @@ module mcntrl_tiled_rw#(
output keep_open, // (programmable bit)keep banks open (for <=8 banks only
output xfer_partial, // partial tile (first of 2) , sequencer will not generate page_next at the end of block
input xfer_page_done, // transfer to/from the buffer finished (partial transfers should not generate), use rpage_nxt_chn@mclk
output xfer_page_rst // reset buffer internal page - at each frame start or when specifically reset
output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge
output xfer_page_rst_rd // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
);
// FIXME: not all tile heights are valid (because of the banks)
......@@ -113,18 +118,25 @@ module mcntrl_tiled_rw#(
reg [MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
reg xfer_start_rd_r;
reg xfer_start_wr_r;
reg xfer_start32_rd_r;
reg xfer_start32_wr_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channle (continue ones in progress)
wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off
reg xfer_page_rst_r=1;
reg xfer_page_rst_r=1;
reg xfer_page_rst_pos=1;
reg xfer_page_rst_neg=1;
reg [2:0] page_cntr; // to maintain requests - difference between client requests and generated requests
// partial (truncated by memory page) generated requests should not count
wire cmd_wrmem= MCNTRL_TILED_WRITE_MODE; // 0: read from memory, 1:write to memory (change to parameter?)
wire cmd_wrmem; //= MCNTRL_TILED_WRITE_MODE; // 0: read from memory, 1:write to memory (change to parameter?)
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire byte32; // use 32-byte wide colums in each tile (0 - use 16-byte ones)
reg busy_r;
reg want_r;
reg need_r;
......@@ -159,7 +171,7 @@ module mcntrl_tiled_rw#(
wire tile_vstep_zero= !(|cmd_data[16+:MAX_TILE_HEIGHT]);
// reg [5:0] mode_reg;//mode register: {write_mode,keep_open,extra_pages[1:0],enable,!reset}
reg [4:0] mode_reg;//mode register: {keep_open,extra_pages[1:0],enable,!reset}
reg [6:0] mode_reg;//mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
......@@ -193,7 +205,7 @@ module mcntrl_tiled_rw#(
// Set parameter registers
always @(posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[4:0]; // [5:0];
else if (set_mode_w) mode_reg <= cmd_data[6:0]; // [5:0];
if (rst) start_addr <= 0;
else if (set_start_addr_w) start_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
......@@ -237,7 +249,11 @@ module mcntrl_tiled_rw#(
end
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
assign xfer_start= xfer_start_r[0];
// assign xfer_start= xfer_start_r[0];
assign xfer_start_rd= xfer_start_rd_r;
assign xfer_start_wr= xfer_start_wr_r;
assign xfer_start32_rd= xfer_start32_rd_r;
assign xfer_start32_wr= xfer_start32_wr_r;
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign frame_done= frame_done_r;
assign frame_finished= frame_finished_r;
......@@ -258,9 +274,10 @@ module mcntrl_tiled_rw#(
assign line_unfinished=line_unfinished_r1;
assign chn_en = &mode_reg[1:0]; // enable requests by channle (continue ones in progress)
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
assign keep_open= mode_reg[4]; // keep banks open (will be used only if number of rows <= 8
// assign cmd_wrmem = mode_reg[5];// 0: read from memory, 1:write to memory
assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
assign keep_open= mode_reg[5]; // keep banks open (will be used only if number of rows <= 8
assign byte32= mode_reg[6]; // use 32-byte wide columns in each tile (false - 16-byte)
assign status_data= {frame_finished_r, busy_r};
assign pgm_param_w= cmd_we;
assign rowcol_inc= frame_full_width;
......@@ -271,7 +288,10 @@ module mcntrl_tiled_rw#(
assign remainder_tile_width = {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
// assign buf_skip_reset= continued_tile; // buf_skip_reset_r;
assign xfer_page_rst= xfer_page_rst_r;
// assign xfer_page_rst= xfer_page_rst_r;
assign xfer_page_rst_wr= xfer_page_rst_r;
assign xfer_page_rst_rd= xfer_page_rst_neg;
assign xfer_partial= xfer_limited_by_mem_page_r;
integer i;
......@@ -353,6 +373,18 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (rst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32;
if (rst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32;
if (rst) xfer_start32_rd_r <= 0;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32;
if (rst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
if (rst) continued_tile <= 1'b0;
else if (chn_rst) continued_tile <= 1'b0;
else if (frame_start) continued_tile <= 1'b0;
......@@ -374,7 +406,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
if (rst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? frame_start:1'b0);
else xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start & cmd_wrmem):1'b0);
if (rst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start & ~cmd_wrmem):1'b0);
// increment x,y (two cycles)
if (rst) curr_x <= 0;
......@@ -387,7 +422,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (rst) last_block <= 0;
else if (chn_rst || !busy_r) last_block <= 0;
// else if (last_row_w && last_in_row_w) last_block <= 1;
else if (xfer_start_r[0]) last_block <= last_row_w && last_in_row_w;
// start_not_partial is not generated when partial (first of 2, caused by a tile crossing memory page) transfer is requested
......@@ -396,8 +430,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_page_done) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_page_done) pending_xfers <= pending_xfers - 1; // page done is not generated on partial (first) pages
// else if ( start_not_partial && !xfer_page_done) pending_xfers <= pending_xfers + 1;
// else if (!start_not_partial && xfer_page_done) pending_xfers <= pending_xfers - 1; // page done is not generated on partial (first) pages
// single cycle (sent out)
if (rst) frame_done_r <= 0;
......@@ -409,19 +441,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (frame_done_r) frame_finished_r <= 1;
//line_unfinished_r cmd_wrmem
/*
if (rst) line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r[0] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (rst) line_unfinished_r[1] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r[1] <= window_y0+start_y;
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[1] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[1] <= line_unfinished_r[0];
*/
if (rst) line_unfinished_r0 <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start) line_unfinished_r0 <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r0 <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
......@@ -434,7 +453,9 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (xfer_grant && cmd_wrmem) line_unfinished_r1 <= line_unfinished_r0;
end
always @ (negedge mclk) begin
xfer_page_rst_neg <= xfer_page_rst_pos;
end
cmd_deser #(
.ADDR (MCNTRL_TILED_ADDR),
.ADDR_MASK (MCNTRL_TILED_MASK),
......
memctrl/memctrl16.v
View file @ ad0351ef
......@@ -152,6 +152,10 @@ module memctrl16 #(
input cmd0_we, // write enble to write commend sequencer from PS
input [9:0] cmd0_addr, // address write commend sequencer from PS
input [31:0] cmd0_data, // data to write commend sequencer from PS
input [31:0] seq_data, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr, // strobe for writing sequencer data (address is autoincremented)
input seq_set, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
// channel interfaces TODO: move request/grant here, add "done"
// channel 0 interface
......@@ -159,18 +163,18 @@ module memctrl16 #(
input want_rq0, // both want_rq and need_rq should go inactive after being granted
input need_rq0, // want_rq should be active when need_rq is.
output reg channel_pgm_en0, // channel can program sequence data
input [31:0] seq_data0, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr0, // strobe for writing sequencer data (address is autoincremented)
input seq_set0, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done0, // sequencer finished executing sequence for this channel
output rpage_nxt_chn0,
output buf_run0, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn0,
output buf_run0, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn0
output buf_wr_chn0, // @ negedge mclk
output buf_wpage_nxt_chn0, // @ negedge mclk
output [63:0] buf_wdata_chn0, // @ negedge mclk
`else
output buf_wrun0, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn0
output buf_rd_chn0,
output buf_rpage_nxt_chn0,
input [63:0] buf_rdata_chn0,
`endif
`endif
......@@ -180,18 +184,18 @@ module memctrl16 #(
input want_rq1, // both want_rq and need_rq should go inactive after being granted
input need_rq1,
output reg channel_pgm_en1, // channel can program sequence data
input [31:0] seq_data1, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr1, // strobe for writing sequencer data (address is autoincremented)
input seq_set1, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done1, // sequencer finished executing sequence for this channel
output rpage_nxt_chn1,
output buf_run1, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn1,
output buf_run1, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn1
output buf_wr_chn1, // @ negedge mclk
output buf_wpage_nxt_chn1,// @ negedge mclk
output [63:0] buf_wdata_chn1,// @ negedge mclk
`else
output buf_wrun1, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn1
output buf_rd_chn1,
output buf_rpage_nxt_chn1,
input [63:0] buf_rdata_chn1,
`endif
`endif
......@@ -201,18 +205,18 @@ module memctrl16 #(
input want_rq2, // both want_rq and need_rq should go inactive after being granted
input need_rq2,
output reg channel_pgm_en2, // channel can program sequence data
input [31:0] seq_data2, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr2, // strobe for writing sequencer data (address is autoincremented)
input seq_set2, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done2, // sequencer finished executing sequence for this channel
output rpage_nxt_chn2,
output buf_run2, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn2,
output buf_run2, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn2
output buf_wr_chn2,
output buf_wpage_nxt_chn2,
output [63:0] buf_wdata_chn2,
`else
output buf_wrun2, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn2
output buf_rd_chn2,
output buf_rpage_nxt_chn2,
input [63:0] buf_rdata_chn2,
`endif
`endif
......@@ -222,18 +226,18 @@ module memctrl16 #(
input want_rq3, // both want_rq and need_rq should go inactive after being granted
input need_rq3,
output reg channel_pgm_en3, // channel can program sequence data
input [31:0] seq_data3, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr3, // strobe for writing sequencer data (address is autoincremented)
input seq_set3, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done3, // sequencer finished executing sequence for this channel
output rpage_nxt_chn3,
output buf_run3, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn3,
output buf_run3, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn3
output buf_wr_chn3,
output buf_wpage_nxt_chn3,
output [63:0] buf_wdata_chn3,
`else
output buf_wrun3, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn3
output buf_rd_chn3,
output buf_rpage_nxt_chn3,
input [63:0] buf_rdata_chn3,
`endif
`endif
......@@ -243,18 +247,18 @@ module memctrl16 #(
input want_rq4, // both want_rq and need_rq should go inactive after being granted
input need_rq4,
output reg channel_pgm_en4, // channel can program sequence data
input [31:0] seq_data4, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr4, // strobe for writing sequencer data (address is autoincremented)
input seq_set4, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done4, // sequencer finished executing sequence for this channel
output rpage_nxt_chn4,
output buf_run4, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn4,
output buf_run4, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn4
output buf_wr_chn4, // @ negedge mclk
output buf_wpage_nxt_chn4, // @ negedge mclk
output [63:0] buf_wdata_chn4, // @ negedge mclk
`else
output buf_wrun4, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn4
output buf_rd_chn4,
output buf_rpage_nxt_chn4,
input [63:0] buf_rdata_chn4,
`endif
`endif
......@@ -264,18 +268,18 @@ module memctrl16 #(
input want_rq5, // both want_rq and need_rq should go inactive after being granted
input need_rq5,
output reg channel_pgm_en5, // channel can program sequence data
input [31:0] seq_data5, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr5, // strobe for writing sequencer data (address is autoincremented)
input seq_set5, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done5, // sequencer finished executing sequence for this channel
output rpage_nxt_chn5,
output buf_run5, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn5,
output buf_run5, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn5
output buf_wr_chn5, // @ negedge mclk
output buf_wpage_nxt_chn5, // @ negedge mclk
output [63:0] buf_wdata_chn5, // @ negedge mclk
`else
output buf_wrun5, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn5
output buf_rd_chn5,
output buf_rpage_nxt_chn5,
input [63:0] buf_rdata_chn5,
`endif
`endif
......@@ -285,18 +289,18 @@ module memctrl16 #(
input want_rq6, // both want_rq and need_rq should go inactive after being granted
input need_rq6,
output reg channel_pgm_en6, // channel can program sequence data
input [31:0] seq_data6, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr6, // strobe for writing sequencer data (address is autoincremented)
input seq_set6, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done6, // sequencer finished executing sequence for this channel
output rpage_nxt_chn6,
output buf_run6, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn6,
output buf_run6, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn6
output buf_wr_chn6, // @ negedge mclk
output buf_wpage_nxt_chn6, // @ negedge mclk
output [63:0] buf_wdata_chn6, // @ negedge mclk
`else
output buf_wrun6, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn6
output buf_rd_chn6,
output buf_rpage_nxt_chn6,
input [63:0] buf_rdata_chn6,
`endif
`endif
......@@ -306,18 +310,18 @@ module memctrl16 #(
input want_rq7, // both want_rq and need_rq should go inactive after being granted
input need_rq7,
output reg channel_pgm_en7, // channel can program sequence data
input [31:0] seq_data7, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr7, // strobe for writing sequencer data (address is autoincremented)
input seq_set7, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done7, // sequencer finished executing sequence for this channel
output rpage_nxt_chn7,
output buf_run7, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn7,
output buf_run7, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn7
output buf_wr_chn7, // @ negedge mclk
output buf_wpage_nxt_chn7, // @ negedge mclk
output [63:0] buf_wdata_chn7, // @ negedge mclk
`else
output buf_wrun7, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn7
output buf_rd_chn7,
output buf_rpage_nxt_chn7,
input [63:0] buf_rdata_chn7,
`endif
`endif
......@@ -327,18 +331,18 @@ module memctrl16 #(
input want_rq8, // both want_rq and need_rq should go inactive after being granted
input need_rq8,
output reg channel_pgm_en8, // channel can program sequence data
input [31:0] seq_data8, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr8, // strobe for writing sequencer data (address is autoincremented)
input seq_set8, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done8, // sequencer finished executing sequence for this channel
output rpage_nxt_chn8,
output buf_run8, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn8,
output buf_run8, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn8
output buf_wr_chn8, // @ negedge mclk
output buf_wpage_nxt_chn8, // @ negedge mclk
output [63:0] buf_wdata_chn8, // @ negedge mclk
`else
output buf_wrun8, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn8
output buf_rd_chn8,
output buf_rpage_nxt_chn8,
input [63:0] buf_rdata_chn8,
`endif
`endif
......@@ -348,18 +352,18 @@ module memctrl16 #(
input want_rq9, // both want_rq and need_rq should go inactive after being granted
input need_rq9,
output reg channel_pgm_en9, // channel can program sequence data
input [31:0] seq_data9, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr9, // strobe for writing sequencer data (address is autoincremented)
input seq_set9, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done9, // sequencer finished executing sequence for this channel
output rpage_nxt_chn9,
output buf_run9, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn9,
output buf_run9, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn9
output buf_wr_chn9, // @ negedge mclk
output buf_wpage_nxt_chn9, // @ negedge mclk
output [63:0] buf_wdata_chn9, // @ negedge mclk
`else
output buf_wrun9, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn9
output buf_rd_chn9,
output buf_rpage_nxt_chn9,
input [63:0] buf_rdata_chn9,
`endif
`endif
......@@ -369,18 +373,18 @@ module memctrl16 #(
input want_rq10, // both want_rq and need_rq should go inactive after being granted
input need_rq10,
output reg channel_pgm_en10, // channel can program sequence data
input [31:0] seq_data10, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr10, // strobe for writing sequencer data (address is autoincremented)
input seq_set10, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done10, // sequencer finished executing sequence for this channel
output rpage_nxt_chn10,
output buf_run10, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn10,
output buf_run10, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn10
output buf_wr_chn10, // @ negedge mclk
output buf_wpage_nxt_chn10, // @ negedge mclk
output [63:0] buf_wdata_chn10, // @ negedge mclk
`else
output buf_wrun10, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn10
output buf_rd_chn10,
output buf_rpage_nxt_chn10,
input [63:0] buf_rdata_chn10,
`endif
`endif
......@@ -390,18 +394,18 @@ module memctrl16 #(
input want_rq11, // both want_rq and need_rq should go inactive after being granted
input need_rq11,
output reg channel_pgm_en11, // channel can program sequence data
input [31:0] seq_data11, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr11, // strobe for writing sequencer data (address is autoincremented)
input seq_set11, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done11, // sequencer finished executing sequence for this channel
output rpage_nxt_chn11,
output buf_run11, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn11,
output buf_run11, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn11
output buf_wr_chn11, // @ negedge mclk
output buf_wpage_nxt_chn11, // @ negedge mclk
output [63:0] buf_wdata_chn11, // @ negedge mclk
`else
output buf_wrun11, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn11
output buf_rd_chn11,
output buf_rpage_nxt_chn11,
input [63:0] buf_rdata_chn11,
`endif
`endif
......@@ -411,18 +415,18 @@ module memctrl16 #(
input want_rq12, // both want_rq and need_rq should go inactive after being granted
input need_rq12,
output reg channel_pgm_en12, // channel can program sequence data
input [31:0] seq_data12, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr12, // strobe for writing sequencer data (address is autoincremented)
input seq_set12, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done12, // sequencer finished executing sequence for this channel
output rpage_nxt_chn12,
output buf_run12, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn12,
output buf_run12, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn12
output buf_wr_chn12, // @ negedge mclk
output buf_wpage_nxt_chn12, // @ negedge mclk
output [63:0] buf_wdata_chn12, // @ negedge mclk
`else
output buf_wrun12, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn12
output buf_rd_chn12,
output buf_rpage_nxt_chn12,
input [63:0] buf_rdata_chn12,
`endif
`endif
......@@ -432,18 +436,18 @@ module memctrl16 #(
input want_rq13, // both want_rq and need_rq should go inactive after being granted
input need_rq13,
output reg channel_pgm_en13, // channel can program sequence data
input [31:0] seq_data13, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr13, // strobe for writing sequencer data (address is autoincremented)
input seq_set13, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done13, // sequencer finished executing sequence for this channel
output rpage_nxt_chn13,
output buf_run13, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn13,
output buf_run13, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn13
output buf_wr_chn13, // @ negedge mclk
output buf_wpage_nxt_chn13, // @ negedge mclk
output [63:0] buf_wdata_chn13, // @ negedge mclk
`else
output buf_wrun13, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn13
output buf_rd_chn13,
output buf_rpage_nxt_chn13,
input [63:0] buf_rdata_chn13,
`endif
`endif
......@@ -453,18 +457,18 @@ module memctrl16 #(
input want_rq14, // both want_rq and need_rq should go inactive after being granted
input need_rq14,
output reg channel_pgm_en14, // channel can program sequence data
input [31:0] seq_data14, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr14, // strobe for writing sequencer data (address is autoincremented)
input seq_set14, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done14, // sequencer finished executing sequence for this channel
output rpage_nxt_chn14,
output buf_run14, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn14,
output buf_run14, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn14
output buf_wr_chn14, // @ negedge mclk
output buf_wpage_nxt_chn14, // @ negedge mclk
output [63:0] buf_wdata_chn14, // @ negedge mclk
`else
output buf_wrun14, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn14
output buf_rd_chn14,
output buf_rpage_nxt_chn14,
input [63:0] buf_rdata_chn14,
`endif
`endif
......@@ -474,18 +478,18 @@ module memctrl16 #(
input want_rq15, // both want_rq and need_rq should go inactive after being granted
input need_rq15,
output reg channel_pgm_en15, // channel can program sequence data
input [31:0] seq_data15, //16x32 data to be written to the sequencer (and start address for software-based sequencer)
input seq_wr15, // strobe for writing sequencer data (address is autoincremented)
input seq_set15, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done15, // sequencer finished executing sequence for this channel
output rpage_nxt_chn15,
output buf_run15, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
output page_nxt_chn15,
output buf_run15, // external buffer run (may be used to force page) @posedge mclk
`ifdef def_read_mem_chn15
output buf_wr_chn15, // @ negedge mclk
output buf_wpage_nxt_chn15, // @ negedge mclk
output [63:0] buf_wdata_chn15, // @ negedge mclk
`else
output buf_wrun15, // external buffer run with delays compensated fro write, reclocked to @negedge
`endif
`ifdef def_write_mem_chn15
output buf_rd_chn15,
output buf_rpage_nxt_chn15,
input [63:0] buf_rdata_chn15,
`endif
`endif
......@@ -524,6 +528,7 @@ wire rst=rst_in; // TODO: decide where toi generate
wire ext_buf_rd;
wire ext_buf_rpage_nxt;
wire ext_buf_page_nxt;
// wire [6:0] ext_buf_raddr;
wire [3:0] ext_buf_rchn;
wire ext_buf_rrefresh;
......@@ -540,9 +545,6 @@ wire rst=rst_in; // TODO: decide where toi generate
wire [15:0] want_rq; // both want_rq and need_rq should go inactive after being granted
wire [15:0] need_rq;
reg [31:0] seq_data; //16x32 data to be written to the sequencer (and start address for software-based sequencer)
reg seq_wr; // strobe for writing sequencer data (address is autoincremented)
reg seq_set; // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
// status data from phy (sequencer)
wire [7:0] status_ad_phy;
......@@ -935,8 +937,9 @@ end
.status_ad (status_ad_phy), // output[7:0]
.status_rq (status_rq_phy), // output
.status_start (status_start_phy), // input
.ext_buf_page_nxt (ext_buf_page_nxt),
.ext_buf_rd (ext_buf_rd), // output
.ext_buf_rpage_nxt (ext_buf_rpage_nxt), // output[6:0]
.ext_buf_rpage_nxt (ext_buf_rpage_nxt), // output
// .ext_buf_raddr (ext_buf_raddr), // output[6:0]
.ext_buf_rchn (ext_buf_rchn), // output[3:0]
.ext_buf_rrefresh(ext_buf_rrefresh), // output
......@@ -955,273 +958,289 @@ end
// Registering existing channel buffers I/Os
`ifdef def_enable_mem_chn0
mcont_common_chnbuf_reg #( .CHN_NUMBER(0)) mcont_common_chnbuf_reg0_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done0),.rpage_nxt(rpage_nxt_chn0));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done0),.page_nxt(page_nxt_chn0),.buf_run(buf_run0));
`ifdef def_read_mem_chn0
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn0),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn0),.buf_run(buf_run0),.buf_wdata_chn(buf_wdata_chn0));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn0),.buf_run(buf_wrun0),.buf_wdata_chn(buf_wdata_chn0));
`endif
`ifdef def_write_mem_chn0
wire [63:0] ext_buf_rdata0;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata0),.buf_rd_chn(buf_rd_chn0),.buf_run(buf_run0),.buf_rdata_chn(buf_rdata_chn0));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata0),.buf_rd_chn(buf_rd_chn0),.rpage_nxt(buf_rpage_nxt_chn0),.buf_rdata_chn(buf_rdata_chn0));
`endif
`endif
`ifdef def_enable_mem_chn1
mcont_common_chnbuf_reg #( .CHN_NUMBER(1)) mcont_common_chnbuf_reg1_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done1),.rpage_nxt(rpage_nxt_chn1));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done1),.page_nxt(page_nxt_chn1),.buf_run(buf_run1));
`ifdef def_read_mem_chn1
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn1),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn1),.buf_run(buf_run1),.buf_wdata_chn(buf_wdata_chn1));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn1),.buf_run(buf_wrun1),.buf_wdata_chn(buf_wdata_chn1));
`endif
`ifdef def_write_mem_chn1
wire [63:0] ext_buf_rdata1;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata1),.buf_rd_chn(buf_rd_chn1),.buf_run(buf_run1),.buf_rdata_chn(buf_rdata_chn1));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata1),.buf_rd_chn(buf_rd_chn1),.rpage_nxt(buf_rpage_nxt_chn1),.buf_rdata_chn(buf_rdata_chn1));
`endif
`endif
`ifdef def_enable_mem_chn2
mcont_common_chnbuf_reg #( .CHN_NUMBER(2)) mcont_common_chnbuf_reg2_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done2),.rpage_nxt(rpage_nxt_chn2));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done2),.page_nxt(page_nxt_chn2),.buf_run(buf_run2));
`ifdef def_read_mem_chn2
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn2),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn2),.buf_run(buf_run2),.buf_wdata_chn(buf_wdata_chn2));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn2),.buf_run(buf_wrun2),.buf_wdata_chn(buf_wdata_chn2));
`endif
`ifdef def_write_mem_chn2
wire [63:0] ext_buf_rdata2;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata2),.buf_rd_chn(buf_rd_chn2),.buf_run(buf_run2),.buf_rdata_chn(buf_rdata_chn2));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata2),.buf_rd_chn(buf_rd_chn2),.rpage_nxt(buf_rpage_nxt_chn2),.buf_rdata_chn(buf_rdata_chn2));
`endif
`endif
`ifdef def_enable_mem_chn3
mcont_common_chnbuf_reg #( .CHN_NUMBER(3)) mcont_common_chnbuf_reg3_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done3),.rpage_nxt(rpage_nxt_chn3));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done3),.page_nxt(page_nxt_chn3),.buf_run(buf_run3));
`ifdef def_read_mem_chn3
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn3),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn3),.buf_run(buf_run3),.buf_wdata_chn(buf_wdata_chn3));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn3),.buf_run(buf_wrun3),.buf_wdata_chn(buf_wdata_chn3));
`endif
`ifdef def_write_mem_chn3
wire [63:0] ext_buf_rdata3;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata3),.buf_rd_chn(buf_rd_chn3),.buf_run(buf_run3),.buf_rdata_chn(buf_rdata_chn3));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata3),.buf_rd_chn(buf_rd_chn3),.rpage_nxt(buf_rpage_nxt_chn3),.buf_rdata_chn(buf_rdata_chn3));
`endif
`endif
`ifdef def_enable_mem_chn4
mcont_common_chnbuf_reg #( .CHN_NUMBER(4)) mcont_common_chnbuf_reg4_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done4),.rpage_nxt(rpage_nxt_chn4));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done4),.page_nxt(page_nxt_chn4),.buf_run(buf_run4));
`ifdef def_read_mem_chn4
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn4),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn4),.buf_run(buf_run4),.buf_wdata_chn(buf_wdata_chn4));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn4),.buf_run(buf_wrun4),.buf_wdata_chn(buf_wdata_chn4));
`endif
`ifdef def_write_mem_chn4
wire [63:0] ext_buf_rdata4;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata4),.buf_rd_chn(buf_rd_chn4),.buf_run(buf_run4),.buf_rdata_chn(buf_rdata_chn4));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata4),.buf_rd_chn(buf_rd_chn4),.rpage_nxt(buf_rpage_nxt_chn4),.buf_rdata_chn(buf_rdata_chn4));
`endif
`endif
`ifdef def_enable_mem_chn5
mcont_common_chnbuf_reg #( .CHN_NUMBER(5)) mcont_common_chnbuf_reg5_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done5),.rpage_nxt(rpage_nxt_chn5));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done5),.page_nxt(page_nxt_chn5),.buf_run(buf_run5));
`ifdef def_read_mem_chn5
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn5),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn5),.buf_run(buf_run5),.buf_wdata_chn(buf_wdata_chn5));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn5),.buf_run(buf_wrun5),.buf_wdata_chn(buf_wdata_chn5));
`endif
`ifdef def_write_mem_chn5
wire [63:0] ext_buf_rdata5;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata5),.buf_rd_chn(buf_rd_chn5),.buf_run(buf_run5),.buf_rdata_chn(buf_rdata_chn5));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata5),.buf_rd_chn(buf_rd_chn5),.rpage_nxt(buf_rpage_nxt_chn5),.buf_rdata_chn(buf_rdata_chn5));
`endif
`endif
`ifdef def_enable_mem_chn6
mcont_common_chnbuf_reg #( .CHN_NUMBER(6)) mcont_common_chnbuf_reg6_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done6),.rpage_nxt(rpage_nxt_chn6));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done6),.page_nxt(page_nxt_chn6),.buf_run(buf_run6));
`ifdef def_read_mem_chn6
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn6),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn6),.buf_run(buf_run6),.buf_wdata_chn(buf_wdata_chn6));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn6),.buf_run(buf_wrun6),.buf_wdata_chn(buf_wdata_chn6));
`endif
`ifdef def_write_mem_chn6
wire [63:0] ext_buf_rdata6;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata6),.buf_rd_chn(buf_rd_chn6),.buf_run(buf_run6),.buf_rdata_chn(buf_rdata_chn6));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata6),.buf_rd_chn(buf_rd_chn6),.rpage_nxt(buf_rpage_nxt_chn6),.buf_rdata_chn(buf_rdata_chn6));
`endif
`endif
`ifdef def_enable_mem_chn7
mcont_common_chnbuf_reg #( .CHN_NUMBER(7)) mcont_common_chnbuf_reg7_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done7),.rpage_nxt(rpage_nxt_chn7));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done7),.page_nxt(page_nxt_chn7),.buf_run(buf_run7));
`ifdef def_read_mem_chn7
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn7),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn7),.buf_run(buf_run7),.buf_wdata_chn(buf_wdata_chn7));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn7),.buf_run(buf_wrun7),.buf_wdata_chn(buf_wdata_chn7));
`endif
`ifdef def_write_mem_chn7
wire [63:0] ext_buf_rdata7;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata7),.buf_rd_chn(buf_rd_chn7),.buf_run(buf_run7),.buf_rdata_chn(buf_rdata_chn7));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata7),.buf_rd_chn(buf_rd_chn7),.rpage_nxt(buf_rpage_nxt_chn7),.buf_rdata_chn(buf_rdata_chn7));
`endif
`endif
`ifdef def_enable_mem_chn8
mcont_common_chnbuf_reg #( .CHN_NUMBER(8)) mcont_common_chnbuf_reg8_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done8),.rpage_nxt(rpage_nxt_chn8));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done8),.page_nxt(page_nxt_chn8),.buf_run(buf_run8));
`ifdef def_read_mem_chn8
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn8),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn8),.buf_run(buf_run8),.buf_wdata_chn(buf_wdata_chn8));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn8),.buf_run(buf_wrun8),.buf_wdata_chn(buf_wdata_chn8));
`endif
`ifdef def_write_mem_chn8
wire [63:0] ext_buf_rdata8;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata8),.buf_rd_chn(buf_rd_chn8),.buf_run(buf_run8),.buf_rdata_chn(buf_rdata_chn8));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata8),.buf_rd_chn(buf_rd_chn8),.rpage_nxt(buf_rpage_nxt_chn8),.buf_rdata_chn(buf_rdata_chn8));
`endif
`endif
`ifdef def_enable_mem_chn9
mcont_common_chnbuf_reg #( .CHN_NUMBER(9)) mcont_common_chnbuf_reg9_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done9),.rpage_nxt(rpage_nxt_chn9));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done9),.page_nxt(page_nxt_chn9),.buf_run(buf_run9));
`ifdef def_read_mem_chn9
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn9),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn9),.buf_run(buf_run9),.buf_wdata_chn(buf_wdata_chn9));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn9),.buf_run(buf_wrun9),.buf_wdata_chn(buf_wdata_chn9));
`endif
`ifdef def_write_mem_chn9
wire [63:0] ext_buf_rdata9;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata9),.buf_rd_chn(buf_rd_chn9),.buf_run(buf_run9),.buf_rdata_chn(buf_rdata_chn9));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata9),.buf_rd_chn(buf_rd_chn9),.rpage_nxt(buf_rpage_nxt_chn9),.buf_rdata_chn(buf_rdata_chn9));
`endif
`endif
`ifdef def_enable_mem_chn10
mcont_common_chnbuf_reg #( .CHN_NUMBER(10)) mcont_common_chnbuf_reg10_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done10),.rpage_nxt(rpage_nxt_chn10));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done10),.page_nxt(page_nxt_chn10),.buf_run(buf_run10));
`ifdef def_read_mem_chn10
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn10),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn10),.buf_run(buf_run10),.buf_wdata_chn(buf_wdata_chn10));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn10),.buf_run(buf_wrun10),.buf_wdata_chn(buf_wdata_chn10));
`endif
`ifdef def_write_mem_chn10
wire [63:0] ext_buf_rdata10;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata10),.buf_rd_chn(buf_rd_chn10),.buf_run(buf_run10),.buf_rdata_chn(buf_rdata_chn10));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata10),.buf_rd_chn(buf_rd_chn10),.rpage_nxt(buf_rpage_nxt_chn10),.buf_rdata_chn(buf_rdata_chn10));
`endif
`endif
`ifdef def_enable_mem_chn11
mcont_common_chnbuf_reg #( .CHN_NUMBER(11)) mcont_common_chnbuf_reg11_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done11),.rpage_nxt(rpage_nxt_chn11));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done11),.page_nxt(page_nxt_chn11),.buf_run(buf_run11));
`ifdef def_read_mem_chn11
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn11),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn11),.buf_run(buf_run11),.buf_wdata_chn(buf_wdata_chn11));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn11),.buf_run(buf_wrun11),.buf_wdata_chn(buf_wdata_chn11));
`endif
`ifdef def_write_mem_chn11
wire [63:0] ext_buf_rdata11;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 11),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg11_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata11),.buf_rd_chn(buf_rd_chn11),.buf_run(buf_run11),.buf_rdata_chn(buf_rdata_chn11));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata11),.buf_rd_chn(buf_rd_chn11),.rpage_nxt(buf_rpage_nxt_chn11),.buf_rdata_chn(buf_rdata_chn11));
`endif
`endif
`ifdef def_enable_mem_chn12
mcont_common_chnbuf_reg #( .CHN_NUMBER(12)) mcont_common_chnbuf_reg12_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done12),.rpage_nxt(rpage_nxt_chn12));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done12),.page_nxt(page_nxt_chn12),.buf_run(buf_run12));
`ifdef def_read_mem_chn12
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn12),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn12),.buf_run(buf_run12),.buf_wdata_chn(buf_wdata_chn12));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn12),.buf_run(buf_wrun12),.buf_wdata_chn(buf_wdata_chn12));
`endif
`ifdef def_write_mem_chn12
wire [63:0] ext_buf_rdata12;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 12),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg12_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata12),.buf_rd_chn(buf_rd_chn12),.buf_run(buf_run12),.buf_rdata_chn(buf_rdata_chn12));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata12),.buf_rd_chn(buf_rd_chn12),.rpage_nxt(buf_rpage_nxt_chn12),.buf_rdata_chn(buf_rdata_chn12));
`endif
`endif
`ifdef def_enable_mem_chn13
mcont_common_chnbuf_reg #( .CHN_NUMBER(13)) mcont_common_chnbuf_reg13_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done13),.rpage_nxt(rpage_nxt_chn13));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done13),.page_nxt(page_nxt_chn13),.buf_run(buf_run13));
`ifdef def_read_mem_chn13
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn13),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn13),.buf_run(buf_run13),.buf_wdata_chn(buf_wdata_chn13));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn13),.buf_run(buf_wrun13),.buf_wdata_chn(buf_wdata_chn13));
`endif
`ifdef def_write_mem_chn13
wire [63:0] ext_buf_rdata13;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 13),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg13_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata13),.buf_rd_chn(buf_rd_chn13),.buf_run(buf_run13),.buf_rdata_chn(buf_rdata_chn13));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata13),.buf_rd_chn(buf_rd_chn13),.rpage_nxt(buf_rpage_nxt_chn13),.buf_rdata_chn(buf_rdata_chn13));
`endif
`endif
`ifdef def_enable_mem_chn14
mcont_common_chnbuf_reg #( .CHN_NUMBER(14)) mcont_common_chnbuf_reg14_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done14),.rpage_nxt(rpage_nxt_chn14));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done14),.page_nxt(page_nxt_chn14),.buf_run(buf_run14));
`ifdef def_read_mem_chn14
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn14),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn14),.buf_run(buf_run14),.buf_wdata_chn(buf_wdata_chn14));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn14),.buf_run(buf_wrun14),.buf_wdata_chn(buf_wdata_chn14));
`endif
`ifdef def_write_mem_chn14
wire [63:0] ext_buf_rdata14;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 14),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg14_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata14),.buf_rd_chn(buf_rd_chn14),.buf_run(buf_run14),.buf_rdata_chn(buf_rdata_chn14));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata14),.buf_rd_chn(buf_rd_chn14),.rpage_nxt(buf_rpage_nxt_chn14),.buf_rdata_chn(buf_rdata_chn14));
`endif
`endif
`ifdef def_enable_mem_chn15
mcont_common_chnbuf_reg #( .CHN_NUMBER(15)) mcont_common_chnbuf_reg15_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done15),.rpage_nxt(rpage_nxt_chn15));
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_page_nxt(ext_buf_page_nxt),.seq_done(sequencer_run_done), .ext_buf_run(ext_buf_rrun),
.buf_done(seq_done15),.page_nxt(page_nxt_chn15),.buf_run(buf_run15));
`ifdef def_read_mem_chn15
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn15),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn15),.buf_run(buf_run15),.buf_wdata_chn(buf_wdata_chn15));
`else
.buf_wpage_nxt_chn(buf_wpage_nxt_chn15),.buf_run(buf_wrun15),.buf_wdata_chn(buf_wdata_chn15));
`endif
`ifdef def_write_mem_chn15
wire [63:0] ext_buf_rdata15;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 15),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg15_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata15),.buf_rd_chn(buf_rd_chn15),.buf_run(buf_run15),.buf_rdata_chn(buf_rdata_chn15));
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),
.ext_buf_rdata(ext_buf_rdata15),.buf_rd_chn(buf_rd_chn15),.rpage_nxt(buf_rpage_nxt_chn15),.buf_rdata_chn(buf_rdata_chn15));
`endif
`endif
......@@ -1241,82 +1260,82 @@ localparam [3:0] EXT_READ_LATENCY=CHNBUF_READ_LATENCY+2; // +1;
always @ (posedge mclk) if (ext_buf_rd_late) begin
case (ext_buf_rchn_late)
`ifdef def_enable_mem_chn0
`ifndef def_read_mem_chn0
`ifdef def_write_mem_chn0
4'h0:ext_buf_rdata <= ext_buf_rdata0;
`endif
`endif
`ifdef def_enable_mem_chn1
`ifndef def_read_mem_chn1
`ifdef def_write_mem_chn1
4'h1:ext_buf_rdata <= ext_buf_rdata1;
`endif
`endif
`ifdef def_enable_mem_chn2
`ifndef def_read_mem_chn2
`ifdef def_write_mem_chn2
4'h2:ext_buf_rdata <= ext_buf_rdata2;
`endif
`endif
`ifdef def_enable_mem_chn3
`ifndef def_read_mem_chn3
`ifdef def_write_mem_chn3
4'h3:ext_buf_rdata <= ext_buf_rdata3;
`endif
`endif
`ifdef def_enable_mem_chn4
`ifndef def_read_mem_chn4
`ifdef def_write_mem_chn4
4'h4:ext_buf_rdata <= ext_buf_rdata4;
`endif
`endif
`ifdef def_enable_mem_chn5
`ifndef def_read_mem_chn5
`ifdef def_write_mem_chn5
4'h5:ext_buf_rdata <= ext_buf_rdata5;
`endif
`endif
`ifdef def_enable_mem_chn6
`ifndef def_read_mem_chn6
`ifdef def_write_mem_chn6
4'h6:ext_buf_rdata <= ext_buf_rdata6;
`endif
`endif
`ifdef def_enable_mem_chn7
`ifndef def_read_mem_chn7
`ifdef def_write_mem_chn7
4'h7:ext_buf_rdata <= ext_buf_rdata7;
`endif
`endif
`ifdef def_enable_mem_chn8
`ifndef def_read_mem_chn8
`ifdef def_write_mem_chn8
4'h8:ext_buf_rdata <= ext_buf_rdata8;
`endif
`endif
`ifdef def_enable_mem_chn9
`ifndef def_read_mem_chn9
`ifdef def_write_mem_chn9
4'h9:ext_buf_rdata <= ext_buf_rdata9;
`endif
`endif
`ifdef def_enable_mem_chn10
`ifndef def_read_mem_chn10
`ifdef def_write_mem_chn10
4'h10:ext_buf_rdata <= ext_buf_rdata10;
`endif
`endif
`ifdef def_enable_mem_chn11
`ifndef def_read_mem_chn11
`ifdef def_write_mem_chn11
4'h11:ext_buf_rdata <= ext_buf_rdata11;
`endif
`endif
`ifdef def_enable_mem_chn12
`ifndef def_read_mem_chn12
`ifdef def_write_mem_chn12
4'h12:ext_buf_rdata <= ext_buf_rdata12;
`endif
`endif
`ifdef def_enable_mem_chn13
`ifndef def_read_mem_chn13
`ifdef def_write_mem_chn13
4'h13:ext_buf_rdata <= ext_buf_rdata13;
`endif
`endif
`ifdef def_enable_mem_chn14
`ifndef def_read_mem_chn14
`ifdef def_write_mem_chn14
4'h14:ext_buf_rdata <= ext_buf_rdata14;
`endif
`endif
`ifdef def_enable_mem_chn15
`ifndef def_read_mem_chn15
`ifdef def_write_mem_chn15
4'h15:ext_buf_rdata <= ext_buf_rdata15;
`endif
`endif
......@@ -1379,63 +1398,6 @@ assign want_rq[15:0]= {want_rq15,want_rq14,want_rq13,want_rq12,want_rq11,want_
assign need_rq[15:0]= {need_rq15,need_rq14,need_rq13,need_rq12,need_rq11,need_rq10,need_rq9,need_rq8,
need_rq7,need_rq6,need_rq5,need_rq4,need_rq3,need_rq2,need_rq1,need_rq0};
always @ (posedge rst or posedge mclk) begin
if (rst) begin seq_data <= 0; seq_wr <=0; seq_set <=0; end
else begin
case (cmd_wr_chn)
`ifdef def_enable_mem_chn0
4'h0:begin seq_data <= seq_data0; seq_wr <= seq_wr0; seq_set <= seq_set0; end
`endif
`ifdef def_enable_mem_chn1
4'd1:begin seq_data <= seq_data1; seq_wr <= seq_wr1; seq_set <= seq_set1; end
`endif
`ifdef def_enable_mem_chn2
4'd2:begin seq_data <= seq_data2; seq_wr <= seq_wr2; seq_set <= seq_set2; end
`endif
`ifdef def_enable_mem_chn3
4'd3:begin seq_data <= seq_data3; seq_wr <= seq_wr3; seq_set <= seq_set3; end
`endif
`ifdef def_enable_mem_chn4
4'd4:begin seq_data <= seq_data4; seq_wr <= seq_wr4; seq_set <= seq_set4; end
`endif
`ifdef def_enable_mem_chn5
4'd5:begin seq_data <= seq_data5; seq_wr <= seq_wr5; seq_set <= seq_set5; end
`endif
`ifdef def_enable_mem_chn6
4'd6:begin seq_data <= seq_data6; seq_wr <= seq_wr6; seq_set <= seq_set6; end
`endif
`ifdef def_enable_mem_chn7
4'd7:begin seq_data <= seq_data7; seq_wr <= seq_wr7; seq_set <= seq_set7; end
`endif
`ifdef def_enable_mem_chn8
4'd8:begin seq_data <= seq_data8; seq_wr <= seq_wr8; seq_set <= seq_set8; end
`endif
`ifdef def_enable_mem_chn9
4'd9:begin seq_data <= seq_data9; seq_wr <= seq_wr9; seq_set <= seq_set9; end
`endif
`ifdef def_enable_mem_chn10
4'd10:begin seq_data <= seq_data10; seq_wr <= seq_wr10; seq_set <= seq_set10; end
`endif
`ifdef def_enable_mem_chn11
4'd11:begin seq_data <= seq_data11; seq_wr <= seq_wr11; seq_set <= seq_set11; end
`endif
`ifdef def_enable_mem_chn12
4'd12:begin seq_data <= seq_data12; seq_wr <= seq_wr12; seq_set <= seq_set12; end
`endif
`ifdef def_enable_mem_chn13
4'd13:begin seq_data <= seq_data13; seq_wr <= seq_wr13; seq_set <= seq_set13; end
`endif
`ifdef def_enable_mem_chn14
4'd14:begin seq_data <= seq_data14; seq_wr <= seq_wr14; seq_set <= seq_set14; end
`endif
`ifdef def_enable_mem_chn15
4'd15:begin seq_data <= seq_data15; seq_wr <= seq_wr15; seq_set <= seq_set15; end
`endif
endcase
end
end
`ifdef def_enable_mem_chn0
always @ (posedge mclk) channel_pgm_en0 <= grant && (grant_chn == 0);
......
memctrl/phy/mcontr_sequencer.v
View file @ ad0351ef
......@@ -143,6 +143,7 @@ module mcontr_sequencer #(
// Interface to write-to-memory buffers (up to 16)
// There will be =1 cycle external latency in address/re and 1 cycle latency in read data (should match sequence programs)
// Address data is sync to posedge mclk
output ext_buf_page_nxt, // Generated for both reads and writes, @posedge mclk
output ext_buf_rd,
output ext_buf_rpage_nxt, // increment external buffer read address to next page start
// output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
......@@ -217,7 +218,8 @@ module mcontr_sequencer #(
wire [31:0] phy_cmd_word; // selected output from either cmd0 buffer or cmd1 buffer
wire [31:0] phy_cmd0_word; // cmd0 buffer output
wire [31:0] phy_cmd1_word; // cmd1 buffer output
wire buf_raddr_reset;
reg buf_raddr_reset;
reg buf_addr_reset; // generated regardless of read/write
// reg [ 6:0] buf_raddr;
reg buf_waddr_reset_negedge;
// reg [ 6:0] buf_waddr_negedge;
......@@ -260,6 +262,7 @@ module mcontr_sequencer #(
reg run_w_d_negedge;
reg run_seq_d;
reg mem_read_mode; // last was buf_wr, not buf_rd
wire [7:0] tmp_debug_a;
assign tmp_debug[11:0] =
......@@ -284,9 +287,10 @@ module mcontr_sequencer #(
// External buffers buffer related signals
assign buf_raddr_reset= buf_rst; // run_seq_d;
// assign buf_raddr_reset= buf_rst & ~mem_read_mode; // run_seq_d;
assign ext_buf_rd= buf_rd;
assign ext_buf_rpage_nxt=buf_raddr_reset;
assign ext_buf_page_nxt= buf_addr_reset;
// assign ext_buf_raddr= buf_raddr;
assign ext_buf_rchn= run_chn_d;
assign ext_buf_rrefresh= run_refresh_d;
......@@ -468,6 +472,18 @@ module mcontr_sequencer #(
if (rst) run_seq_d <= 0;
else run_seq_d <= run_seq;
if (rst) buf_raddr_reset <= 0;
else buf_raddr_reset<= buf_rst & ~mem_read_mode;
if (rst) buf_addr_reset <= 0;
else buf_addr_reset<= buf_rst;
end
always @ (posedge mclk) begin
if (buf_wr) mem_read_mode <= 1; // last was buf_wr, not buf_rd
else if (buf_rd) mem_read_mode <= 0;
end
// re-register buffer write address to match DDR3 data
......@@ -613,7 +629,7 @@ module mcontr_sequencer #(
.clk(mclk), // input
.rst(1'b0), // input
.dly(wbuf_delay[3:0]), // input[3:0]
.din({buf_rst,buf_wr_ndly}), // input
.din({mem_read_mode & buf_rst,buf_wr_ndly}), // input
.dout({buf_rst_d, buf_wr}) // output reg
);
assign wbuf_delay_m1=wbuf_delay-1;
......
util_modules/mcont_common_chnbuf_reg.v
View file @ ad0351ef
......@@ -27,10 +27,12 @@ module mcont_common_chnbuf_reg #(
input clk,
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead of ext_buf_rd!, maybe not needed - will be generated externally
input ext_buf_rrefresh,
input ext_buf_rpage_nxt,
input ext_buf_page_nxt,
input seq_done, // sequence done
input ext_buf_run,
output reg buf_done, // sequence done for the specified channel
output reg rpage_nxt
output reg page_nxt,
output reg buf_run
);
reg buf_chn_sel;
always @ (posedge rst or posedge clk) begin
......@@ -39,8 +41,11 @@ module mcont_common_chnbuf_reg #(
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
if (rst) buf_run <= 0;
else buf_run <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh && ext_buf_run;
end
always @ (posedge clk) rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
always @ (posedge clk) page_nxt <= ext_buf_page_nxt && (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
endmodule
util_modules/mcont_from_chnbuf_reg.v
View file @ ad0351ef
......@@ -29,10 +29,12 @@ module mcont_from_chnbuf_reg #(
input ext_buf_rd,
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input ext_buf_rrefresh,
input ext_buf_rrun,
// input ext_buf_rrun,
input ext_buf_rpage_nxt,
output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
output reg buf_rd_chn,
output reg buf_run,
// output reg buf_run,
output reg rpage_nxt,
input [63:0] buf_rdata_chn
);
reg buf_chn_sel;
......@@ -44,8 +46,8 @@ module mcont_from_chnbuf_reg #(
if (rst) buf_rd_chn <= 0;
else buf_rd_chn <= buf_chn_sel && ext_buf_rd;
if (rst) buf_run <= 0;
else buf_run <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh && ext_buf_rrun;
// if (rst) buf_run <= 0;
// else buf_run <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh && ext_buf_rrun;
if (rst) latency_reg<= 0;
// else latency_reg <= buf_rd_chn | (latency_reg << 1);
......@@ -57,5 +59,7 @@ module mcont_from_chnbuf_reg #(
// always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
always @ (posedge clk) rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh;
endmodule
x393.v
View file @ ad0351ef
......@@ -28,11 +28,20 @@ module x393 #(
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
// parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 1 (PS sequence, memory write)
// parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
// parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
// parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
// parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h0800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_WR_ADDR = 'h0c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
......@@ -186,7 +195,7 @@ module x393 #(
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
......@@ -199,17 +208,18 @@ module x393 #(
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h6,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -222,7 +232,8 @@ module x393 #(
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WHS= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......@@ -233,18 +244,18 @@ module x393 #(
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f // status/readback register for channel 4
)(
// DDR3 interface
output SDRST, // DDR3 reset (active low)
......@@ -459,6 +470,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//mcntrl393_test01
wire frame_start_chn1; // input
wire next_page_chn1; // input
wire page_ready_chn1; // output
wire frame_done_chn1; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1; // output[15:0]
wire suspend_chn1; // input
wire frame_start_chn2; // input
wire next_page_chn2; // input
wire page_ready_chn2; // output
......@@ -477,12 +494,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
wire frame_done_chn4; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4; // output[15:0]
wire suspend_chn4; // input
wire frame_start_chn5; // input
wire next_page_chn5; // input
wire page_ready_chn5; // output
wire frame_done_chn5; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5; // output[15:0]
wire suspend_chn5; // input
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
......@@ -505,18 +516,18 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TEST01_ADDR (MCNTRL_TEST01_ADDR),
.MCNTRL_TEST01_MASK (MCNTRL_TEST01_MASK),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_TEST01_CHN1_MODE (MCNTRL_TEST01_CHN1_MODE),
.MCNTRL_TEST01_CHN1_STATUS_CNTRL (MCNTRL_TEST01_CHN1_STATUS_CNTRL),
.MCNTRL_TEST01_CHN2_MODE (MCNTRL_TEST01_CHN2_MODE),
.MCNTRL_TEST01_CHN2_STATUS_CNTRL (MCNTRL_TEST01_CHN2_STATUS_CNTRL),
.MCNTRL_TEST01_CHN3_MODE (MCNTRL_TEST01_CHN3_MODE),
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_CHN5_MODE (MCNTRL_TEST01_CHN5_MODE),
.MCNTRL_TEST01_CHN5_STATUS_CNTRL (MCNTRL_TEST01_CHN5_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN5_ADDR (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR)
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) mcntrl393_test01_i (
.rst(axi_rst), // input
.mclk (mclk), // input
......@@ -525,6 +536,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.status_ad (status_test01_ad), // output[7:0]
.status_rq (status_test01_rq), // output
.status_start (status_test01_start), // input
.frame_start_chn1 (frame_start_chn1), // output
.next_page_chn1 (next_page_chn1), // output
.page_ready_chn1 (page_ready_chn1), // input
.frame_done_chn1 (frame_done_chn1), // input
.line_unfinished_chn1 (line_unfinished_chn1), // input[15:0]
.suspend_chn1 (suspend_chn1), // output
.frame_start_chn2 (frame_start_chn2), // output
.next_page_chn2 (next_page_chn2), // output
.page_ready_chn2 (page_ready_chn2), // input
......@@ -542,13 +559,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.page_ready_chn4 (page_ready_chn4), // input
.frame_done_chn4 (frame_done_chn4), // input
.line_unfinished_chn4 (line_unfinished_chn4), // input[15:0]
.suspend_chn4 (suspend_chn4), // output
.frame_start_chn5 (frame_start_chn5), // output
.next_page_chn5 (next_page_chn5), // output
.page_ready_chn5 (page_ready_chn5), // input
.frame_done_chn5 (frame_done_chn5), // input
.line_unfinished_chn5 (line_unfinished_chn5), // input[15:0]
.suspend_chn5 (suspend_chn5) // output
.suspend_chn4 (suspend_chn4) // output
);
// Interface to channels to read/write memory (including 4 page BRAM buffers)
......@@ -642,11 +653,16 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCONTR_RD_MASK (MCONTR_RD_MASK),
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF0_WR_ADDR (MCONTR_BUF0_WR_ADDR),
.MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR),
.MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF2_WR_ADDR (MCONTR_BUF2_WR_ADDR),
.MCONTR_BUF3_RD_ADDR (MCONTR_BUF3_RD_ADDR),
.MCONTR_BUF3_WR_ADDR (MCONTR_BUF3_WR_ADDR),
.MCONTR_BUF4_RD_ADDR (MCONTR_BUF4_RD_ADDR),
.MCONTR_BUF5_WR_ADDR (MCONTR_BUF5_WR_ADDR),
.MCONTR_BUF4_WR_ADDR (MCONTR_BUF4_WR_ADDR),
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
......@@ -726,7 +742,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_SCANLINE_CHN2_ADDR (MCNTRL_SCANLINE_CHN2_ADDR),
.MCNTRL_SCANLINE_CHN1_ADDR (MCNTRL_SCANLINE_CHN1_ADDR),
.MCNTRL_SCANLINE_CHN3_ADDR (MCNTRL_SCANLINE_CHN3_ADDR),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
......@@ -736,13 +752,14 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN2_ADDR (MCNTRL_TILED_CHN2_ADDR),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_CHN5_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -752,6 +769,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_CHN2_ADDR (MCNTRL_TILED_STATUS_REG_CHN2_ADDR),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
......@@ -781,6 +799,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.axird_rdata (mcntrl_axird_rdata), // output[31:0]
.axird_selected (mcntrl_axird_selected), // output
//TODO:
.frame_start_chn1 (frame_start_chn1), // input
.next_page_chn1 (next_page_chn1), // input
.page_ready_chn1 (page_ready_chn1), // output
.frame_done_chn1 (frame_done_chn1), // output
.line_unfinished_chn1 (line_unfinished_chn1), // output[15:0]
.suspend_chn1 (suspend_chn1), // input
.frame_start_chn2 (frame_start_chn2), // input
.next_page_chn2 (next_page_chn2), // input
.page_ready_chn2 (page_ready_chn2), // output
......@@ -799,12 +823,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.frame_done_chn4 (frame_done_chn4), // output
.line_unfinished_chn4 (line_unfinished_chn4), // output[15:0]
.suspend_chn4 (suspend_chn4), // input
.frame_start_chn5 (frame_start_chn5), // input
.next_page_chn5 (next_page_chn5), // input
.page_ready_chn5 (page_ready_chn5), // output
.frame_done_chn5 (frame_done_chn5), // output
.line_unfinished_chn5 (line_unfinished_chn5), // output[15:0]
.suspend_chn5 (suspend_chn5), // input
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
......
x393_testbench01.sav
View file @ ad0351ef
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Fri Feb 20 06:23:37 2015
[*] Sat Feb 21 04:19:14 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150219230857315.lxt"
[dumpfile_mtime] "Fri Feb 20 06:18:19 2015"
[dumpfile_size] 511941344
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150220211129513.lxt"
[dumpfile_mtime] "Sat Feb 21 04:16:31 2015"
[dumpfile_size] 216491754
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 47202600
[timestart] 34710000
[size] 1823 1180
[pos] 2056 0
*-16.698502 48006875 55877500 55843010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-22.698502 66264375 55877500 55843010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
......@@ -98,6 +98,20 @@ x393_testbench01.target_phase[7:0]
x393_testbench01.read_and_wait_status.address[7:0]
@1000200
-top_extra
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_page_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rpage_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_wpage_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run0[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run2[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run3[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_wr_chn4[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run4[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_rd_chn5[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_run5[0]
@200
-
@c00200
-read_block_buf_chn
@22
......@@ -1319,8 +1333,6 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
@1401200
-mcntrl393_test01
@22
x393_testbench01.ii[31:0]
@200
-
@c00200
......@@ -1529,7 +1541,7 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.full_cmd[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_write[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enable_autopre[0]
@23
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rom_r[12:0]
@200
-
......@@ -1657,7 +1669,6 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.recalc_r[8:0]
-group_end
@28
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn4_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.rpage_nxt_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.frame_busy_chn4[0]
@22
......@@ -2465,7 +2476,6 @@ x393_testbench01.x393_i.mcntrl393_i.axiwr_wen[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata3[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata1[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg3_i.buf_rd_chn[0]
@800028
......@@ -2535,8 +2545,6 @@ x393_testbench01.write_block_incremtal.start_word_address[29:0]
-write_block_scanline_chn
@200
-
@22
x393_testbench01.ii[31:0]
@28
x393_testbench01.wait_status_condition.invert_match[0]
@22
......@@ -2893,8 +2901,9 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.val
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.values[255:0]
@1401200
-index_max16
@c00200
@800200
-PS_PIO
@c00200
-PS_PIO_STATUS
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_generate_i.ad[7:0]
......@@ -2974,38 +2983,38 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0]
-PS_PIO_CHN0
@200
-
@c00200
@800201
-PS_PIO_CHN1
@200
@201
-
@28
@29
x393_testbench01.schedule_ps_pio.chn[0]
x393_testbench01.schedule_ps_pio.page[1:0]
@22
@23
x393_testbench01.schedule_ps_pio.seq_addr[9:0]
@28
@29
x393_testbench01.schedule_ps_pio.urgent[0]
@22
@23
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.data_out[63:0]
@28
@29
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_clk[0]
@22
@23
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_waddr[9:0]
@28
@29
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_r[1:0]
@22
@23
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.raddr[6:0]
@28
@29
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1401200
@1000201
-PS_PIO_CHN1
@c00200
-other_modules
......@@ -3016,7 +3025,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_wrun[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_wchn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_chn[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set[0]
@800028
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set_d[1:0]
......@@ -3040,7 +3048,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.sequence_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sequencer_run_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done1[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0]
@1001200
-group_end
......@@ -3049,42 +3056,25 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.busy[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set[0]
@c00022
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0]
(2)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0]
(3)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0]
@1401200
-group_end
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rd[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rdata[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_run0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_run1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rd_chn1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rpage_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rdata_chn1[63:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wdata_chn0[63:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wdata[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wpage_nxt_chn0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wr_chn0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wpage_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_wrun[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.busy[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.channel_pgm_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn_rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_a[4:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_half_full[0]
......@@ -3101,15 +3091,25 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_set_d[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wait[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wait_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wr[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.cmd_wr_out[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.en_page_w_set[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.en_reset[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.need_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.need_rq1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out_chn1[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_neg[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out_chn0[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.need_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.nreset_page_fifo[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.nreset_page_fifo_neg[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out_r[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_out_r_negedge[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_r_set[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_w_set_early[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_w_set_early_negedge[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.page_w_set_negedge[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.pending_pages[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_addr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port0_clk[0]
......@@ -3126,41 +3126,25 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_clk[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.port1_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.rpage_nxt_chn1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.rst[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_data0[9:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_data[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_chn_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.pre_run_seq_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.sel_refresh_w[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_chn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done1[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_set0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.seq_set[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_cmd_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_en_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.short_busy[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_ad[7:0]
@800028
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
@28
(0)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
(1)x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
@1401200
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq[0]
@1000200
-PS_PIO
@c00200
-memcntrl16_0
......@@ -3168,10 +3152,6 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd_late[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_rdata_chn1[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata1[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rpage_nxt[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn[3:0]
......@@ -3179,21 +3159,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata[63:0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_chn_sel[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_rd_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_rdata_chn[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rchn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rd[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rdata[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rrefresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
@22
......
x393_testbench01.tf
View file @ ad0351ef
......@@ -27,18 +27,18 @@
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
//`define TEST_READ_PATTERN 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
//`define TEST_SCANLINE_WRITE 1
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ 1
`define TEST_READ_SHOW 1
`define TEST_TILED_WRITE 1
//`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_TILED_READ 1
//`define TEST_TILED_READ 1
module x393_testbench01 #(
......@@ -193,6 +193,7 @@ module x393_testbench01 #(
wire bready;
integer NUM_WORDS_READ;
integer NUM_WORDS_EXPECTED;
reg [15:0] ENABLED_CHANNELS = 0; // currently enabled memory channels
// integer SCANLINE_CUR_X;
// integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
......@@ -322,285 +323,47 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
enable_refresh(1);
axi_set_dqs_odelay('h78); //??? dafaults - wrong?
`ifdef TEST_WRITE_LEVELLING
// Set special values for DQS idelay for write leveling
wait_ps_pio_done(DEFAULT_STATUS_MODE); // not no interrupt running cycle - delays are changed immediately
axi_set_dqs_idelay_wlv;
// Set write buffer (from DDR3) WE signal delay for write leveling mode
axi_set_wbuf_delay(WBUF_DLY_WLV);
axi_set_dqs_odelay('h80); // 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
// @ (negedge rstb);
axi_set_dqs_odelay(DLY_DQS_ODELAY);
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
// @ (negedge rstb);
axi_set_dqs_idelay_nominal;
// axi_set_dqs_odelay_nominal;
axi_set_dqs_odelay('h78);
axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY
`ifdef TEST_WRITE_LEVELLING
test_write_levelling;
`endif
`ifdef TEST_READ_PATTERN
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
test_read_pattern;
`endif
`ifdef TEST_WRITE_BLOCK
// write_block_buf_chn; // fill block memory - already set in set_up task
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
test_write_block;
`endif
`ifdef TEST_READ_BLOCK
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
test_read_block;
`endif
`ifdef TEST_SCANLINE_WRITE
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(3,0); // lowest priority channel 3
enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
// VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
write_block_scanline_chn(
3,
(ii & 3),
SCANLINE_XFER_SIZE,
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii< (WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW) ;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// write_block_scanline_chn(3, (ii & 3), WINDOW_WIDTH, WINDOW_X0,WINDOW_Y0+ii);
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
write_block_scanline_chn(
3,
(ii & 3),
SCANLINE_XFER_SIZE,
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);
end
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
end
`ifdef TEST_SCANLINE_WRITE_WAIT
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0); // equal to
`endif
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1); // input wait_done;
`endif
`ifdef TEST_SCANLINE_READ
// program to the
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_MODE, {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(2,0); // lowest priority channel 2
enable_memcntrl_channels(16'h000f); // channels 0,1,2,3 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE, TEST01_START_FRAME);
for (ii=0;ii<(WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW);ii = ii+1) begin
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii) << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// read block (if needed), for now just sikip
`ifdef TEST_READ_SHOW
read_block_buf_chn (
2,
(ii & 3),
SCANLINE_XFER_SIZE <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
`endif
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE, TEST01_NEXT_PAGE);
end
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
1); // input show_data;
`endif
`ifdef TEST_TILED_WRITE
// program to the
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_MODE, {27'b0,TILED_KEEP_OPEN,TILED_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(5,0); // lowest priority channel 5
enable_memcntrl_channels(16'h002f); // channels 0,1,2,3 and 5 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_MODE, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
5, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
5, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
end
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_MODE, TEST01_NEXT_PAGE);
end
`ifdef TEST_TILED_WRITE_WAIT
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0); // equal to
`endif
test_tiled_write (
2, // [3:0] channel;
0, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1); // wait_done;
`endif
`ifdef TEST_TILED_READ
// program to the
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_MODE, {27'b0,TILED_KEEP_OPEN,TILED_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(4,0); // lowest priority channel 2
enable_memcntrl_channels(16'h003f); // channels 0,1,2,3,4 and 5 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE, TEST01_START_FRAME);
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
ii << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// read block (if needed), for now just sikip
`ifdef TEST_READ_SHOW
read_block_buf_chn (
4, // channel
(ii & 3), // page
TILE_SIZE << 2, // length in 32-bit words
1 ); // chn=4, page=?, number of 32-bit words=?, wait_done
`endif
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE, TEST01_NEXT_PAGE);
end
test_tiled_read (
2, // [3:0] channel;
0, // byte32;
TILED_KEEP_OPEN, // keep_open;
TILED_EXTRA_PAGES, // extra_pages;
1); // show_data;
`endif
#20000;
......@@ -673,11 +436,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCONTR_RD_MASK (MCONTR_RD_MASK),
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF0_WR_ADDR (MCONTR_BUF0_WR_ADDR),
.MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR),
.MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF2_WR_ADDR (MCONTR_BUF2_WR_ADDR),
.MCONTR_BUF3_RD_ADDR (MCONTR_BUF3_RD_ADDR),
.MCONTR_BUF3_WR_ADDR (MCONTR_BUF3_WR_ADDR),
.MCONTR_BUF4_RD_ADDR (MCONTR_BUF4_RD_ADDR),
.MCONTR_BUF5_WR_ADDR (MCONTR_BUF5_WR_ADDR),
.MCONTR_BUF4_WR_ADDR (MCONTR_BUF4_WR_ADDR),
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
......@@ -780,7 +547,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_SCANLINE_CHN2_ADDR (MCNTRL_SCANLINE_CHN2_ADDR),
.MCNTRL_SCANLINE_CHN1_ADDR (MCNTRL_SCANLINE_CHN1_ADDR),
.MCNTRL_SCANLINE_CHN3_ADDR (MCNTRL_SCANLINE_CHN3_ADDR),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
......@@ -790,13 +557,14 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),
.MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN2_ADDR (MCNTRL_TILED_CHN2_ADDR),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_CHN5_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -805,25 +573,26 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_CHN2_ADDR (MCNTRL_TILED_STATUS_REG_CHN2_ADDR),
.MCNTRL_TILED_STATUS_REG_CHN4_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS (MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.MCNTRL_TEST01_ADDR (MCNTRL_TEST01_ADDR),
.MCNTRL_TEST01_MASK (MCNTRL_TEST01_MASK),
.MCNTRL_TEST01_CHN1_MODE (MCNTRL_TEST01_CHN1_MODE),
.MCNTRL_TEST01_CHN1_STATUS_CNTRL (MCNTRL_TEST01_CHN1_STATUS_CNTRL),
.MCNTRL_TEST01_CHN2_MODE (MCNTRL_TEST01_CHN2_MODE),
.MCNTRL_TEST01_CHN2_STATUS_CNTRL (MCNTRL_TEST01_CHN2_STATUS_CNTRL),
.MCNTRL_TEST01_CHN3_MODE (MCNTRL_TEST01_CHN3_MODE),
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_CHN5_MODE (MCNTRL_TEST01_CHN5_MODE),
.MCNTRL_TEST01_CHN5_STATUS_CNTRL (MCNTRL_TEST01_CHN5_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN1_ADDR (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN5_ADDR (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR)
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) x393_i (
.SDRST (SDRST), // DDR3 reset (active low)
.SDCLK (SDCLK), // output
......@@ -1205,6 +974,470 @@ simul_axi_read #(
end
endtask
// tasks - when tested - move to includes
task test_write_levelling; // SuppressThisWarning VEditor - may be unused
begin
// Set special values for DQS idelay for write leveling
wait_ps_pio_done(DEFAULT_STATUS_MODE); // not no interrupt running cycle - delays are changed immediately
axi_set_dqs_idelay_wlv;
// Set write buffer (from DDR3) WE signal delay for write leveling mode
axi_set_wbuf_delay(WBUF_DLY_WLV);
axi_set_dqs_odelay('h80); // 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
// @ (negedge rstb);
axi_set_dqs_odelay(DLY_DQS_ODELAY);
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
// @ (negedge rstb);
axi_set_dqs_idelay_nominal;
// axi_set_dqs_odelay_nominal;
axi_set_dqs_odelay('h78);
axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY
end
endtask
task test_read_pattern; // SuppressThisWarning VEditor - may be unused
begin
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
endtask
task test_write_block; // SuppressThisWarning VEditor - may be unused
begin
// write_block_buf_chn; // fill block memory - already set in set_up task
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
end
endtask
task test_read_block; // SuppressThisWarning VEditor - may be unused
begin
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
endtask
task test_scanline_write; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input [1:0] extra_pages;
input wait_done;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
begin
$display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t",
channel, extra_pages, wait_done, $time);
case (channel)
1: begin
start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
end
3: begin
start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN3_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 1 and 3 are valid");
start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
end
endcase
mode= func_encode_mode_scanline(
extra_pages,
1, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(start_addr+ MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);
configure_channel_priority(channel,0); // lowest priority channel 3
// enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
// VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
write_block_scanline_chn(
channel,
(ii & 3),
SCANLINE_XFER_SIZE,
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii< (WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW) ;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
status_address, //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
write_block_scanline_chn(
channel,
(ii & 3),
SCANLINE_XFER_SIZE,
WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
if (wait_done) begin
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
status_address, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0); // equal to
// enable_memcntrl_en_dis(channel,0); // disable channel
end
end
endtask
task test_scanline_read; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input [1:0] extra_pages;
input show_data;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
begin
$display("====== test_scanline_read: channel=%d, extra_pages=%d, show_data=%d @%t",
channel, extra_pages, show_data, $time);
case (channel)
1: begin
start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
end
3: begin
start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN3_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 1 and 3 are valid");
start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
end
endcase
mode= func_encode_mode_scanline(
extra_pages,
0, // write_mem,
1, // enable
0); // chn_reset
// program to the
write_contol_register(start_addr + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<(WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW);ii = ii+1) begin
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
(
((ii % SCANLINE_PAGES_PER_ROW) < (SCANLINE_PAGES_PER_ROW-1))?
(1<<NUM_XFER_BITS):
(WINDOW_WIDTH % (1<<NUM_XFER_BITS))
)
):
(WINDOW_WIDTH));
wait_status_condition (
status_address, //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii) << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
// read block (if needed), for now just sikip
if (show_data) begin
read_block_buf_chn (
channel,
(ii & 3),
SCANLINE_XFER_SIZE <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
end
endtask
task test_tiled_write; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input byte32;
input keep_open;
input [1:0] extra_pages;
input wait_done;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
begin
$display("====== test_tiled_write: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, wait_done=%d @%t",
channel, byte32, keep_open, extra_pages, wait_done, $time);
case (channel)
2: begin
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
4: begin
start_addr= MCNTRL_TILED_CHN4_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN4_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 2 and 4 are valid");
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
endcase
mode= func_encode_mode_tiled(
byte32,
keep_open,
extra_pages,
1, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
channel, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
status_address, // MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
channel, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
if (wait_done) begin
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
status_address, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0); // equal to
// enable_memcntrl_en_dis(channel,0); // disable channel
end
end
endtask
task test_tiled_read; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input byte32;
input keep_open;
input [1:0] extra_pages;
input show_data;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
begin
$display("====== test_tiled_read: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, show_data=%d @%t",
channel, byte32, keep_open, extra_pages, show_data, $time);
case (channel)
2: begin
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
4: begin
start_addr= MCNTRL_TILED_CHN4_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN4_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 2 and 4 are valid");
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
endcase
mode= func_encode_mode_tiled(
byte32,
keep_open,
extra_pages,
0, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
wait_status_condition (
status_address, // MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
ii << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
if (show_data) begin
read_block_buf_chn (
channel,
(ii & 3),
TILE_SIZE <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
// enable_memcntrl_en_dis(channel,0); // disable channel
end
endtask
task set_all_sequences;
begin
$display("SET MRS @ %t",$time);
......@@ -1234,7 +1467,8 @@ task set_all_sequences;
endtask
task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
// input integer chn; // buffer channel
input [3:0] chn; // buffer channel
input [1:0] page;
// input integer num_words; // number of words to write (will be rounded up to multiple of 16)
input [NUM_XFER_BITS:0] num_bursts; // number of 8-bursts to write (will be rounded up to multiple of 16)
......@@ -1246,12 +1480,14 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
// $display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_words, $time);
$display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_bursts, $time);
case (chn)
0: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
5: start_addr=MCONTR_BUF5_WR_ADDR + (page << 8); // it is actually tiled, not scanline
4: start_addr=MCONTR_BUF4_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
end
endcase
num_words=num_bursts << 2;
......@@ -1260,11 +1496,47 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
end
endtask
function [6:0] func_encode_mode_tiled;
input byte32; // 32-byte columns (0 - 16-byte columns)
input keep_open; // for 8 or less rows - do not close page between accesses
input [1:0] extra_pages; // number of extra pages that need to stay (not to be overwritten) in the buffer
// can be used for overlapping tile read access
input write_mem; // write to memory mode (0 - read from memory)
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
begin
func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
end
endfunction
function [4:0] func_encode_mode_scanline;
input [1:0] extra_pages; // number of extra pages that need to stay (not to be overwritten) in the buffer
// can be used for overlapping tile read access
input write_mem; // write to memory mode (0 - read from memory)
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
begin
func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
end
endfunction
/*
task enable_memcntrl_en_dis;
input [3:0] chn;
input en;
begin
if (en) begin
ENABLED_CHANNELS = ENABLED_CHANNELS | (1<<chn);
end else begin
ENABLED_CHANNELS = ENABLED_CHANNELS & ~(1<<chn);
end
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
end
endtask
*/
`include "includes/x393_tasks_mcntrl_en_dis_priority.vh"
`include "includes/x393_tasks_mcntrl_buffers.vh"
`include "includes/x393_tasks_pio_sequences.vh"
`include "includes/x393_tasks_mcntrl_timing.vh"
`include "includes/x393_tasks_mcntrl_timing.vh"
`include "includes/x393_tasks_ps_pio.vh"
`include "includes/x393_tasks_status.vh"
`include "includes/x393_tasks01.vh"
......
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