more simulating/debugging of sensor interface modules (aa331d14) · Commits · Elphel / x393

includes/x393_simulation_parameters.vh

+4 −2

Original line number	Diff line number	Diff line
		@@ -56,6 +56,8 @@
		parameter HISTOGRAM_STRAT_PAGE = 20'h12345,
		parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)

		parameter WOI_WIDTH= 64
		parameter WOI_WIDTH= 64,
		parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2
		// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]


		No newline at end of file

sensor/pxd_single.v

+2 −2

Original line number	Diff line number	Diff line
		@@ -53,8 +53,8 @@ module pxd_single#(

		assign pxd_in=pxd_r;
		// assign pxd_async = pxd_iobuf;
		always @ (posedge mclk) begin
		if (mrst) pxd_r <= 0;
		always @ (posedge ipclk) begin
		if (irst) pxd_r <= 0;
		else pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]);
		end

sensor/sens_parallel12.v

+43 −18

Original line number	Diff line number	Diff line
		@@ -101,8 +101,8 @@ module sens_parallel12 #(
		inout aro,
		output dclk, // externally connected to inout port
		// output
		output [11:0] pxd_out,
		output vact_out,
		output reg [11:0] pxd_out,
		output reg vact_out,
		output hact_out,

		// JTAG to program 10359
		@@ -124,6 +124,10 @@ module sens_parallel12 #(
		input status_start // Acknowledge of the first status packet byte (address)
		);

		// delaying vact and pxd by one clock cycle to match hact register
		wire [11:0] pxd_out_pre;
		wire vact_out_pre;

		reg [2:0] irst_r;
		wire ibpf;
		wire ipclk_pre, ipclk2x_pre;
		@@ -133,10 +137,14 @@ module sens_parallel12 #(
		reg set_ctrl_r;
		reg set_status_r;
		reg [1:0] set_width_r; // to make double-cycle subtract
		wire set_width_ipclk; //re-clocked to pclk
		reg set_jtag_r;

		reg [LINE_WIDTH_BITS-1:0] line_width_m1; // regenerated HACT duration;
		reg [LINE_WIDTH_BITS-1:0] line_width_m1_ipclk; // regenerated HACT duration;

		reg line_width_internal; // use regenetrated ( 0 - use HACT as is)
		reg line_width_internal_ipclk;
		reg [LINE_WIDTH_BITS-1:0] hact_cntr;

		// reg set_quad; // [1:0] - px, [3:2] - HACT, [5:4] - VACT,
		@@ -254,20 +262,29 @@ module sens_parallel12 #(

		if (mclk_rst) line_width_internal <= 0;
		else if (set_width_r[1]) line_width_internal <= ~ (\|data_r[LINE_WIDTH_BITS:0]);
		end

		// regenerate/propagate HACT
		always @(posedge ipclk) begin
		if (irst) line_width_m1_ipclk <= 0;
		else if (set_width_ipclk) line_width_m1_ipclk <= line_width_m1;

		if (mclk_rst) hact_ext_r <= 1'b0;
		if (irst) line_width_internal_ipclk <= 0;
		else if (set_width_ipclk) line_width_internal_ipclk <= line_width_internal;
		// regenerate/propagate HACT
		if (irst) hact_ext_r <= 1'b0;
		else hact_ext_r <= hact_ext;

		if (mclk_rst) hact_r <= 0;
		if (irst) hact_r <= 0;
		else if (hact_ext && !hact_ext_r) hact_r <= 1;
		else if (line_width_internal?(hact_cntr == 0):( hact_ext ==0)) hact_r <= 0;
		else if (line_width_internal_ipclk?(hact_cntr == 0):(hact_ext ==0)) hact_r <= 0;

		if (mclk_rst) hact_cntr <= 0;
		else if (hact_ext && !hact_ext_r) hact_cntr <= line_width_m1;
		if (irst) hact_cntr <= 0;
		else if (hact_ext && !hact_ext_r) hact_cntr <= line_width_m1_ipclk; // from mclk
		else if (hact_r) hact_cntr <= hact_cntr - 1;

		pxd_out <= pxd_out_pre;
		vact_out <= vact_out_pre;

		end

		/*
		@@ -299,6 +316,14 @@ module sens_parallel12 #(

		*/

		pulse_cross_clock pulse_cross_clock_set_width_ipclk_i (
		.rst (mclk_rst), // input
		.src_clk (mclk), // input
		.dst_clk (ipclk), // input
		.in_pulse (set_width_r[1]), // input
		.out_pulse (set_width_ipclk), // output
		.busy() // output
		);



		@@ -352,7 +377,7 @@ module sens_parallel12 #(
		.pxd_out (xfpgatdi), // input
		.pxd_en (xpgmen), // input
		.pxd_async (), // output
		.pxd_in (pxd_out[0]), // output
		.pxd_in (pxd_out_pre[0]), // output
		.ipclk (ipclk), // input
		.ipclk2x (ipclk2x), // input
		.mrst (mclk_rst), // input
		@@ -379,7 +404,7 @@ module sens_parallel12 #(
		.pxd_out (1'b0), // input
		.pxd_en (1'b0), // input
		.pxd_async (xfpgatdo), // output
		.pxd_in (pxd_out[1]), // output
		.pxd_in (pxd_out_pre[1]), // output
		.ipclk (ipclk), // input
		.ipclk2x (ipclk2x), // input
		.mrst (mclk_rst), // input
		@@ -403,12 +428,12 @@ module sens_parallel12 #(
		.PXD_SLEW (PXD_SLEW),
		.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
		) pxd_pxd1_i (
		) pxd_pxd2_12_i (
		.pxd (pxd[i]), // inout
		.pxd_out (1'b0), // input
		.pxd_en (1'b0), // input
		.pxd_async (), // output
		.pxd_in (pxd_out[i]), // output
		.pxd_in (pxd_out_pre[i]), // output
		.ipclk (ipclk), // input
		.ipclk2x (ipclk2x), // input
		.mrst (mclk_rst), // input
		@@ -464,7 +489,7 @@ module sens_parallel12 #(
		.pxd_out (1'b0), // input
		.pxd_en (1'b0), // input
		.pxd_async (), // output
		.pxd_in (vact_out), // output
		.pxd_in (vact_out_pre), // output
		.ipclk (ipclk), // input
		.ipclk2x (ipclk2x), // input
		.mrst (mclk_rst), // input

sensor/sensor_fifo.v

+78 −12

Original line number	Diff line number	Diff line
		@@ -47,11 +47,11 @@ module sensor_fifo #(
		// output clock domain
		// wire pre_re;
		wire re; // re_w,re;
		reg re_r;
		// reg re_r;
		reg [1:0] pre_hact;
		reg hact_out_r;
		reg [1:0] hact_out_r;
		reg [SENSOR_DATA_WIDTH-1:0] pxd_r;
		wire hact_out_start;
		// wire hact_out_start;

		assign we=sof_in \|\| eof_in \|\| hact \|\| hact_r;
		always @(posedge iclk) begin
		@@ -75,7 +75,7 @@ module sensor_fifo #(
		.nempty (nempty), // output
		.half_empty () // output
		);

		/*
		dly_16 #(
		.WIDTH(1)
		) hact_dly_16_i (
		@@ -85,21 +85,85 @@ module sensor_fifo #(
		.din(pre_hact[0] && ! pre_hact[1]), // input[0:0]
		.dout(hact_out_start) // output[0:0]
		);
		*/
		wire pre_sof_pclk;
		wire pre_eof_pclk;
		wire pre_sol_pclk;

		wire sof_pclk;
		wire eof_pclk;
		wire sol_pclk;

		pulse_cross_clock pulse_cross_clock_sof_i (
		.rst (irst), // input
		.src_clk (iclk), // input
		.dst_clk (pclk), // input
		.in_pulse (sof_in), // input
		.out_pulse (pre_sof_pclk), // output
		.busy() // output
		);

		pulse_cross_clock pulse_cross_clock_eof_i (
		.rst (irst), // input
		.src_clk (iclk), // input
		.dst_clk (pclk), // input
		.in_pulse (eof_in), // input
		.out_pulse (pre_eof_pclk), // output
		.busy() // output
		);

		pulse_cross_clock pulse_cross_clock_sol_i (
		.rst (irst), // input
		.src_clk (iclk), // input
		.dst_clk (pclk), // input
		.in_pulse (hact && !hact_r), // input
		.out_pulse (pre_sol_pclk), // output
		.busy() // output
		);

		dly_16 #(
		.WIDTH(3)
		) hact_dly_16_i (
		.clk(pclk), // input
		.rst(prst), // input
		.dly(SENSOR_FIFO_DELAY), // input[3:0]
		.din({pre_sof_pclk, pre_eof_pclk, pre_sol_pclk}), // input[0:0]
		.dout({sof_pclk, eof_pclk, sol_pclk}) // output[0:0]
		);



		reg sof_rq;
		reg eof_rq;
		reg sol_rq;
		always @ (posedge pclk) begin
		if (prst \|\| (re && sof_w)) sof_rq <= 0;
		else if (sof_pclk) sof_rq <= 1;

		if (prst \|\| (re && eof_w)) eof_rq <= 0;
		else if (eof_pclk) eof_rq <= 1;

		if (prst \|\| (re && hact_out_r[0] && !hact_out_r[1])) sol_rq <= 0;
		else if (sol_pclk) sol_rq <= 1;
		end



		// output clock domain
		// assign pre_re = nempty && !re_r;
		// Generating first read (for hact), then wait to fill half FIFO and continue continuous read until hact end
		// assign re_w = re_r && nempty; // to protect from false positive on nempty
		// assign re = (re_w && !pre_hact) \|\| hact_out_r; // no check for nempty - producing un-interrupted stream
		assign re = (re_r && nempty && !pre_hact[0]) \|\| hact_out_r; // no check for nempty - producing un-interrupted stream
		// assign re = (re_r && nempty && !pre_hact[0]) \|\| hact_out_r[0]; // no check for nempty - producing un-interrupted stream
		assign re = ((sof_rq \|\| eof_rq \|\| sol_rq) && nempty) \|\| hact_out_r[0]; // no check for nempty - producing un-interrupted stream
		assign pxd_out= pxd_r;
		assign data_valid = hact_out_r;
		assign data_valid = hact_out_r[1];
		assign sof = sof_r;
		assign eof = eof_r;

		always @(posedge pclk) begin
		if (prst) re_r <= 0;
		else re_r <= nempty && !re_r && !pre_hact[0]; // only generate one cycle (after SOF of HACT)
		// if (prst) re_r <= 0;
		// else re_r <= nempty && !re_r && !pre_hact[0]; // only generate one cycle (after SOF of HACT)

		if (prst) pre_hact[0] <= 0;
		else if (re) pre_hact[0] <= hact_w;
		@@ -111,10 +175,12 @@ module sensor_fifo #(
		if (prst) pxd_r <= 0;
		else if (re) pxd_r <= pxd_w;

		if (prst) hact_out_r <= 0;
		else if (hact_out_start) hact_out_r <= 1;
		// else if (!hact_w) hact_out_r <= 0;
		else if (!(hact_w && re)) hact_out_r <= 0;
		if (prst) hact_out_r[0] <= 0;
		else if (sol_pclk) hact_out_r[0] <= 1;
		else if (!(hact_w) && re) hact_out_r[0] <= 0;

		if (prst \|\| (!(hact_w) && re)) hact_out_r[1] <= 0;
		else hact_out_r[1] <= hact_out_r[0];

		if (prst) sof_r <= 0;
		else sof_r <= re && sof_w;

x393_testbench02.tf

+4 −2

Original line number	Diff line number	Diff line
		@@ -1910,7 +1910,9 @@ task setup_sensor_channel;
		3, // input [1:0] clk_sel; // <2: keep MMCM clock source, 2 - use internal pixel clock, 3 - use pixel clock from the sensor
		0, // input set_delays; // (self-clearing) load all pre-programmed delays
		1'b1, // input set_quadrants; // 0 - keep quadrants settings, 1 - update quadrants
		6'h24); // data-0, hact - 1, vact - 2 input [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants; // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
		// 6'h24); // data-0, hact - 1, vact - 2 input [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants; // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
		// 6'h01); // data-1, hact - 0, vact - 0 input [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants; // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
		QUADRANTS_PXD_HACT_VACT); // data-0, hact - 1, vact - 2 input [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants; // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
		/*
		// setup camsync module
		reset_camsync_inout (0); // reset input selection

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