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x393
Commit a7d6e9ea authored by Andrey Filippov's avatar Andrey Filippov
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multiple updates, fpga version 0393021f

parent 2cb5c0b4
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fpga_version.vh
View file @ a7d6e9ea
......@@ -35,7 +35,17 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930215; // pclk phase -3.0 (multiple of 1.5)
parameter FPGA_VERSION = 32'h0393021f; // (ext resistor) low_pwr, DIFF_SSTL18_I pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h0393021e; // internal 100ohm, low_pwr, LVDS_25 pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h0393021d; // (ext resistor) low_pwr, DIFF_SSTL18_I pclk phase 0.0 mmcm phase -22.5 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h0393021c; // untuned_60 DIFF_SSTL18_I pclk phase 0.0 mmcm phase -21.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1
// parameter FPGA_VERSION = 32'h0393021b; // untuned_50 DIFF_SSTL18_I pclk phase 0.0 mmcm phase -21.0 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h0393021a; // ext 100Ohm/DIFF_SSTL18_I pclk phase 0.0 mmcm phase -21.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1
// parameter FPGA_VERSION = 32'h03930219; // MINI_LVDS_25 pclk phase 0.0 mmcm phase -21.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1
// parameter FPGA_VERSION = 32'h03930218; // pclk phase 0.0 mmcm phase -21.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1
// parameter FPGA_VERSION = 32'h03930217; // pclk phase 0.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1
// parameter FPGA_VERSION = 32'h03930216; // pclk phase -3.0 (multiple of 1.5) set TWEAKING_IOSTANDARD 1
// parameter FPGA_VERSION = 32'h03930215; // pclk phase -3.0 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h03930214; // pclk phase +3.0 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h03930213; // bug fixing in frame_start_pending_long
// parameter FPGA_VERSION = 32'h03930212; // test mode interface, no-pending frames
......
includes/x393_parameters.vh
View file @ a7d6e9ea
......@@ -707,28 +707,41 @@
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "MINI_LVDS_25", // "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
parameter CLKFBOUT_PHASE_SENSOR = -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
parameter CLKFBOUT_PHASE_SENSOR = -22.5, // -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.0, // -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
parameter IPCLK2X_PHASE = 0.000,
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // "60", // "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
......@@ -737,20 +750,18 @@
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "MINI_LVDS_25", // "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
`else
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
`ifdef BOSON
......@@ -804,11 +815,6 @@
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
`ifdef BOSON
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // "TRUE",
`else
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`endif
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
......
py393/x393_export_c.py
View file @ a7d6e9ea
......@@ -1908,7 +1908,7 @@ class X393ExportC(object):
dw.append(("ps_out", 0, 8,0, "Sensor MMCM current phase"))
dw.append(("ps_rdy", 8, 1,0, "Sensor MMCM phase ready"))
dw.append(("perr", 9, 1,0, "Parity error in video stream"))
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("recv_odd_even", 10, 1,0, "UART receive odd/even output byte (next byte should have it inverted)"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked - wait after removing sensor mrst!"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
......@@ -1920,8 +1920,6 @@ class X393ExportC(object):
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......
py393/x393_sens_cmprs.py
View file @ a7d6e9ea
......@@ -934,10 +934,11 @@ class X393SensCmprs(object):
chn_en = True,
bits16 = bits16) #False)
if sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
if sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
skip_frames = 70 # 65 < min <70. 70 shows 4 frames, 100 shows 35 frames over uart
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (70): # 65): #70): #80): #100): # 60 10 2
for _ in range (skip_frames): # 65): #70): #80): #100): # 60 10 2
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
......@@ -1933,7 +1934,7 @@ class X393SensCmprs(object):
for module in x393_sensor.BOSON_MAP:
mod_index, indx = x393_sensor.BOSON_MAP[module]
for byte_var in range(4):
num_payload_bytes = (0,1,2,4)[byte_var]
# num_payload_bytes = (0,1,2,4)[byte_var]
self.x393Sensor.set_sensor_i2c_table_reg_wr (
num_sensor = num_sensor,
page = indx * 4 + byte_var,
......
py393/x393_sensor.py
View file @ a7d6e9ea
......@@ -1732,7 +1732,7 @@ uart_print_packet 0 False False
wait_packet = True,
enable_sequencer = True):
"""
Send packet to UART (assuming sequencer is disabled if needed)
Read packet from UART (assuming sequencer is disabled if needed)
@param num_sensor - sensor port number (0..3)
@param wait packet - if False, return empty packet if none is available
@param enable_sequencer (Re)enable sequencer commands
......
sensor/sens_103993.v
View file @ a7d6e9ea
......@@ -269,6 +269,7 @@ module sens_103993 #(
wire recv_pav; // output
wire recv_eop; // output fifo not empty
wire [7:0] recv_data; // output[7:0]
wire recv_odd_even;// output odd/even output counter for status (next byte should have inverted)
wire senspgmin; // detect sensorboard
// GP0..GP3 are not yet used, fake-use gp_comb to keep
......@@ -285,7 +286,7 @@ module sens_103993 #(
imrst ? hact_alive : gp_comb, // 13 using gp_comb to keep
locked_pclk, // 12 // wait after mrst
test_patt? nonlock_persistent : clkin_pxd_stopped_mmcm, // 11
clkfb_pxd_stopped_mmcm, // 10
recv_odd_even, // clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
test_patt? perr : ps_rdy, // 8
test_patt? test_out[7:0]:ps_out[7:0],// [7:0]
......@@ -449,7 +450,9 @@ module sens_103993 #(
.recv_next (recv_next), // input
.recv_pav (recv_pav), // output at least one received packet is in fifo
.recv_eop (recv_eop), // output end of packet (discard recv_data; apply recv_next)
.recv_data (recv_data) // output[7:0]
.recv_data (recv_data), // output[7:0]
.recv_odd_even (recv_odd_even)// output odd/even output counter for status (next byte should have inverted)
);
......
sensor/sens_103993_clock.v
View file @ a7d6e9ea
......@@ -121,6 +121,49 @@ module sens_103993_clock#(
.I (clp_p), // input
.IB (clk_n) // input
);
// variable termination
end else if (LVDS_UNTUNED_SPLIT == "40") begin
ibufds_ibufgds_40 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "50") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else if (LVDS_UNTUNED_SPLIT == "60") begin
ibufds_ibufgds_60 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
......
sensor/sens_103993_din.v
View file @ a7d6e9ea
......@@ -88,6 +88,48 @@ module sens_103993_din #(
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else if (LVDS_UNTUNED_SPLIT == "40") begin
ibufds_ibufgds_40 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else if (LVDS_UNTUNED_SPLIT == "50") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else if (LVDS_UNTUNED_SPLIT == "60") begin
ibufds_ibufgds_60 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
......
sensor/serial_103993.v
View file @ a7d6e9ea
......@@ -83,7 +83,8 @@ module serial_103993#(
// output recv_dav, // read byte available
output recv_pav, // packet available
output recv_eop, // end of packet (discard recv_data, apply recv_next)
output [7:0] recv_data
output [7:0] recv_data,
output recv_odd_even // odd/even output counter for status (next byte should have inverted)
);
wire [ 7:0] xmit_fifo_out;
......@@ -141,6 +142,7 @@ module serial_103993#(
// wire recv_end; // Discard recv_data, this is packet end
wire recv_prgrs; // packet is being received (to distinguish eop from data byte)
wire xmit_run_any;
reg recv_odd_even_r;
assign extif_rq_w = packet_ready_seq && !extif_run && !packet_over_seq;
assign xmit_any_data = extif_run ? xmit_extif_data : xmit_fifo_out;
......@@ -156,6 +158,7 @@ module serial_103993#(
assign recv_fifo_wr = fslp_stb_or_done;
assign recv_pav = recv_pav_r;
assign xmit_run_any = xmit_run || extif_run;
assign recv_odd_even = recv_odd_even_r;
// assign recv_eop = recv_end;
always @(posedge mclk) begin
fslp_stb_or_done <= fslp_rx_stb || fslp_rx_done;
......@@ -207,7 +210,8 @@ module serial_103993#(
xmit_stb_seq <= pre_tx_stb && extif_run_in;
xmit_over_seq <= pre_tx_stb && packet_over_seq;
if (mrst) recv_odd_even_r <= 0;
else if (recv_fifo_re_regen[1]) recv_odd_even_r <= !recv_odd_even_r;
end
serial_103993_extif #(
......
wrap/ibufds_ibufgds.v
View file @ a7d6e9ea
......@@ -75,6 +75,36 @@ module ibufds_ibufgds #(
endmodule
module ibufds_ibufgds_40 #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
(* IN_TERM="UNTUNED_SPLIT_40" *)
IBUFDS #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
.DQS_BIAS (DQS_BIAS),
.IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFDS_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
module ibufds_ibufgds_50 #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
......@@ -104,4 +134,32 @@ module ibufds_ibufgds_50 #(
);
endmodule
module ibufds_ibufgds_60 #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
(* IN_TERM="UNTUNED_SPLIT_60" *)
IBUFDS #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
.DQS_BIAS (DQS_BIAS),
.IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFDS_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
x393_boson.bit
View file @ a7d6e9ea
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