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Commit a78a7d75 authored by Andrey Filippov's avatar Andrey Filippov
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removed conflicting line from hargs-after

parent dcb169c1
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py393/hargs-after
View file @ a78a7d75
...@@ -6,5 +6,4 @@ ...@@ -6,5 +6,4 @@
-c bitstream_set_path /usr/local/verilog/x393_parallel.bit -c bitstream_set_path /usr/local/verilog/x393_parallel.bit
-c specify_phys_memory -c specify_phys_memory
-c specify_window -c specify_window
-c set_qtables all 0 80
-i -i
py393/x393_jpeg.py
View file @ a78a7d75
...@@ -1049,8 +1049,8 @@ setup_all_sensors True None 0x4 ...@@ -1049,8 +1049,8 @@ setup_all_sensors True None 0x4
################## Parallel after drivers ################## ################## Parallel after drivers ##################
cd /usr/local/verilog/; test_mcntrl.py @hargs-after cd /usr/local/verilog/; test_mcntrl.py @hargs-after
specify_phys_memory
specify_window set_qtables all 0 80
r r
read_control_register 0x431 read_control_register 0x431
......
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