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Commit a445ef42 authored by Andrey Filippov's avatar Andrey Filippov
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added another channel for testing - tile write

parent 31a6b971
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.editor_defines.vh
View file @ a445ef42
......@@ -2,7 +2,7 @@
// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
`define IVERILOG 1
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
......@@ -33,8 +33,10 @@
`define def_read_mem_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 5 is enabled
`define def_enable_mem_chn5
`undef def_read_mem_chn5
`define def_tiled_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
......
axi/axibram.v deleted 100644 → 0
View file @ 31a6b971
/*******************************************************************************
* Module: axibram
* Date:2014-03-18
* Author: Andrey Filippov
* Description:
*
* Copyright (c) 2014 Elphel, Inc.
* axibram.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* axibram.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
module axibram(
input aclk, // clock - should be buffered
input aresetn, // reset, active low
// AXI Read Address
input [31:0] araddr, // ARADDR[31:0], input
input arvalid, // ARVALID, input
output arready, // ARREADY, output
input [11:0] arid, // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
input [ 3:0] arlen, // ARLEN[3:0], input
input [ 1:0] arsize, // ARSIZE[1:0], input
input [ 1:0] arburst, // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
output [31:0] rdata, // RDATA[31:0], output
output reg rvalid, // RVALID, output
input rready, // RREADY, input
output reg [11:0] rid, // RID[11:0], output
output reg rlast, // RLAST, output
output [ 1:0] rresp, // RRESP[1:0], output
// AXI Write Address
input [31:0] awaddr, // AWADDR[31:0], input
input awvalid, // AWVALID, input
output awready, // AWREADY, output
input [11:0] awid, // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
input [ 3:0] awlen, // AWLEN[3:0], input
input [ 1:0] awsize, // AWSIZE[1:0], input
input [ 1:0] awburst, // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
input [31:0] wdata, // WDATA[31:0], input
input wvalid, // WVALID, input
output wready, // WREADY, output
input [11:0] wid, // WID[11:0], input
input wlast, // WLAST, input
input [ 3:0] wstb, // WSTRB[3:0], input
// AXI PS Master GP0: Write Responce
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp // BRESP[1:0], output
);
// **** Read channel ****
wire ar_nempty;
wire ar_half_full;
assign arready=~ar_half_full;
wire [ 1:0] arburst_out;
// SuppressWarnings VEditor all
wire [ 1:0] arsize_out; // not used
wire [ 3:0] arlen_out;
wire [ 9:0] araddr_out;
wire [11:0] arid_out;
wire rst=~aresetn;
reg read_in_progress=0;
reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
reg read_in_progress_or=0; // read_in_progress || read_in_progress_d
reg [ 9:0] read_address; // transfer address (not including lower bits
reg [ 3:0] read_left; // number of read transfers
// will ignore arsize - assuming always 32 bits (a*size[2:0]==2)
reg [ 1:0] rburst; // registered burst type
reg [ 3:0] rlen; // registered burst type
wire [ 9:0] next_rd_address_w; // next transfer address;
assign next_rd_address_w=
rburst[1]?
(rburst[0]? (10'h0):((read_address[9:0]+1) & {6'h3f, ~rlen[3:0]})):
(rburst[0]? (read_address[9:0]+1):(read_address[9:0]));
wire start_read_burst_w;
// wire bram_re_w;
wire bram_reg_re_w;
wire read_in_progress_w;
wire read_in_progress_d_w;
wire last_in_burst_w;
wire last_in_burst_d_w;
reg pre_last_in_burst_r;
assign rresp=2'b0;
// reduce combinatorial delay from rready (use it in final mux)
// assign bram_reg_re_w= read_in_progress && (!rvalid || rready);
// assign start_read_burst_w=ar_nempty && (!read_in_progress || (bram_reg_re_w && (read_left==4'b0))); // reduce delay from arready
assign last_in_burst_w= bram_reg_re_w && (read_left==4'b0);
assign last_in_burst_d_w=bram_reg_re_w && pre_last_in_burst_r;
// make sure ar_nempty is updated
// assign start_read_burst_w=ar_nempty && (!read_in_progress || last_in_burst_w); // reduce delay from arready
assign read_in_progress_w= start_read_burst_w || (read_in_progress && !last_in_burst_w); // reduce delay from arready
assign read_in_progress_d_w=(read_in_progress && bram_reg_re_w) ||
(read_in_progress && !last_in_burst_d_w); // reduce delay from arready
// assign read_in_progress_d_w=read_in_progress_d;
wire pre_rvalid_w;
assign pre_rvalid_w=bram_reg_re_w || (rvalid && !rready);
reg bram_reg_re_0;
wire pre_left_zero_w;
reg last_in_burst_1;
reg last_in_burst_0;
reg start_read_burst_0;
reg start_read_burst_1;
reg [11:0] pre_rid0;
reg [11:0] pre_rid;
always @ (posedge aclk or posedge rst) begin
if (rst) pre_last_in_burst_r <= 0;
// else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
else if (bram_reg_re_w) pre_last_in_burst_r <= (read_left==4'b0);
if (rst) rburst[1:0] <= 0;
else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];
if (rst) rlen[3:0] <= 0;
else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];
if (rst) read_in_progress <= 0;
else read_in_progress <= read_in_progress_w;
if (rst) read_in_progress_d <= 0;
// else read_in_progress_d <= read_in_progress_d_w;
else if (bram_reg_re_w) read_in_progress_d <= read_in_progress_d_w;
if (rst) read_in_progress_or <= 0;
// else read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// else if (bram_reg_re_w) read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// FIXME:
else if (bram_reg_re_w || !read_in_progress_or) read_in_progress_or <= read_in_progress_d_w || read_in_progress_w;
// reg read_in_progress_d=0; // delayed by one active cycle (not skipped)
// reg read_in_progress_or=0; // read_in_progress || read_in_progress_d
if (rst) read_left <= 0;
else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
else if (bram_reg_re_w) read_left <= read_left-1;
if (rst) read_address <= 10'b0;
else if (start_read_burst_w) read_address <= araddr_out[9:0]; // precedence over inc
else if (bram_reg_re_w) read_address <= next_rd_address_w;
if (rst) rvalid <= 1'b0;
else if (bram_reg_re_w && read_in_progress_d) rvalid <= 1'b1;
else if (rready) rvalid <= 1'b0;
if (rst) rlast <= 1'b0;
else if (last_in_burst_d_w) rlast <= 1'b1;
else if (rready) rlast <= 1'b0;
end
always @ (posedge aclk) begin
// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;
bram_reg_re_0 <= (ar_nempty && !read_in_progress) || (read_in_progress && !read_in_progress);
last_in_burst_1 <= read_in_progress_w && pre_left_zero_w;
last_in_burst_0 <= read_in_progress_w && !pre_rvalid_w && pre_left_zero_w;
start_read_burst_1 <= !read_in_progress_w || pre_left_zero_w;
start_read_burst_0 <= !read_in_progress_w || (!pre_rvalid_w && pre_left_zero_w);
if (start_read_burst_w) pre_rid0[11:0] <= arid_out[11:0];
if (bram_reg_re_w) pre_rid[11:0] <= pre_rid0[11:0];
if (bram_reg_re_w) rid[11:0] <= pre_rid[11:0];
end
// reducing rready combinatorial delay
assign pre_left_zero_w=start_read_burst_w?(arlen_out[3:0]==4'b0):(bram_reg_re_w && (read_left==4'b0001));
// assign bram_reg_re_w= read_in_progress && (!rvalid || rready);
assign bram_reg_re_w= read_in_progress_or && (!rvalid || rready); // slower/simplier
// assign bram_reg_re_w= rready? read_in_progress : bram_reg_re_0; // faster - more verification
assign last_in_burst_w=bram_reg_re_w && (read_left==4'b0); // slower/simplier
// assign last_in_burst_w=rready? (read_in_progress && (read_left==4'b0)): (bram_reg_re_0 && (read_left==4'b0));
// assign last_in_burst_w=rready? last_in_burst_1: last_in_burst_0; // faster (unfinished) - more verification
assign start_read_burst_w=ar_nempty && (!read_in_progress || (bram_reg_re_w && (read_left==4'b0))); // reduce delay from rready
// assign start_read_burst_w=ar_nempty && (!read_in_progress || ((rready? read_in_progress : bram_reg_re_0) && (read_left==4'b0)));
// assign start_read_burst_w=
// rready?
// (ar_nempty && (!read_in_progress || ((read_in_progress) && (read_left==4'b0)))):
// (ar_nempty && (!read_in_progress || ((bram_reg_re_0 ) && (read_left==4'b0))));
/*
assign start_read_burst_w=
ar_nempty*(rready?
(!read_in_progress || (read_left==4'b0)):
((!read_in_progress || ((bram_reg_re_0 ) && (read_left==4'b0)))));
*/
// assign start_read_burst_w= ar_nempty && (rready?start_read_burst_1:start_read_burst_0);
// **** Write channel: ****
wire aw_nempty;
wire aw_half_full;
assign awready=~aw_half_full;
wire [ 1:0] awburst_out;
// SuppressWarnings VEditor all
wire [ 1:0] awsize_out; // not used
wire [ 3:0] awlen_out;
wire [ 9:0] awaddr_out;
// SuppressWarnings VEditor all
wire [11:0] awid_out; // not used
wire w_nempty;
wire w_half_full;
assign wready=~w_half_full;
wire [31:0] wdata_out;
// SuppressWarnings VEditor all
wire wlast_out; // not used
wire [ 3:0] wstb_out; // WSTRB[3:0], input
wire [11:0] wid_out;
reg write_in_progress=0;
reg [ 9:0] write_address; // transfer address (not including lower bits
reg [ 3:0] write_left; // number of read transfers
// will ignore arsize - assuming always 32 bits (a*size[2:0]==2)
reg [ 1:0] wburst; // registered burst type
reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers)
wire [ 9:0] next_wr_address_w; // next transfer address;
wire bram_we_w; // write BRAM memory
wire start_write_burst_w;
wire write_in_progress_w;
assign next_wr_address_w=
wburst[1]?
(wburst[0]? (10'h0):((write_address[9:0]+1) & {6'h3f, ~wlen[3:0]})):
(wburst[0]? (write_address[9:0]+1):(write_address[9:0]));
assign bram_we_w= w_nempty && write_in_progress;
assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0)));
always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0;
else if (start_write_burst_w) wburst[1:0] <= awburst_out[1:0];
if (rst) wlen[3:0] <= 0;
else if (start_write_burst_w) wlen[3:0] <= awlen_out[3:0];
if (rst) write_in_progress <= 0;
else write_in_progress <= write_in_progress_w;
if (rst) write_left <= 0;
else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc
else if (bram_we_w) write_left <= write_left-1;
if (rst) write_address <= 10'b0;
else if (start_write_burst_w) write_address <= awaddr_out[9:0]; // precedence over inc
else if (bram_we_w) write_address <= next_wr_address_w;
end
// **** Write responce channel ****
wire [ 1:0] bresp_in;
assign bresp_in=2'b0;
/*
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp // BRESP[1:0], output
*/
/*
reg bram_reg_re_r;
always @ (posedge aclk) begin
bram_reg_re_r <= bram_reg_re_w;
end
*/
ram_1kx32_1kx32
#(
.REGISTERS(1) // 1 - registered output
)
ram_1kx32_1kx32_i
(
.rclk(aclk), // clock for read port
.raddr(read_in_progress?read_address[9:0]:10'h3ff), // read address
// .ren(read_in_progress_or) , // read port enable
.ren(bram_reg_re_w) , // read port enable
.regen(bram_reg_re_w), // output register enable
// .regen(bram_reg_re_r), // output register enable
.data_out(rdata[31:0]), // data out
.wclk(aclk), // clock for read port
.waddr(write_address[9:0]), // write address
.we(bram_we_w), // write port enable
.web(wstb_out[3:0]), // write byte enable
.data_in(wdata_out[31:0]) // data out
);
fifo_same_clock #( .DATA_WIDTH(30),.DATA_DEPTH(4))
raddr_i (
.rst(rst),
.clk(aclk),
.we(arvalid && arready),
.re(start_read_burst_w),
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[11:2]}),
.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[9:0]}),
.nempty(ar_nempty),
.full(),
.half_full(ar_half_full)
);
fifo_same_clock #( .DATA_WIDTH(30),.DATA_DEPTH(4))
waddr_i (
.rst(rst),
.clk(aclk),
.we(awvalid && awready),
.re(start_write_burst_w),
.data_in({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[11:2]}),
.data_out({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[9:0]}),
.nempty(aw_nempty),
.full(),
.half_full(aw_half_full)
);
fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
.rst(rst),
.clk(aclk),
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
.data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}),
.nempty(w_nempty),
.full(),
.half_full(w_half_full)
);
fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.clk(aclk),
.we(bram_we_w),
.re(bready && bvalid),
.data_in({wid_out[11:0],bresp_in[1:0]}),
.data_out({bid[11:0],bresp[1:0]}),
.nempty(bvalid),
.full(),
.half_full()
);
endmodule
axi/axibram_write.v
View file @ a445ef42
......@@ -19,7 +19,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`define DEBUG_FIFO 1
//`define DEBUG_FIFO 1
module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits
)(
......@@ -197,6 +197,7 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (awvalid && awready),
.re (start_write_burst_w),
.data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
......@@ -216,6 +217,7 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
......@@ -244,6 +246,7 @@ fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i (
.rst(rst),
.clk(aclk),
.sync_rst (1'b0),
.we(bram_we_w),
// .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
......
ddrc_test01.v deleted 100644 → 0
View file @ 31a6b971
/*******************************************************************************
* Module: ddrc_test01
* Date:2014-05-18
* Author: Andrey Filippov
* Description: DDR3 controller test with axi
*
* Copyright (c) 2014 Elphel, Inc.
* ddrc_test01.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ddrc_test01.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
module ddrc_test01 #(
parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
parameter AXI_WR_ADDR_BITS = 13,
parameter AXI_RD_ADDR_BITS = 13,
parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h1400, // AXI write address of control registers
parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
parameter STATUS_ADDR_MASK = 'h1400, // AXI write address of status registers
parameter BUSY_WR_ADDR = 'h1800, // AXI write address to generate busy
parameter BUSY_WR_ADDR_MASK = 'h1c00, // AXI write address mask to generate busy
parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
parameter PORT0_RD_ADDR = 'h0000, // AXI read address to generate busy
parameter PORT0_RD_ADDR_MASK = 'h1c00, // AXI read address mask to generate busy
parameter PORT1_WR_ADDR = 'h0400, // AXI read address to generate busy
parameter PORT1_WR_ADDR_MASK = 'h1c00, // AXI read address mask to generate busy
// parameters below to be ORed with CONTROL_ADDR and CONTROL_ADDR_MASK respectively
parameter DLY_LD_REL = 'h080, // address to generate delay load
parameter DLY_LD_REL_MASK = 'h380, // address mask to generate delay load
parameter DLY_SET_REL = 'h070, // address to generate delay set
parameter DLY_SET_REL_MASK = 'h3ff, // address mask to generate delay set
parameter RUN_CHN_REL = 'h000, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
parameter PATTERNS_REL = 'h020, // address to set DQM and DQS patterns (16'h0055)
parameter PATTERNS_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
parameter PATTERNS_TRI_REL = 'h021, // address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter PATTERNS_TRI_REL_MASK = 'h3ff, // address mask to set DQM and DQS tristate patterns
parameter WBUF_DELAY_REL = 'h022, // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
parameter WBUF_DELAY_REL_MASK = 'h3ff, // address mask to set extra delay
parameter PAGES_REL = 'h023, // address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
parameter CMDA_EN_REL = 'h024, // address to enable('h825)/disable('h824) command/address outputs
parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
parameter SDRST_ACT_REL = 'h026, // address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory
parameter SDRST_ACT_REL_MASK = 'h3fe, // address mask for reset DDR3
parameter CKE_EN_REL = 'h028, // address to enable('h829)/disable('h828) CKE signal to memory
parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
parameter DCI_RST_REL = 'h02a, // address to activate('h82b)/deactivate('h82a) Zynq DCI calibrate circuitry
parameter DCI_RST_REL_MASK = 'h3fe, // address mask for DCI calibrate circuitry
parameter DLY_RST_REL = 'h02c, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry
parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry
parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div)
parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters
parameter REFRESH_EN_REL = 'h030, // address to enable('h31) and disable ('h30) DDR refresh
parameter REFRESH_EN_REL_MASK = 'h3fe, // address mask to enable/disable DDR refresh
parameter REFRESH_PER_REL = 'h032, // address to set refresh period in 32 x tCK
parameter REFRESH_PER_REL_MASK = 'h3ff, // address mask set refresh period
parameter REFRESH_ADDR_REL = 'h033, // address to set sequencer start address for DDR refresh
parameter REFRESH_ADDR_REL_MASK = 'h3ff // address mask set refresh sequencer address
)(
// DDR3 interface
output SDRST, // DDR3 reset (active low)
output SDCLK, // DDR3 clock differential output, positive
output SDNCLK,// DDR3 clock differential output, negative
output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
output [2:0] SDBA, // output bank address ports
output SDWE, // output WE port
output SDRAS, // output RAS port
output SDCAS, // output CAS port
output SDCKE, // output Clock Enable port
output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads
output SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad
output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad
inout NDQSU,
output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
input MEMCLK
// ~UDQS I/O pad
// AXI write (ps -> pl)
);
localparam ADDRESS_NUMBER=15;
// Source for reset and clock
wire [3:0] fclk; // PL Clocks [3:0], output
wire [3:0] frst; // PL Clocks [3:0], output
// AXI write interface signals
//(* keep = "true" *)
wire axi_aclk; // clock - should be buffered
// wire axi_naclk; // debugging
// wire axi_aresetn; // reset, active low
//(* dont_touch = "true" *)
wire axi_rst; // reset, active high
// AXI Write Address
wire [31:0] axi_awaddr; // AWADDR[31:0], input
wire axi_awvalid; // AWVALID, input
wire axi_awready; // AWREADY, output
wire [11:0] axi_awid; // AWID[11:0], input
// input [ 1:0] awlock, // AWLOCK[1:0], input
// input [ 3:0] awcache, // AWCACHE[3:0], input
// input [ 2:0] awprot, // AWPROT[2:0], input
wire [ 3:0] axi_awlen; // AWLEN[3:0], input
wire [ 1:0] axi_awsize; // AWSIZE[1:0], input
wire [ 1:0] axi_awburst; // AWBURST[1:0], input
// input [ 3:0] awqos, // AWQOS[3:0], input
// AXI PS Master GP0: Write Data
wire [31:0] axi_wdata; // WDATA[31:0], input
wire axi_wvalid; // WVALID, input
wire axi_wready; // WREADY, output
wire [11:0] axi_wid; // WID[11:0], input
wire axi_wlast; // WLAST, input
wire [ 3:0] axi_wstb; // WSTRB[3:0], input
// AXI PS Master GP0: Write Responce
wire axi_bvalid; // BVALID, output
wire axi_bready; // BREADY, input
wire [11:0] axi_bid; // BID[11:0], output
wire [ 1:0] axi_bresp; // BRESP[1:0], output
// BRAM (and other write modules) interface from AXI write
wire [AXI_WR_ADDR_BITS-1:0] axiwr_pre_awaddr; // same as awaddr_out, early address to decode and return dev_ready
wire axiwr_start_burst; // start of write burst, valid pre_awaddr, save externally to control ext. dev_ready multiplexer
wire axiwr_dev_ready; // extrernal combinatorial ready signal, multiplexed from different sources according to pre_awaddr@start_burst
wire axiwr_bram_wclk;
wire [AXI_WR_ADDR_BITS-1:0] axiwr_bram_waddr;
wire axiwr_bram_wen; // external memory write enable, (internally combined with registered dev_ready
// SuppressWarnings VEditor unused (yet?)
wire [3:0] axiwr_bram_wstb;
wire [31:0] axiwr_bram_wdata;
// AXI Read Address
wire [31:0] axi_araddr; // ARADDR[31:0], input
wire axi_arvalid; // ARVALID, input
wire axi_arready; // ARREADY, output
wire [11:0] axi_arid; // ARID[11:0], input
// input [ 1:0] arlock, // ARLOCK[1:0], input
// input [ 3:0] archache,// ARCACHE[3:0], input
// input [ 2:0] arprot, // ARPROT[2:0], input
wire [ 3:0] axi_arlen; // ARLEN[3:0], input
wire [ 1:0] axi_arsize; // ARSIZE[1:0], input
wire [ 1:0] axi_arburst; // ARBURST[1:0], input
// input [ 3:0] adqos, // ARQOS[3:0], input
// AXI Read Data
wire [31:0] axi_rdata; // RDATA[31:0], output
wire axi_rvalid; // RVALID, output
wire axi_rready; // RREADY, input
wire [11:0] axi_rid; // RID[11:0], output
wire axi_rlast; // RLAST, output
wire [ 1:0] axi_rresp;
// External memory synchronization
wire [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr; // same as awaddr_out, early address to decode and return dev_ready
wire axird_start_burst; // start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer
wire axird_dev_ready; // extrernal combinatorial ready signal, multiplexed from different sources according to pre_araddr@start_burst
// External memory interface
// SuppressWarnings VEditor unused (yet?) - use mclk
wire axird_bram_rclk; // .rclk(aclk), // clock for read port
wire [AXI_RD_ADDR_BITS-1:0] axird_bram_raddr; // .raddr(read_in_progress?read_address[9:0]:10'h3ff), // read address
wire axird_bram_ren; // .ren(bram_reg_re_w) , // read port enable
wire axird_bram_regen; // .regen(bram_reg_re_w), // output register enable
wire [31:0] axird_bram_rdata; // .data_out(rdata[31:0]), // data out
wire [31:0] port0_rdata; //
wire [31:0] status_rdata; //
wire mclk;
wire en_cmd0_wr;
wire [10:0] axi_run_addr;
wire [ 3:0] axi_run_chn;
wire axi_run_seq;
wire [10:0] run_addr; // multiplexed - from refresh or axi
wire [ 3:0] run_chn; // multiplexed - from refresh or axi
wire run_seq;
wire run_seq_rq_in; // higher priority request to run sequence
wire run_seq_rq_gen;// SuppressThisWarning VEditor : unused this wants to run sequencer
// wire run_seq_busy; // sequencer is busy or access granted to other master
// wire run_done; // output
wire run_busy; // TODO: add to ddrc_sequencer
wire [ 7:0] dly_data; // input[7:0]
wire [ 6:0] dly_addr; // input[6:0]
wire ld_delay; // input
wire set; // input
wire locked; // output
wire locked_mmcm;
wire locked_pll;
wire dly_ready;
wire dci_ready;
wire phy_locked_mmcm;
wire phy_locked_pll;
wire phy_dly_ready;
wire phy_dci_ready;
wire [ 7:0] tmp_debug;
wire ps_rdy; // output
wire [ 7:0] ps_out; // output[7:0]
wire en_port0_rd;
wire en_port0_regen;
wire en_port1_wr;
wire [ 1:0] port0_page; // input[1:0]
wire [ 1:0] port0_int_page; // input[1:0]
wire [ 1:0] port1_page; // input[1:0]
wire [ 1:0] port1_int_page;// input[1:0]
// additional control signals
wire cmda_en; // enable DDR3 memory control and addreee outputs
wire ddr_rst; // generate DDR3 memory reset (active hight)
wire dci_rst; // active high - reset DCI circuitry
wire dly_rst; // active high - reset delay calibration circuitry
wire ddr_cke; // control of the DDR3 memory CKE signal
wire inv_clk_div; // input
wire [ 7:0] dqs_pattern; // input[7:0] 8'h55
wire [ 7:0] dqm_pattern; // input[7:0] 8'h00
reg select_port0;
reg select_status;
wire axiwr_dev_busy;
wire axird_dev_busy;
wire [ 3:0] dq_tri_on_pattern;
wire [ 3:0] dq_tri_off_pattern;
wire [ 3:0] dqs_tri_on_pattern;
wire [ 3:0] dqs_tri_off_pattern;
wire [ 3:0] wbuf_delay;
wire port0_rd_match;
reg port0_rd_match_r; // rd address matched in previous cycle
wire [7:0] refresh_period;
wire [10:0] refresh_address;
wire refresh_en;
wire refresh_set;
assign port0_rd_match=(((axird_bram_raddr ^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
assign en_cmd0_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ CMD0_ADDR) & CMD0_ADDR_MASK)==0);
assign en_port0_rd= axird_bram_ren && port0_rd_match;
assign en_port0_regen= axird_bram_regen && port0_rd_match_r;
assign en_port1_wr= axiwr_bram_wen && (((axiwr_bram_waddr ^ PORT1_WR_ADDR) & PORT1_WR_ADDR_MASK)==0);
assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
assign axird_bram_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx);
assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
assign locked=locked_mmcm && locked_pll;
// Clock and reset from PS
wire comb_rst=~frst[0] | frst[1];
reg axi_rst_pre=1'b1;
always @(posedge comb_rst or posedge axi_aclk) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
end
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//BUFG bufg_axi_naclk_i (.O(axi_naclk),.I(~fclk[0]));
always @ (posedge axi_aclk) begin
port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
end
always @ (posedge axi_rst or posedge axi_aclk) begin
if (axi_rst) select_port0 <= 1'b0;
else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
if (axi_rst) select_status <= 1'b0;
else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
end
`ifdef DEBUG_FIFO
wire waddr_under, wdata_under, wresp_under;
wire waddr_over, wdata_over, wresp_over;
reg waddr_under_r, wdata_under_r, wresp_under_r;
reg waddr_over_r, wdata_over_r, wresp_over_r;
wire fifo_rst= frst[2];
wire [3:0] waddr_wcount;
wire [3:0] waddr_rcount;
wire [3:0] waddr_num_in_fifo;
wire [3:0] wdata_wcount;
wire [3:0] wdata_rcount;
wire [3:0] wdata_num_in_fifo;
wire [3:0] wresp_wcount;
wire [3:0] wresp_rcount;
wire [3:0] wresp_num_in_fifo;
wire [3:0] wleft;
wire [3:0] wlength; // output[3:0]
wire [3:0] wlen_in_dbg; // output[3:0] reg
always @(posedge fifo_rst or posedge axi_aclk) begin
if (fifo_rst) {waddr_under_r, wdata_under_r, wresp_under_r,waddr_over_r, wdata_over_r, wresp_over_r} <= 0;
else {waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} <=
{waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} |
{waddr_under, wdata_under, wresp_under, waddr_over, wdata_over, wresp_over};
end
`endif
/*
dly_addr[1],
dly_addr[0],
clkin_stopped_mmcm,
clkfb_stopped_mmcm,
ddr_rst,
rst_in,
dci_rst,
dly_rst
*/
//MEMCLK
wire [63:0] gpio_in;
assign gpio_in={
frst[3]?{
16'b0,
1'b1, // 1
MEMCLK, // 1/0? - external clock
1'b0, //
1'b0, //
frst[1], // 0 (follows)
fclk[1:0], // 2'bXX (toggle)
axird_dev_busy, // 0
4'b0, // 4'b0
4'b0, // 4'b0
tmp_debug[7:4], // 4'b0111 -> 4'bx00x
// dly_addr[1], 0
// dly_addr[0], 0
// clkin_stopped_mmcm, 0
// clkfb_stopped_mmcm, 0
tmp_debug[3:0], // 4'b1100 -> 4'bxx00
// ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
// rst_in, 0 0
// dci_rst, 0 1
// dly_rst 0 1
phy_locked_mmcm, // 1 1
phy_locked_pll, // 1 1
phy_dci_ready, // 1 0
phy_dly_ready, // 1 0
locked_mmcm, // 1 1
locked_pll, // 1 1
dci_ready, // 1 0
dly_ready // 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
wdata_wcount[3:0],
wdata_rcount[3:0],
wdata_num_in_fifo[3:0],
wresp_wcount[3:0],
wresp_rcount[3:0],
wresp_num_in_fifo[3:0],
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
//ps_out[7:4], // 4'b0 input[7:0] 4'b0
//ps_out[3:0], // 4'b0 input[7:0] 4'b0
1'b0,
waddr_under_r,
wdata_under_r,
wresp_under_r,
1'b0,
waddr_over_r,
wdata_over_r,
wresp_over_r, // ???
run_busy, // input // 0
locked, // input // 1
ps_rdy, // input // 1
axi_arready, // 1
axi_awready, // 1
axi_wready, // 1 - sometimes gets stuck with 0 (axi_awready==1) ? TODO: Add timeout
fifo_rst, // fclk[0], // 0/1
axi_rst_pre //axi_rst // 0
};
assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0];
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input
.rst (axi_rst), // input
.awaddr (axi_awaddr[31:0]), // input[31:0]
.awvalid (axi_awvalid), // input
.awready (axi_awready), // output
.awid (axi_awid[11:0]), // input[11:0]
.awlen (axi_awlen[3:0]), // input[3:0]
.awsize (axi_awsize[1:0]), // input[1:0]
.awburst (axi_awburst[1:0]), // input[1:0]
.wdata (axi_wdata[31:0]), // input[31:0]
.wvalid (axi_wvalid), // input
.wready (axi_wready), // output
.wid (axi_wid[11:0]), // input[11:0]
.wlast (axi_wlast), // input
.wstb (axi_wstb[3:0]), // input[3:0]
.bvalid (axi_bvalid), // output
.bready (axi_bready), // input
.bid (axi_bid[11:0]), // output[11:0]
.bresp (axi_bresp[1:0]), // output[1:0]
.pre_awaddr (axiwr_pre_awaddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.start_burst (axiwr_start_burst), // output
.dev_ready (axiwr_dev_ready), // input
.bram_wclk (axiwr_bram_wclk), // output
.bram_waddr (axiwr_bram_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.bram_wen (axiwr_bram_wen), // output
.bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used
.bram_wdata (axiwr_bram_wdata[31:0]) // output[31:0]
`ifdef DEBUG_FIFO
,
.waddr_under (waddr_under), // output
.wdata_under (wdata_under), // output
.wresp_under (wresp_under), // output
.waddr_over (waddr_over), // output
.wdata_over (wdata_over), // output
.wresp_over (wresp_over), // output
.waddr_wcount(waddr_wcount), // output[3:0]
.waddr_rcount(waddr_rcount), // output[3:0]
.waddr_num_in_fifo(waddr_num_in_fifo), // output[3:0]
.wdata_wcount(wdata_wcount), // output[3:0]
.wdata_rcount(wdata_rcount), // output[3:0]
.wdata_num_in_fifo(wdata_num_in_fifo), // output[3:0]
.wresp_wcount(wresp_wcount), // output[3:0]
.wresp_rcount(wresp_rcount), // output[3:0]
.wresp_num_in_fifo(wresp_num_in_fifo), // output[3:0]
.wleft (wleft[3:0]),
.wlength (wlength[3:0]), // output[3:0]
.wlen_in_dbg (wlen_in_dbg[3:0]) // output[3:0] reg
`endif
);
/* Instance template for module axibram_read */
axibram_read #(
.ADDRESS_BITS(AXI_RD_ADDR_BITS)
) axibram_read_i ( //SuppressThisWarning ISExst Output port <bram_rclk> of the instance <axibram_read_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input
.rst (axi_rst), // input
.araddr (axi_araddr[31:0]), // input[31:0]
.arvalid (axi_arvalid), // input
.arready (axi_arready), // output
.arid (axi_arid[11:0]), // input[11:0]
.arlen (axi_arlen[3:0]), // input[3:0]
.arsize (axi_arsize[1:0]), // input[1:0]
.arburst (axi_arburst[1:0]), // input[1:0]
.rdata (axi_rdata[31:0]), // output[31:0]
.rvalid (axi_rvalid), // output reg
.rready (axi_rready), // input
.rid (axi_rid), // output[11:0] reg
.rlast (axi_rlast), // output reg
.rresp (axi_rresp[1:0]), // output[1:0]
.pre_araddr (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0]
.start_burst (axird_start_burst), // output
.dev_ready (axird_dev_ready), // input
.bram_rclk (axird_bram_rclk), // output //SuppressThisWarning ISExst Assignment to axird_bram_rclk ignored, since the identifier is never used
.bram_raddr (axird_bram_raddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0]
.bram_ren (axird_bram_ren), // output
.bram_regen (axird_bram_regen), // output
.bram_rdata (axird_bram_rdata) // input[31:0]
);
ddrc_control #(
.AXI_WR_ADDR_BITS (AXI_WR_ADDR_BITS),
.CONTROL_ADDR (CONTROL_ADDR),
.CONTROL_ADDR_MASK (CONTROL_ADDR_MASK),
// .STATUS_ADDR (STATUS_ADDR),
// .STATUS_ADDR_MASK (STATUS_ADDR_MASK),
.BUSY_WR_ADDR (BUSY_WR_ADDR),
.BUSY_WR_ADDR_MASK (BUSY_WR_ADDR_MASK),
.DLY_LD_REL (DLY_LD_REL),
.DLY_LD_REL_MASK (DLY_LD_REL_MASK),
.DLY_SET_REL (DLY_SET_REL),
.DLY_SET_REL_MASK (DLY_SET_REL_MASK),
.RUN_CHN_REL (RUN_CHN_REL),
.RUN_CHN_REL_MASK (RUN_CHN_REL_MASK),
.PATTERNS_REL (PATTERNS_REL),
.PATTERNS_REL_MASK (PATTERNS_REL_MASK),
.PATTERNS_TRI_REL (PATTERNS_TRI_REL),
.PATTERNS_TRI_REL_MASK (PATTERNS_TRI_REL_MASK),
.WBUF_DELAY_REL (WBUF_DELAY_REL),
.WBUF_DELAY_REL_MASK (WBUF_DELAY_REL_MASK),
.PAGES_REL (PAGES_REL),
.PAGES_REL_MASK (PAGES_REL_MASK),
.CMDA_EN_REL (CMDA_EN_REL),
.CMDA_EN_REL_MASK (CMDA_EN_REL_MASK),
.SDRST_ACT_REL (SDRST_ACT_REL),
.SDRST_ACT_REL_MASK (SDRST_ACT_REL_MASK),
.CKE_EN_REL (CKE_EN_REL),
.CKE_EN_REL_MASK (CKE_EN_REL_MASK),
.DCI_RST_REL (DCI_RST_REL),
.DCI_RST_REL_MASK (DCI_RST_REL_MASK),
.DLY_RST_REL (DLY_RST_REL),
.DLY_RST_REL_MASK (DLY_RST_REL_MASK),
.EXTRA_REL (EXTRA_REL),
.EXTRA_REL_MASK (EXTRA_REL_MASK),
.REFRESH_EN_REL (REFRESH_EN_REL),
.REFRESH_EN_REL_MASK (REFRESH_EN_REL_MASK),
.REFRESH_PER_REL (REFRESH_PER_REL),
.REFRESH_PER_REL_MASK (REFRESH_PER_REL_MASK),
.REFRESH_ADDR_REL (REFRESH_ADDR_REL),
.REFRESH_ADDR_REL_MASK (REFRESH_ADDR_REL_MASK)
) ddrc_control_i (
.clk (axiwr_bram_wclk), // same as axi_aclk
.mclk (mclk), // input
.rst (axi_rst), // input
.pre_waddr (axiwr_pre_awaddr[AXI_WR_ADDR_BITS-1:0]), // input[11:0]
.start_wburst (axiwr_start_burst), // input
.waddr (axiwr_bram_waddr[AXI_WR_ADDR_BITS-1:0]), // input[11:0]
.wr_en (axiwr_bram_wen), // input
.wdata (axiwr_bram_wdata[31:0]), // input[31:0] (no input for wstb here)
.busy (axiwr_dev_busy), // output
.run_addr (axi_run_addr[10:0]), // output[10:0]
.run_chn (axi_run_chn[3:0]), // output[3:0]
.run_seq (axi_run_seq), // output
.run_seq_rq_in (run_seq_rq_in), // input
.run_seq_rq_gen (run_seq_rq_gen), // output
.run_seq_busy (run_busy), // input
.refresh_address (refresh_address[10:0]), // output[10:0]
.refresh_period (refresh_period[7:0]), // output[7:0]
.refresh_set (refresh_set), // output
.refresh_en (refresh_en), // output
.dly_data (dly_data[7:0]), // output[7:0]
.dly_addr (dly_addr[6:0]), // output[6:0]
.ld_delay (ld_delay), // output
.dly_set (set), // output
.cmda_en (cmda_en), // output
.ddr_rst (ddr_rst), // output
.dci_rst (dci_rst), // output
.dly_rst (dly_rst), // output
.ddr_cke (ddr_cke), // output
.inv_clk_div (inv_clk_div), // output
.dqs_pattern (dqs_pattern[7:0]), // output[7:0]
.dqm_pattern (dqm_pattern[7:0]), // output[7:0]
.dq_tri_on_pattern (dq_tri_on_pattern[3:0]), // output[3:0]
.dq_tri_off_pattern (dq_tri_off_pattern[3:0]), // output[3:0]
.dqs_tri_on_pattern (dqs_tri_on_pattern[3:0]), // output[3:0]
.dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]),// output[3:0]
.wbuf_delay (wbuf_delay[3:0]), // output[3:0]
.port0_page (port0_page[1:0]), // output[1:0]
.port0_int_page (port0_int_page[1:0]), // output[1:0]
.port1_page (port1_page[1:0]), // output[1:0]
.port1_int_page (port1_int_page[1:0]) // output[1:0]
);
assign run_addr = axi_run_seq ? axi_run_addr[10:0] : refresh_address[10:0];
assign run_chn = axi_run_seq ? axi_run_chn[3:0] : 4'h0;
assign run_seq = axi_run_seq || refresh_grant;
/*
wire run_seq_rq_in; // higher priority request to run sequence
wire run_seq_rq_gen;// SuppressThisWarning VEditor : unused this wants to run sequencer
// wire run_seq_busy; // sequencer is busy or access granted to other master
run_busy
wire [10:0] refresh_address;
*/
// assign run_seq_rq_in = 1'b0; // higher priority request input
wire refresh_want;
wire refresh_need;
reg refresh_grant;
assign run_seq_rq_in = refresh_en && refresh_need; // higher priority request input
ddr_refresh ddr_refresh_i (
.rst (axi_rst), // input
.clk (mclk), // input
.refresh_period (refresh_period[7:0]), // input[7:0]
.set (refresh_set), // input
.want (refresh_want), // output
.need (refresh_need), // output
.grant (refresh_grant) // input
);
always @(posedge axi_rst or posedge mclk) begin
if (axi_rst) refresh_grant <= 0;
else refresh_grant <= !refresh_grant && refresh_en && !run_busy && !axi_run_seq && (refresh_need || (refresh_want && !run_seq_rq_gen));
end
ddrc_status
// #(
// .AXI_RD_ADDR_BITS (AXI_RD_ADDR_BITS),
// .SELECT_ADDR (SELECT_RD_ADDR),
// .SELECT_ADDR_MASK (SELECT_RD_ADDR_MASK),
// .BUSY_ADDR (BUSY_RD_ADDR),
// .BUSY_ADDR_MASK (BUSY_RD_ADDR_MASK)
// )
ddrc_status_i (
// .clk (axi_aclk), // input
// .mclk (mclk), // input
// .rst (axi_rst), // input
// .pre_raddr (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // input[11:0]
// .start_rburst (axird_start_burst), // input
// .raddr (axird_bram_raddr[AXI_RD_ADDR_BITS-1:0]), // input[11:0]
// .rd_en (axird_bram_regen), // input
.rdata (status_rdata[31:0]), // output[31:0]
.busy (axird_dev_busy), // output
// .run_done (run_done), // input
.run_busy (run_busy), // input
.locked (locked), // input
.locked_mmcm (locked_mmcm), // input
.locked_pll (locked_pll), // input
.dly_ready (dly_ready), // input
.dci_ready (dci_ready), // input
.ps_rdy (ps_rdy), // input
.ps_out (ps_out[7:0]) // input[7:0]
);
ddrc_sequencer #(
.PHASE_WIDTH (PHASE_WIDTH),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
.SLEW_CMDA (SLEW_CMDA),
.SLEW_CLK (SLEW_CLK),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
.REF_JITTER1 (REF_JITTER1),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) ddrc_sequencer_i ( //SuppressThisWarning ISExst Output port <run_done> of the instance <ddrc_sequencer_i> is unconnected or connected to loadless signal.
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
.SDA (SDA[14:0]), // output[14:0] // BUG with localparam - fixed
.SDBA (SDBA[2:0]), // output[2:0]
.SDWE (SDWE), // output
.SDRAS (SDRAS), // output
.SDCAS (SDCAS), // output
.SDCKE (SDCKE), // output
.SDODT (SDODT), // output
.SDD (SDD[15:0]), // inout[15:0]
.SDDML (SDDML), // inout
.DQSL (DQSL), // inout
.NDQSL (NDQSL), // inout
.SDDMU (SDDMU), // inout
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.clk_in (axi_aclk), // input
.rst_in (axi_rst), // input
.mclk (mclk), // output
.cmd0_clk (axi_aclk), // input
.cmd0_we (en_cmd0_wr), // input
.cmd0_addr (axiwr_bram_waddr[9:0]), // input[9:0]
.cmd0_data (axiwr_bram_wdata[31:0]), // input[31:0]
.cmd1_clk (mclk), // input
// TODO: add - from PL generation of the command sequences
.cmd1_we (1'b0), // input
.cmd1_addr (10'b0), // input[9:0]
.cmd1_data (32'b0), // input[31:0]
.run_addr (run_addr[10:0]), // input[10:0]
.run_chn (run_chn[3:0]), // input[3:0]
.run_seq (run_seq), // input #################### DISABLED ####################
// .run_seq (1'b0 && run_seq), // input #################### DISABLED ####################
// .run_done (run_done), // output
.run_done (), // output
.run_busy (run_busy), // output
.dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0]
.ld_delay (ld_delay), // input
.set (set), // input
// .locked (locked), // output
.locked_mmcm (locked_mmcm), // output
.locked_pll (locked_pll), // output
.dly_ready (dly_ready), // output
.dci_ready (dci_ready), // output
.phy_locked_mmcm (phy_locked_mmcm), // output
.phy_locked_pll (phy_locked_pll), // output
.phy_dly_ready (phy_dly_ready), // output
.phy_dci_ready (phy_dci_ready), // output
.tmp_debug (tmp_debug[7:0]),
.ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]), // output[7:0]
.port0_clk (axi_aclk), // input
.port0_re (en_port0_rd), // input
.port0_regen (en_port0_regen), // input
.port0_page (port0_page[1:0]), // input[1:0]
.port0_int_page (port0_int_page[1:0]), // input[1:0]
.port0_addr (axird_bram_raddr[7:0]), // input[7:0]
.port0_data (port0_rdata[31:0]), // output[31:0]
.port1_clk (axi_aclk), // input
.port1_we (en_port1_wr), // input
.port1_page (port1_page[1:0]), // input[1:0]
.port1_int_page (port1_int_page[1:0]), // input[1:0]
.port1_addr (axiwr_bram_waddr[7:0]), // input[7:0]
.port1_data (axiwr_bram_wdata[31:0]), // input[31:0]
.cmda_en (cmda_en), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
.dly_rst (dly_rst), // input
.ddr_cke (ddr_cke), // input
.inv_clk_div (inv_clk_div), // input
.dqs_pattern (dqs_pattern), // input[7:0]
.dqm_pattern (dqm_pattern), // input[7:0]
.dq_tri_on_pattern (dq_tri_on_pattern[3:0]), // input[3:0]
.dq_tri_off_pattern (dq_tri_off_pattern[3:0]), // input[3:0]
.dqs_tri_on_pattern (dqs_tri_on_pattern[3:0]), // input[3:0]
.dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]),// input[3:0]
.wbuf_delay (wbuf_delay[3:0]) // input[3:0]
);
PS7 ps7_i (
// EMIO interface
// CAN interface
.EMIOCAN0PHYTX(), // CAN 0 TX, output
.EMIOCAN0PHYRX(), // CAN 0 RX, input
.EMIOCAN1PHYTX(), // Can 1 TX, output
.EMIOCAN1PHYRX(), // CAN 1 RX, input
// GMII 0
.EMIOENET0GMIICRS(), // GMII 0 Carrier sense, input
.EMIOENET0GMIICOL(), // GMII 0 Collision detect, input
.EMIOENET0EXTINTIN(), // GMII 0 Controller Interrupt input, input
// GMII 0 TX signals
.EMIOENET0GMIITXCLK(), // GMII 0 TX clock, input
.EMIOENET0GMIITXD(), // GMII 0 Tx Data[7:0], output
.EMIOENET0GMIITXEN(), // GMII 0 Tx En, output
.EMIOENET0GMIITXER(), // GMII 0 Tx Err, output
// GMII 0 TX timestamp signals
.EMIOENET0SOFTX(), // GMII 0 Tx Tx Start-of-Frame, output
.EMIOENET0PTPDELAYREQTX(), // GMII 0 Tx PTP delay req frame detected, output
.EMIOENET0PTPPDELAYREQTX(), // GMII 0 Tx PTP peer delay frame detect, output
.EMIOENET0PTPPDELAYRESPTX(), // GMII 0 Tx PTP pear delay response frame detected, output
.EMIOENET0PTPSYNCFRAMETX(), // GMII 0 Tx PTP sync frame detected, output
// GMII 0 RX signals
.EMIOENET0GMIIRXCLK(), // GMII 0 Rx Clock, input
.EMIOENET0GMIIRXD(), // GMII 0 Rx Data (7:0), input
.EMIOENET0GMIIRXDV(), // GMII 0 Rx Data valid, input
.EMIOENET0GMIIRXER(), // GMII 0 Rx Error, input
// GMII 0 RX timestamp signals
.EMIOENET0SOFRX(), // GMII 0 Rx Start of Frame, output
.EMIOENET0PTPDELAYREQRX(), // GMII 0 Rx PTP delay req frame detected
.EMIOENET0PTPPDELAYREQRX(), // GMII 0 Rx PTP peer delay frame detected, output
.EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay responce frame detected, output
.EMIOENET0PTPSYNCFRAMERX(), // GMII 0 Rx PTP sync frame detected, output
// MDIO 0
.EMIOENET0MDIOMDC(), // MDIO 0 MD clock output, output
.EMIOENET0MDIOO(), // MDIO 0 MD data output, output
.EMIOENET0MDIOTN(), // MDIO 0 MD data 3-state, output
.EMIOENET0MDIOI(), // MDIO 0 MD data input, input
// GMII 1
.EMIOENET1GMIICRS(), // GMII 1 Carrier sense, input
.EMIOENET1GMIICOL(), // GMII 1 Collision detect, input
.EMIOENET1EXTINTIN(), // GMII 1 Controller Interrupt input, input
// GMII 1 TX signals
.EMIOENET1GMIITXCLK(), // GMII 1 TX clock, input
.EMIOENET1GMIITXD(), // GMII 1 Tx Data[7:0], output
.EMIOENET1GMIITXEN(), // GMII 1 Tx En, output
.EMIOENET1GMIITXER(), // GMII 1 Tx Err, output
// GMII 1 TX timestamp signals
.EMIOENET1SOFTX(), // GMII 1 Tx Tx Start-of-Frame, output
.EMIOENET1PTPDELAYREQTX(), // GMII 1 Tx PTP delay req frame detected, output
.EMIOENET1PTPPDELAYREQTX(), // GMII 1 Tx PTP peer delay frame detect, output
.EMIOENET1PTPPDELAYRESPTX(), // GMII 1 Tx PTP pear delay response frame detected, output
.EMIOENET1PTPSYNCFRAMETX(), // GMII 1 Tx PTP sync frame detected, output
// GMII 1 RX signals
.EMIOENET1GMIIRXCLK(), // GMII 1 Rx Clock, input
.EMIOENET1GMIIRXD(), // GMII 1 Rx Data (7:0), input
.EMIOENET1GMIIRXDV(), // GMII 1 Rx Data valid, input
.EMIOENET1GMIIRXER(), // GMII 1 Rx Error, input
// GMII 1 RX timestamp signals
.EMIOENET1SOFRX(), // GMII 1 Rx Start of Frame, output
.EMIOENET1PTPDELAYREQRX(), // GMII 1 Rx PTP delay req frame detected
.EMIOENET1PTPPDELAYREQRX(), // GMII 1 Rx PTP peer delay frame detected, output
.EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay responce frame detected, output
.EMIOENET1PTPSYNCFRAMERX(), // GMII 1 Rx PTP sync frame detected, output
// MDIO 1
.EMIOENET1MDIOMDC(), // MDIO 1 MD clock output, output
.EMIOENET1MDIOO(), // MDIO 1 MD data output, output
.EMIOENET1MDIOTN(), // MDIO 1 MD data 3-state, output
.EMIOENET1MDIOI(), // MDIO 1 MD data input, input
// EMIO GPIO
.EMIOGPIOO(), // EMIO GPIO Data out[63:0], output
.EMIOGPIOI(gpio_in[63:0]), // EMIO GPIO Data in[63:0], input
.EMIOGPIOTN(), // EMIO GPIO OutputEnable[63:0], output
// EMIO I2C 0
.EMIOI2C0SCLO(), // I2C 0 SCL OUT, output // manual says input
.EMIOI2C0SCLI(), // I2C 0 SCL IN, input // manual says output
.EMIOI2C0SCLTN(), // I2C 0 SCL EN, output // manual says input
.EMIOI2C0SDAO(), // I2C 0 SDA OUT, output // manual says input
.EMIOI2C0SDAI(), // I2C 0 SDA IN, input // manual says output
.EMIOI2C0SDATN(), // I2C 0 SDA EN, output // manual says input
// EMIO I2C 1
.EMIOI2C1SCLO(), // I2C 1 SCL OUT, output // manual says input
.EMIOI2C1SCLI(), // I2C 1 SCL IN, input // manual says output
.EMIOI2C1SCLTN(), // I2C 1 SCL EN, output // manual says input
.EMIOI2C1SDAO(), // I2C 1 SDA OUT, output // manual says input
.EMIOI2C1SDAI(), // I2C 1 SDA IN, input // manual says output
.EMIOI2C1SDATN(), // I2C 1 SDA EN, output // manual says input
// JTAG
.EMIOPJTAGTCK(), // JTAG TCK, input
.EMIOPJTAGTMS(), // JTAG TMS, input
.EMIOPJTAGTDI(), // JTAG TDI, input
.EMIOPJTAGTDO(), // JTAG TDO, output
.EMIOPJTAGTDTN(), // JTAG TDO OE, output
// SDIO 0
.EMIOSDIO0CLKFB(), // SDIO 0 Clock feedback, input
.EMIOSDIO0CLK(), // SDIO 0 Clock, output
.EMIOSDIO0CMDI(), // SDIO 0 Command in, input
.EMIOSDIO0CMDO(), // SDIO 0 Command out, output
.EMIOSDIO0CMDTN(), // SDIO 0 command OE, output
.EMIOSDIO0DATAI(), // SDIO 0 Data in [3:0], input
.EMIOSDIO0DATAO(), // SDIO 0 Data out [3:0], output
.EMIOSDIO0DATATN(), // SDIO 0 Data OE [3:0], output
.EMIOSDIO0CDN(), // SDIO 0 Card detect, input
.EMIOSDIO0WP(), // SDIO 0 Write protect, input
.EMIOSDIO0BUSPOW(), // SDIO 0 Power control, output
.EMIOSDIO0LED(), // SDIO 0 LED control, output
.EMIOSDIO0BUSVOLT(), // SDIO 0 Bus voltage [2:0], output
// SDIO 1
.EMIOSDIO1CLKFB(), // SDIO 1 Clock feedback, input
.EMIOSDIO1CLK(), // SDIO 1 Clock, output
.EMIOSDIO1CMDI(), // SDIO 1 Command in, input
.EMIOSDIO1CMDO(), // SDIO 1 Command out, output
.EMIOSDIO1CMDTN(), // SDIO 1 command OE, output
.EMIOSDIO1DATAI(), // SDIO 1 Data in [3:0], input
.EMIOSDIO1DATAO(), // SDIO 1 Data out [3:0], output
.EMIOSDIO1DATATN(), // SDIO 1 Data OE [3:0], output
.EMIOSDIO1CDN(), // SDIO 1 Card detect, input
.EMIOSDIO1WP(), // SDIO 1 Write protect, input
.EMIOSDIO1BUSPOW(), // SDIO 1 Power control, output
.EMIOSDIO1LED(), // SDIO 1 LED control, output
.EMIOSDIO1BUSVOLT(), // SDIO 1 Bus voltage [2:0], output
// SPI 0
.EMIOSPI0SCLKI(), // SPI 0 CLK in , input
.EMIOSPI0SCLKO(), // SPI 0 CLK out, output
.EMIOSPI0SCLKTN(), // SPI 0 CLK OE, output
.EMIOSPI0SI(), // SPI 0 MOSI in , input
.EMIOSPI0MO(), // SPI 0 MOSI out , output
.EMIOSPI0MOTN(), // SPI 0 MOSI OE, output
.EMIOSPI0MI(), // SPI 0 MISO in, input
.EMIOSPI0SO(), // SPI 0 MISO out, output
.EMIOSPI0STN(), // SPI 0 MISO OE, output
.EMIOSPI0SSIN(), // SPI 0 Slave select 0 in, input
.EMIOSPI0SSON(), // SPI 0 Slave select [2:0] out, output
.EMIOSPI0SSNTN(), // SPI 0 Slave select OE, output
// SPI 1
.EMIOSPI1SCLKI(), // SPI 1 CLK in , input
.EMIOSPI1SCLKO(), // SPI 1 CLK out, output
.EMIOSPI1SCLKTN(), // SPI 1 CLK OE, output
.EMIOSPI1SI(), // SPI 1 MOSI in , input
.EMIOSPI1MO(), // SPI 1 MOSI out , output
.EMIOSPI1MOTN(), // SPI 1 MOSI OE, output
.EMIOSPI1MI(), // SPI 1 MISO in, input
.EMIOSPI1SO(), // SPI 1 MISO out, output
.EMIOSPI1STN(), // SPI 1 MISO OE, output
.EMIOSPI1SSIN(), // SPI 1 Slave select 0 in, input
.EMIOSPI1SSON(), // SPI 1 Slave select [2:0] out, output
.EMIOSPI1SSNTN(), // SPI 1 Slave select OE, output
// TPIU signals (Trace)
.EMIOTRACECTL(), // Trace CTL, output
.EMIOTRACEDATA(), // Trace Data[31:0], output
.EMIOTRACECLK(), // Trace CLK, input
// Timers/counters
.EMIOTTC0CLKI(), // Counter/Timer 0 clock in [2:0], input
.EMIOTTC0WAVEO(), // Counter/Timer 0 wave out[2:0], output
.EMIOTTC1CLKI(), // Counter/Timer 1 clock in [2:0], input
.EMIOTTC1WAVEO(), // Counter/Timer 1 wave out[2:0], output
//UART 0
.EMIOUART0TX(), // UART 0 Transmit, output
.EMIOUART0RX(), // UART 0 Receive, input
.EMIOUART0CTSN(), // UART 0 Clear To Send, input
.EMIOUART0RTSN(), // UART 0 Ready to Send, output
.EMIOUART0DSRN(), // UART 0 Data Set Ready , input
.EMIOUART0DCDN(), // UART 0 Data Carrier Detect, input
.EMIOUART0RIN(), // UART 0 Ring Indicator, input
.EMIOUART0DTRN(), // UART 0 Data Terminal Ready, output
//UART 1
.EMIOUART1TX(), // UART 1 Transmit, output
.EMIOUART1RX(), // UART 1 Receive, input
.EMIOUART1CTSN(), // UART 1 Clear To Send, input
.EMIOUART1RTSN(), // UART 1 Ready to Send, output
.EMIOUART1DSRN(), // UART 1 Data Set Ready , input
.EMIOUART1DCDN(), // UART 1 Data Carrier Detect, input
.EMIOUART1RIN(), // UART 1 Ring Indicator, input
.EMIOUART1DTRN(), // UART 1 Data Terminal Ready, output
// USB 0
.EMIOUSB0PORTINDCTL(), // USB 0 Port Indicator [1:0], output
.EMIOUSB0VBUSPWRFAULT(), // USB 0 Power Fault, input
.EMIOUSB0VBUSPWRSELECT(), // USB 0 Power Select, output
// USB 1
.EMIOUSB1PORTINDCTL(), // USB 1 Port Indicator [1:0], output
.EMIOUSB1VBUSPWRFAULT(), // USB 1 Power Fault, input
.EMIOUSB1VBUSPWRSELECT(), // USB 1 Power Select, output
// Watchdog Timer
.EMIOWDTCLKI(), // Watchdog Timer Clock in, input
.EMIOWDTRSTO(), // Watchdog Timer Reset out, output
// DMAC 0
.DMA0ACLK(), // DMAC 0 Clock, input
.DMA0DRVALID(), // DMAC 0 DMA Request Valid, input
.DMA0DRLAST(), // DMAC 0 DMA Request Last, input
.DMA0DRTYPE(), // DMAC 0 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA0DRREADY(), // DMAC 0 DMA Request Ready, output
.DMA0DAVALID(), // DMAC 0 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA0DAREADY(), // DMAC 0 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA0DATYPE(), // DMAC 0 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA0RSTN(), // DMAC 0 RESET output (reserved, do not use), output
// DMAC 1
.DMA1ACLK(), // DMAC 1 Clock, input
.DMA1DRVALID(), // DMAC 1 DMA Request Valid, input
.DMA1DRLAST(), // DMAC 1 DMA Request Last, input
.DMA1DRTYPE(), // DMAC 1 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA1DRREADY(), // DMAC 1 DMA Request Ready, output
.DMA1DAVALID(), // DMAC 1 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA1DAREADY(), // DMAC 1 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA1DATYPE(), // DMAC 1 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA1RSTN(), // DMAC 1 RESET output (reserved, do not use), output
// DMAC 2
.DMA2ACLK(), // DMAC 2 Clock, input
.DMA2DRVALID(), // DMAC 2 DMA Request Valid, input
.DMA2DRLAST(), // DMAC 2 DMA Request Last, input
.DMA2DRTYPE(), // DMAC 2 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA2DRREADY(), // DMAC 2 DMA Request Ready, output
.DMA2DAVALID(), // DMAC 2 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA2DAREADY(), // DMAC 2 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA2DATYPE(), // DMAC 2 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA2RSTN(), // DMAC 2 RESET output (reserved, do not use), output
// DMAC 3
.DMA3ACLK(), // DMAC 3 Clock, input
.DMA3DRVALID(), // DMAC 3 DMA Request Valid, input
.DMA3DRLAST(), // DMAC 3 DMA Request Last, input
.DMA3DRTYPE(), // DMAC 3 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA3DRREADY(), // DMAC 3 DMA Request Ready, output
.DMA3DAVALID(), // DMAC 3 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA3DAREADY(), // DMAC 3 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
// Interrupt signals
.IRQF2P(), // Interrupts, OL to PS [19:0], input
.IRQP2F(), // Interrupts, OL to PS [28:0], output
// Event Signals
.EVENTEVENTI(), // EVENT Wake up one or both CPU from WFE state, input
.EVENTEVENTO(), // EVENT Asserted when one of the COUs executed SEV instruction, output
.EVENTSTANDBYWFE(), // EVENT CPU standby mode [1:0], asserted when CPU is waiting for an event, output
.EVENTSTANDBYWFI(), // EVENT CPU standby mode [1:0], asserted when CPU is waiting for an interrupt, output
// PL Resets and clocks
.FCLKCLK(fclk[3:0]), // PL Clocks [3:0], output
.FCLKCLKTRIGN(), // PL Clock Throttle Control [3:0], input
.FCLKRESETN(frst[3:0]), // PL General purpose user reset [3:0], output (active low)
// Debug signals
.FTMTP2FDEBUG(), // Debug General purpose debug output [31:0], output
.FTMTF2PDEBUG(), // Debug General purpose debug input [31:0], input
.FTMTP2FTRIG(), // Debug Trigger PS to PL [3:0], output
.FTMTP2FTRIGACK(), // Debug Trigger PS to PL acknowledge[3:0], input
.FTMTF2PTRIG(), // Debug Trigger PL to PS [3:0], input
.FTMTF2PTRIGACK(), // Debug Trigger PL to PS acknowledge[3:0], output
.FTMDTRACEINCLOCK(), // Debug Trace PL to PS Clock, input
.FTMDTRACEINVALID(), // Debug Trace PL to PS Clock, data&id valid, input
.FTMDTRACEINDATA(), // Debug Trace PL to PS data [31:0], input
.FTMDTRACEINATID(), // Debug Trace PL to PS ID [3:0], input
// DDR Urgent
.DDRARB(), // DDR Urgent[3:0], input
// SRAM interrupt (on rising edge)
.EMIOSRAMINTIN(), // SRAM interrupt #50 shared with NAND busy, input
// AXI interfaces
.FPGAIDLEN(1'b1), //Idle PL AXI interfaces (active low), input
// AXI PS Master GP0
// AXI PS Master GP0: Clock, Reset
.MAXIGP0ACLK(axi_aclk), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(fclk[0]), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(~fclk[0]), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(axi_naclk), // AXI PS Master GP0 Clock , input
//
.MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output
// AXI PS Master GP0: Read Address
.MAXIGP0ARADDR (axi_araddr[31:0]), // AXI PS Master GP0 ARADDR[31:0], output
.MAXIGP0ARVALID (axi_arvalid), // AXI PS Master GP0 ARVALID, output
.MAXIGP0ARREADY (axi_arready), // AXI PS Master GP0 ARREADY, input
.MAXIGP0ARID (axi_arid[11:0]), // AXI PS Master GP0 ARID[11:0], output
.MAXIGP0ARLOCK (), // AXI PS Master GP0 ARLOCK[1:0], output
.MAXIGP0ARCACHE (),// AXI PS Master GP0 ARCACHE[3:0], output
.MAXIGP0ARPROT(), // AXI PS Master GP0 ARPROT[2:0], output
.MAXIGP0ARLEN (axi_arlen[3:0]), // AXI PS Master GP0 ARLEN[3:0], output
.MAXIGP0ARSIZE (axi_arsize[1:0]), // AXI PS Master GP0 ARSIZE[1:0], output
.MAXIGP0ARBURST (axi_arburst[1:0]),// AXI PS Master GP0 ARBURST[1:0], output
.MAXIGP0ARQOS (), // AXI PS Master GP0 ARQOS[3:0], output
// AXI PS Master GP0: Read Data
.MAXIGP0RDATA (axi_rdata[31:0]), // AXI PS Master GP0 RDATA[31:0], input
.MAXIGP0RVALID (axi_rvalid), // AXI PS Master GP0 RVALID, input
.MAXIGP0RREADY (axi_rready), // AXI PS Master GP0 RREADY, output
.MAXIGP0RID (axi_rid[11:0]), // AXI PS Master GP0 RID[11:0], input
.MAXIGP0RLAST (axi_rlast), // AXI PS Master GP0 RLAST, input
.MAXIGP0RRESP (axi_rresp[1:0]), // AXI PS Master GP0 RRESP[1:0], input
// AXI PS Master GP0: Write Address
.MAXIGP0AWADDR (axi_awaddr[31:0]), // AXI PS Master GP0 AWADDR[31:0], output
.MAXIGP0AWVALID (axi_awvalid), // AXI PS Master GP0 AWVALID, output
.MAXIGP0AWREADY (axi_awready), // AXI PS Master GP0 AWREADY, input
.MAXIGP0AWID (axi_awid[11:0]), // AXI PS Master GP0 AWID[11:0], output
.MAXIGP0AWLOCK (), // AXI PS Master GP0 AWLOCK[1:0], output
.MAXIGP0AWCACHE (),// AXI PS Master GP0 AWCACHE[3:0], output
.MAXIGP0AWPROT (), // AXI PS Master GP0 AWPROT[2:0], output
.MAXIGP0AWLEN (axi_awlen[3:0]), // AXI PS Master GP0 AWLEN[3:0], output
.MAXIGP0AWSIZE (axi_awsize[1:0]), // AXI PS Master GP0 AWSIZE[1:0], output
.MAXIGP0AWBURST (axi_awburst[1:0]),// AXI PS Master GP0 AWBURST[1:0], output
.MAXIGP0AWQOS (), // AXI PS Master GP0 AWQOS[3:0], output
// AXI PS Master GP0: Write Data
.MAXIGP0WDATA (axi_wdata[31:0]), // AXI PS Master GP0 WDATA[31:0], output
.MAXIGP0WVALID (axi_wvalid), // AXI PS Master GP0 WVALID, output
.MAXIGP0WREADY (axi_wready), // AXI PS Master GP0 WREADY, input
.MAXIGP0WID (axi_wid[11:0]), // AXI PS Master GP0 WID[11:0], output
.MAXIGP0WLAST (axi_wlast), // AXI PS Master GP0 WLAST, output
.MAXIGP0WSTRB (axi_wstb[3:0]), // AXI PS Master GP0 WSTRB[3:0], output
// AXI PS Master GP0: Write Responce
.MAXIGP0BVALID (axi_bvalid), // AXI PS Master GP0 BVALID, input
.MAXIGP0BREADY (axi_bready), // AXI PS Master GP0 BREADY, output
.MAXIGP0BID (axi_bid[11:0]), // AXI PS Master GP0 BID[11:0], input
.MAXIGP0BRESP (axi_bresp[1:0]), // AXI PS Master GP0 BRESP[1:0], input
// AXI PS Master GP1
// AXI PS Master GP1: Clock, Reset
.MAXIGP1ACLK(), // AXI PS Master GP1 Clock , input
.MAXIGP1ARESETN(), // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
.MAXIGP1ARADDR(), // AXI PS Master GP1 ARADDR[31:0], output
.MAXIGP1ARVALID(), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY(), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID(), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARLOCK(), // AXI PS Master GP1 ARLOCK[1:0], output
.MAXIGP1ARCACHE(), // AXI PS Master GP1 ARCACHE[3:0], output
.MAXIGP1ARPROT(), // AXI PS Master GP1 ARPROT[2:0], output
.MAXIGP1ARLEN(), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE(), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST(), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARQOS(), // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
.MAXIGP1RDATA(), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID(), // AXI PS Master GP1 RVALID, input
.MAXIGP1RREADY(), // AXI PS Master GP1 RREADY, output
.MAXIGP1RID(), // AXI PS Master GP1 RID[11:0], input
.MAXIGP1RLAST(), // AXI PS Master GP1 RLAST, input
.MAXIGP1RRESP(), // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
.MAXIGP1AWADDR(), // AXI PS Master GP1 AWADDR[31:0], output
.MAXIGP1AWVALID(), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY(), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID(), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWLOCK(), // AXI PS Master GP1 AWLOCK[1:0], output
.MAXIGP1AWCACHE(), // AXI PS Master GP1 AWCACHE[3:0], output
.MAXIGP1AWPROT(), // AXI PS Master GP1 AWPROT[2:0], output
.MAXIGP1AWLEN(), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE(), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST(), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWQOS(), // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
.MAXIGP1WDATA(), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID(), // AXI PS Master GP1 WVALID, output
.MAXIGP1WREADY(), // AXI PS Master GP1 WREADY, input
.MAXIGP1WID(), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST(), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB(), // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write Responce
.MAXIGP1BVALID(), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY(), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID(), // AXI PS Master GP1 BID[11:0], input
.MAXIGP1BRESP(), // AXI PS Master GP1 BRESP[1:0], input
// AXI PS Slave GP0
// AXI PS Slave GP0: Clock, Reset
.SAXIGP0ACLK(), // AXI PS Slave GP0 Clock , input
.SAXIGP0ARESETN(), // AXI PS Slave GP0 Reset, output
// AXI PS Slave GP0: Read Address
.SAXIGP0ARADDR(), // AXI PS Slave GP0 ARADDR[31:0], input
.SAXIGP0ARVALID(), // AXI PS Slave GP0 ARVALID, input
.SAXIGP0ARREADY(), // AXI PS Slave GP0 ARREADY, output
.SAXIGP0ARID(), // AXI PS Slave GP0 ARID[5:0], input
.SAXIGP0ARLOCK(), // AXI PS Slave GP0 ARLOCK[1:0], input
.SAXIGP0ARCACHE(), // AXI PS Slave GP0 ARCACHE[3:0], input
.SAXIGP0ARPROT(), // AXI PS Slave GP0 ARPROT[2:0], input
.SAXIGP0ARLEN(), // AXI PS Slave GP0 ARLEN[3:0], input
.SAXIGP0ARSIZE(), // AXI PS Slave GP0 ARSIZE[1:0], input
.SAXIGP0ARBURST(), // AXI PS Slave GP0 ARBURST[1:0], input
.SAXIGP0ARQOS(), // AXI PS Slave GP0 ARQOS[3:0], input
// AXI PS Slave GP0: Read Data
.SAXIGP0RDATA(), // AXI PS Slave GP0 RDATA[31:0], output
.SAXIGP0RVALID(), // AXI PS Slave GP0 RVALID, output
.SAXIGP0RREADY(), // AXI PS Slave GP0 RREADY, input
.SAXIGP0RID(), // AXI PS Slave GP0 RID[5:0], output
.SAXIGP0RLAST(), // AXI PS Slave GP0 RLAST, output
.SAXIGP0RRESP(), // AXI PS Slave GP0 RRESP[1:0], output
// AXI PS Slave GP0: Write Address
.SAXIGP0AWADDR(), // AXI PS Slave GP0 AWADDR[31:0], input
.SAXIGP0AWVALID(), // AXI PS Slave GP0 AWVALID, input
.SAXIGP0AWREADY(), // AXI PS Slave GP0 AWREADY, output
.SAXIGP0AWID(), // AXI PS Slave GP0 AWID[5:0], input
.SAXIGP0AWLOCK(), // AXI PS Slave GP0 AWLOCK[1:0], input
.SAXIGP0AWCACHE(), // AXI PS Slave GP0 AWCACHE[3:0], input
.SAXIGP0AWPROT(), // AXI PS Slave GP0 AWPROT[2:0], input
.SAXIGP0AWLEN(), // AXI PS Slave GP0 AWLEN[3:0], input
.SAXIGP0AWSIZE(), // AXI PS Slave GP0 AWSIZE[1:0], input
.SAXIGP0AWBURST(), // AXI PS Slave GP0 AWBURST[1:0], input
.SAXIGP0AWQOS(), // AXI PS Slave GP0 AWQOS[3:0], input
// AXI PS Slave GP0: Write Data
.SAXIGP0WDATA(), // AXI PS Slave GP0 WDATA[31:0], input
.SAXIGP0WVALID(), // AXI PS Slave GP0 WVALID, input
.SAXIGP0WREADY(), // AXI PS Slave GP0 WREADY, output
.SAXIGP0WID(), // AXI PS Slave GP0 WID[5:0], input
.SAXIGP0WLAST(), // AXI PS Slave GP0 WLAST, input
.SAXIGP0WSTRB(), // AXI PS Slave GP0 WSTRB[3:0], input
// AXI PS Slave GP0: Write Responce
.SAXIGP0BVALID(), // AXI PS Slave GP0 BVALID, output
.SAXIGP0BREADY(), // AXI PS Slave GP0 BREADY, input
.SAXIGP0BID(), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!!
.SAXIGP0BRESP(), // AXI PS Slave GP0 BRESP[1:0], output
// AXI PS Slave GP1
// AXI PS Slave GP1: Clock, Reset
.SAXIGP1ACLK(), // AXI PS Slave GP1 Clock , input
.SAXIGP1ARESETN(), // AXI PS Slave GP1 Reset, output
// AXI PS Slave GP1: Read Address
.SAXIGP1ARADDR(), // AXI PS Slave GP1 ARADDR[31:0], input
.SAXIGP1ARVALID(), // AXI PS Slave GP1 ARVALID, input
.SAXIGP1ARREADY(), // AXI PS Slave GP1 ARREADY, output
.SAXIGP1ARID(), // AXI PS Slave GP1 ARID[5:0], input
.SAXIGP1ARLOCK(), // AXI PS Slave GP1 ARLOCK[1:0], input
.SAXIGP1ARCACHE(), // AXI PS Slave GP1 ARCACHE[3:0], input
.SAXIGP1ARPROT(), // AXI PS Slave GP1 ARPROT[2:0], input
.SAXIGP1ARLEN(), // AXI PS Slave GP1 ARLEN[3:0], input
.SAXIGP1ARSIZE(), // AXI PS Slave GP1 ARSIZE[1:0], input
.SAXIGP1ARBURST(), // AXI PS Slave GP1 ARBURST[1:0], input
.SAXIGP1ARQOS(), // AXI PS Slave GP1 ARQOS[3:0], input
// AXI PS Slave GP1: Read Data
.SAXIGP1RDATA(), // AXI PS Slave GP1 RDATA[31:0], output
.SAXIGP1RVALID(), // AXI PS Slave GP1 RVALID, output
.SAXIGP1RREADY(), // AXI PS Slave GP1 RREADY, input
.SAXIGP1RID(), // AXI PS Slave GP1 RID[5:0], output
.SAXIGP1RLAST(), // AXI PS Slave GP1 RLAST, output
.SAXIGP1RRESP(), // AXI PS Slave GP1 RRESP[1:0], output
// AXI PS Slave GP1: Write Address
.SAXIGP1AWADDR(), // AXI PS Slave GP1 AWADDR[31:0], input
.SAXIGP1AWVALID(), // AXI PS Slave GP1 AWVALID, input
.SAXIGP1AWREADY(), // AXI PS Slave GP1 AWREADY, output
.SAXIGP1AWID(), // AXI PS Slave GP1 AWID[5:0], input
.SAXIGP1AWLOCK(), // AXI PS Slave GP1 AWLOCK[1:0], input
.SAXIGP1AWCACHE(), // AXI PS Slave GP1 AWCACHE[3:0], input
.SAXIGP1AWPROT(), // AXI PS Slave GP1 AWPROT[2:0], input
.SAXIGP1AWLEN(), // AXI PS Slave GP1 AWLEN[3:0], input
.SAXIGP1AWSIZE(), // AXI PS Slave GP1 AWSIZE[1:0], input
.SAXIGP1AWBURST(), // AXI PS Slave GP1 AWBURST[1:0], input
.SAXIGP1AWQOS(), // AXI PS Slave GP1 AWQOS[3:0], input
// AXI PS Slave GP1: Write Data
.SAXIGP1WDATA(), // AXI PS Slave GP1 WDATA[31:0], input
.SAXIGP1WVALID(), // AXI PS Slave GP1 WVALID, input
.SAXIGP1WREADY(), // AXI PS Slave GP1 WREADY, output
.SAXIGP1WID(), // AXI PS Slave GP1 WID[5:0], input
.SAXIGP1WLAST(), // AXI PS Slave GP1 WLAST, input
.SAXIGP1WSTRB(), // AXI PS Slave GP1 WSTRB[3:0], input
// AXI PS Slave GP1: Write Responce
.SAXIGP1BVALID(), // AXI PS Slave GP1 BVALID, output
.SAXIGP1BREADY(), // AXI PS Slave GP1 BREADY, input
.SAXIGP1BID(), // AXI PS Slave GP1 BID[5:0], output
.SAXIGP1BRESP(), // AXI PS Slave GP1 BRESP[1:0], output
// AXI PS Slave HP0
// AXI PS Slave HP0: Clock, Reset
.SAXIHP0ACLK(), // AXI PS Slave HP0 Clock , input
.SAXIHP0ARESETN(), // AXI PS Slave HP0 Reset, output
// AXI PS Slave HP0: Read Address
.SAXIHP0ARADDR(), // AXI PS Slave HP0 ARADDR[31:0], input
.SAXIHP0ARVALID(), // AXI PS Slave HP0 ARVALID, input
.SAXIHP0ARREADY(), // AXI PS Slave HP0 ARREADY, output
.SAXIHP0ARID(), // AXI PS Slave HP0 ARID[5:0], input
.SAXIHP0ARLOCK(), // AXI PS Slave HP0 ARLOCK[1:0], input
.SAXIHP0ARCACHE(), // AXI PS Slave HP0 ARCACHE[3:0], input
.SAXIHP0ARPROT(), // AXI PS Slave HP0 ARPROT[2:0], input
.SAXIHP0ARLEN(), // AXI PS Slave HP0 ARLEN[3:0], input
.SAXIHP0ARSIZE(), // AXI PS Slave HP0 ARSIZE[2:0], input
.SAXIHP0ARBURST(), // AXI PS Slave HP0 ARBURST[1:0], input
.SAXIHP0ARQOS(), // AXI PS Slave HP0 ARQOS[3:0], input
// AXI PS Slave HP0: Read Data
.SAXIHP0RDATA(), // AXI PS Slave HP0 RDATA[63:0], output
.SAXIHP0RVALID(), // AXI PS Slave HP0 RVALID, output
.SAXIHP0RREADY(), // AXI PS Slave HP0 RREADY, input
.SAXIHP0RID(), // AXI PS Slave HP0 RID[5:0], output
.SAXIHP0RLAST(), // AXI PS Slave HP0 RLAST, output
.SAXIHP0RRESP(), // AXI PS Slave HP0 RRESP[1:0], output
.SAXIHP0RCOUNT(), // AXI PS Slave HP0 RCOUNT[7:0], output
.SAXIHP0RACOUNT(), // AXI PS Slave HP0 RACOUNT[2:0], output
.SAXIHP0RDISSUECAP1EN(), // AXI PS Slave HP0 RDISSUECAP1EN, input
// AXI PS Slave HP0: Write Address
.SAXIHP0AWADDR(), // AXI PS Slave HP0 AWADDR[31:0], input
.SAXIHP0AWVALID(), // AXI PS Slave HP0 AWVALID, input
.SAXIHP0AWREADY(), // AXI PS Slave HP0 AWREADY, output
.SAXIHP0AWID(), // AXI PS Slave HP0 AWID[5:0], input
.SAXIHP0AWLOCK(), // AXI PS Slave HP0 AWLOCK[1:0], input
.SAXIHP0AWCACHE(), // AXI PS Slave HP0 AWCACHE[3:0], input
.SAXIHP0AWPROT(), // AXI PS Slave HP0 AWPROT[2:0], input
.SAXIHP0AWLEN(), // AXI PS Slave HP0 AWLEN[3:0], input
.SAXIHP0AWSIZE(), // AXI PS Slave HP0 AWSIZE[1:0], input
.SAXIHP0AWBURST(), // AXI PS Slave HP0 AWBURST[1:0], input
.SAXIHP0AWQOS(), // AXI PS Slave HP0 AWQOS[3:0], input
// AXI PS Slave HP0: Write Data
.SAXIHP0WDATA(), // AXI PS Slave HP0 WDATA[63:0], input
.SAXIHP0WVALID(), // AXI PS Slave HP0 WVALID, input
.SAXIHP0WREADY(), // AXI PS Slave HP0 WREADY, output
.SAXIHP0WID(), // AXI PS Slave HP0 WID[5:0], input
.SAXIHP0WLAST(), // AXI PS Slave HP0 WLAST, input
.SAXIHP0WSTRB(), // AXI PS Slave HP0 WSTRB[7:0], input
.SAXIHP0WCOUNT(), // AXI PS Slave HP0 WCOUNT[7:0], output
.SAXIHP0WACOUNT(), // AXI PS Slave HP0 WACOUNT[5:0], output
.SAXIHP0WRISSUECAP1EN(), // AXI PS Slave HP0 WRISSUECAP1EN, input
// AXI PS Slave HP0: Write Responce
.SAXIHP0BVALID(), // AXI PS Slave HP0 BVALID, output
.SAXIHP0BREADY(), // AXI PS Slave HP0 BREADY, input
.SAXIHP0BID(), // AXI PS Slave HP0 BID[5:0], output
.SAXIHP0BRESP(), // AXI PS Slave HP0 BRESP[1:0], output
// AXI PS Slave HP1
// AXI PS Slave 1: Clock, Reset
.SAXIHP1ACLK(), // AXI PS Slave HP1 Clock , input
.SAXIHP1ARESETN(), // AXI PS Slave HP1 Reset, output
// AXI PS Slave HP1: Read Address
.SAXIHP1ARADDR(), // AXI PS Slave HP1 ARADDR[31:0], input
.SAXIHP1ARVALID(), // AXI PS Slave HP1 ARVALID, input
.SAXIHP1ARREADY(), // AXI PS Slave HP1 ARREADY, output
.SAXIHP1ARID(), // AXI PS Slave HP1 ARID[5:0], input
.SAXIHP1ARLOCK(), // AXI PS Slave HP1 ARLOCK[1:0], input
.SAXIHP1ARCACHE(), // AXI PS Slave HP1 ARCACHE[3:0], input
.SAXIHP1ARPROT(), // AXI PS Slave HP1 ARPROT[2:0], input
.SAXIHP1ARLEN(), // AXI PS Slave HP1 ARLEN[3:0], input
.SAXIHP1ARSIZE(), // AXI PS Slave HP1 ARSIZE[2:0], input
.SAXIHP1ARBURST(), // AXI PS Slave HP1 ARBURST[1:0], input
.SAXIHP1ARQOS(), // AXI PS Slave HP1 ARQOS[3:0], input
// AXI PS Slave HP1: Read Data
.SAXIHP1RDATA(), // AXI PS Slave HP1 RDATA[63:0], output
.SAXIHP1RVALID(), // AXI PS Slave HP1 RVALID, output
.SAXIHP1RREADY(), // AXI PS Slave HP1 RREADY, input
.SAXIHP1RID(), // AXI PS Slave HP1 RID[5:0], output
.SAXIHP1RLAST(), // AXI PS Slave HP1 RLAST, output
.SAXIHP1RRESP(), // AXI PS Slave HP1 RRESP[1:0], output
.SAXIHP1RCOUNT(), // AXI PS Slave HP1 RCOUNT[7:0], output
.SAXIHP1RACOUNT(), // AXI PS Slave HP1 RACOUNT[2:0], output
.SAXIHP1RDISSUECAP1EN(), // AXI PS Slave HP1 RDISSUECAP1EN, input
// AXI PS Slave HP1: Write Address
.SAXIHP1AWADDR(), // AXI PS Slave HP1 AWADDR[31:0], input
.SAXIHP1AWVALID(), // AXI PS Slave HP1 AWVALID, input
.SAXIHP1AWREADY(), // AXI PS Slave HP1 AWREADY, output
.SAXIHP1AWID(), // AXI PS Slave HP1 AWID[5:0], input
.SAXIHP1AWLOCK(), // AXI PS Slave HP1 AWLOCK[1:0], input
.SAXIHP1AWCACHE(), // AXI PS Slave HP1 AWCACHE[3:0], input
.SAXIHP1AWPROT(), // AXI PS Slave HP1 AWPROT[2:0], input
.SAXIHP1AWLEN(), // AXI PS Slave HP1 AWLEN[3:0], input
.SAXIHP1AWSIZE(), // AXI PS Slave HP1 AWSIZE[1:0], input
.SAXIHP1AWBURST(), // AXI PS Slave HP1 AWBURST[1:0], input
.SAXIHP1AWQOS(), // AXI PS Slave HP1 AWQOS[3:0], input
// AXI PS Slave HP1: Write Data
.SAXIHP1WDATA(), // AXI PS Slave HP1 WDATA[63:0], input
.SAXIHP1WVALID(), // AXI PS Slave HP1 WVALID, input
.SAXIHP1WREADY(), // AXI PS Slave HP1 WREADY, output
.SAXIHP1WID(), // AXI PS Slave HP1 WID[5:0], input
.SAXIHP1WLAST(), // AXI PS Slave HP1 WLAST, input
.SAXIHP1WSTRB(), // AXI PS Slave HP1 WSTRB[7:0], input
.SAXIHP1WCOUNT(), // AXI PS Slave HP1 WCOUNT[7:0], output
.SAXIHP1WACOUNT(), // AXI PS Slave HP1 WACOUNT[5:0], output
.SAXIHP1WRISSUECAP1EN(), // AXI PS Slave HP1 WRISSUECAP1EN, input
// AXI PS Slave HP1: Write Responce
.SAXIHP1BVALID(), // AXI PS Slave HP1 BVALID, output
.SAXIHP1BREADY(), // AXI PS Slave HP1 BREADY, input
.SAXIHP1BID(), // AXI PS Slave HP1 BID[5:0], output
.SAXIHP1BRESP(), // AXI PS Slave HP1 BRESP[1:0], output
// AXI PS Slave HP2
// AXI PS Slave HP2: Clock, Reset
.SAXIHP2ACLK(), // AXI PS Slave HP2 Clock , input
.SAXIHP2ARESETN(), // AXI PS Slave HP2 Reset, output
// AXI PS Slave HP2: Read Address
.SAXIHP2ARADDR(), // AXI PS Slave HP2 ARADDR[31:0], input
.SAXIHP2ARVALID(), // AXI PS Slave HP2 ARVALID, input
.SAXIHP2ARREADY(), // AXI PS Slave HP2 ARREADY, output
.SAXIHP2ARID(), // AXI PS Slave HP2 ARID[5:0], input
.SAXIHP2ARLOCK(), // AXI PS Slave HP2 ARLOCK[1:0], input
.SAXIHP2ARCACHE(), // AXI PS Slave HP2 ARCACHE[3:0], input
.SAXIHP2ARPROT(), // AXI PS Slave HP2 ARPROT[2:0], input
.SAXIHP2ARLEN(), // AXI PS Slave HP2 ARLEN[3:0], input
.SAXIHP2ARSIZE(), // AXI PS Slave HP2 ARSIZE[2:0], input
.SAXIHP2ARBURST(), // AXI PS Slave HP2 ARBURST[1:0], input
.SAXIHP2ARQOS(), // AXI PS Slave HP2 ARQOS[3:0], input
// AXI PS Slave HP2: Read Data
.SAXIHP2RDATA(), // AXI PS Slave HP2 RDATA[63:0], output
.SAXIHP2RVALID(), // AXI PS Slave HP2 RVALID, output
.SAXIHP2RREADY(), // AXI PS Slave HP2 RREADY, input
.SAXIHP2RID(), // AXI PS Slave HP2 RID[5:0], output
.SAXIHP2RLAST(), // AXI PS Slave HP2 RLAST, output
.SAXIHP2RRESP(), // AXI PS Slave HP2 RRESP[1:0], output
.SAXIHP2RCOUNT(), // AXI PS Slave HP2 RCOUNT[7:0], output
.SAXIHP2RACOUNT(), // AXI PS Slave HP2 RACOUNT[2:0], output
.SAXIHP2RDISSUECAP1EN(), // AXI PS Slave HP2 RDISSUECAP1EN, input
// AXI PS Slave HP2: Write Address
.SAXIHP2AWADDR(), // AXI PS Slave HP2 AWADDR[31:0], input
.SAXIHP2AWVALID(), // AXI PS Slave HP2 AWVALID, input
.SAXIHP2AWREADY(), // AXI PS Slave HP2 AWREADY, output
.SAXIHP2AWID(), // AXI PS Slave HP2 AWID[5:0], input
.SAXIHP2AWLOCK(), // AXI PS Slave HP2 AWLOCK[1:0], input
.SAXIHP2AWCACHE(), // AXI PS Slave HP2 AWCACHE[3:0], input
.SAXIHP2AWPROT(), // AXI PS Slave HP2 AWPROT[2:0], input
.SAXIHP2AWLEN(), // AXI PS Slave HP2 AWLEN[3:0], input
.SAXIHP2AWSIZE(), // AXI PS Slave HP2 AWSIZE[1:0], input
.SAXIHP2AWBURST(), // AXI PS Slave HP2 AWBURST[1:0], input
.SAXIHP2AWQOS(), // AXI PS Slave HP2 AWQOS[3:0], input
// AXI PS Slave HP2: Write Data
.SAXIHP2WDATA(), // AXI PS Slave HP2 WDATA[63:0], input
.SAXIHP2WVALID(), // AXI PS Slave HP2 WVALID, input
.SAXIHP2WREADY(), // AXI PS Slave HP2 WREADY, output
.SAXIHP2WID(), // AXI PS Slave HP2 WID[5:0], input
.SAXIHP2WLAST(), // AXI PS Slave HP2 WLAST, input
.SAXIHP2WSTRB(), // AXI PS Slave HP2 WSTRB[7:0], input
.SAXIHP2WCOUNT(), // AXI PS Slave HP2 WCOUNT[7:0], output
.SAXIHP2WACOUNT(), // AXI PS Slave HP2 WACOUNT[5:0], output
.SAXIHP2WRISSUECAP1EN(), // AXI PS Slave HP2 WRISSUECAP1EN, input
// AXI PS Slave HP2: Write Responce
.SAXIHP2BVALID(), // AXI PS Slave HP2 BVALID, output
.SAXIHP2BREADY(), // AXI PS Slave HP2 BREADY, input
.SAXIHP2BID(), // AXI PS Slave HP2 BID[5:0], output
.SAXIHP2BRESP(), // AXI PS Slave HP2 BRESP[1:0], output
// AXI PS Slave HP3
// AXI PS Slave HP3: Clock, Reset
.SAXIHP3ACLK(), // AXI PS Slave HP3 Clock , input
.SAXIHP3ARESETN(), // AXI PS Slave HP3 Reset, output
// AXI PS Slave HP3: Read Address
.SAXIHP3ARADDR(), // AXI PS Slave HP3 ARADDR[31:0], input
.SAXIHP3ARVALID(), // AXI PS Slave HP3 ARVALID, input
.SAXIHP3ARREADY(), // AXI PS Slave HP3 ARREADY, output
.SAXIHP3ARID(), // AXI PS Slave HP3 ARID[5:0], input
.SAXIHP3ARLOCK(), // AXI PS Slave HP3 ARLOCK[1:0], input
.SAXIHP3ARCACHE(), // AXI PS Slave HP3 ARCACHE[3:0], input
.SAXIHP3ARPROT(), // AXI PS Slave HP3 ARPROT[2:0], input
.SAXIHP3ARLEN(), // AXI PS Slave HP3 ARLEN[3:0], input
.SAXIHP3ARSIZE(), // AXI PS Slave HP3 ARSIZE[2:0], input
.SAXIHP3ARBURST(), // AXI PS Slave HP3 ARBURST[1:0], input
.SAXIHP3ARQOS(), // AXI PS Slave HP3 ARQOS[3:0], input
// AXI PS Slave HP3: Read Data
.SAXIHP3RDATA(), // AXI PS Slave HP3 RDATA[63:0], output
.SAXIHP3RVALID(), // AXI PS Slave HP3 RVALID, output
.SAXIHP3RREADY(), // AXI PS Slave HP3 RREADY, input
.SAXIHP3RID(), // AXI PS Slave HP3 RID[5:0], output
.SAXIHP3RLAST(), // AXI PS Slave HP3 RLAST, output
.SAXIHP3RRESP(), // AXI PS Slave HP3 RRESP[1:0], output
.SAXIHP3RCOUNT(), // AXI PS Slave HP3 RCOUNT[7:0], output
.SAXIHP3RACOUNT(), // AXI PS Slave HP3 RACOUNT[2:0], output
.SAXIHP3RDISSUECAP1EN(), // AXI PS Slave HP3 RDISSUECAP1EN, input
// AXI PS Slave HP3: Write Address
.SAXIHP3AWADDR(), // AXI PS Slave HP3 AWADDR[31:0], input
.SAXIHP3AWVALID(), // AXI PS Slave HP3 AWVALID, input
.SAXIHP3AWREADY(), // AXI PS Slave HP3 AWREADY, output
.SAXIHP3AWID(), // AXI PS Slave HP3 AWID[5:0], input
.SAXIHP3AWLOCK(), // AXI PS Slave HP3 AWLOCK[1:0], input
.SAXIHP3AWCACHE(), // AXI PS Slave HP3 AWCACHE[3:0], input
.SAXIHP3AWPROT(), // AXI PS Slave HP3 AWPROT[2:0], input
.SAXIHP3AWLEN(), // AXI PS Slave HP3 AWLEN[3:0], input
.SAXIHP3AWSIZE(), // AXI PS Slave HP3 AWSIZE[1:0], input
.SAXIHP3AWBURST(), // AXI PS Slave HP3 AWBURST[1:0], input
.SAXIHP3AWQOS(), // AXI PS Slave HP3 AWQOS[3:0], input
// AXI PS Slave HP3: Write Data
.SAXIHP3WDATA(), // AXI PS Slave HP3 WDATA[63:0], input
.SAXIHP3WVALID(), // AXI PS Slave HP3 WVALID, input
.SAXIHP3WREADY(), // AXI PS Slave HP3 WREADY, output
.SAXIHP3WID(), // AXI PS Slave HP3 WID[5:0], input
.SAXIHP3WLAST(), // AXI PS Slave HP3 WLAST, input
.SAXIHP3WSTRB(), // AXI PS Slave HP3 WSTRB[7:0], input
.SAXIHP3WCOUNT(), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT(), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN(), // AXI PS Slave HP3 WRISSUECAP1EN, input
// AXI PS Slave HP3: Write Responce
.SAXIHP3BVALID(), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY(), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID(), // AXI PS Slave HP3 BID[5:0], output
.SAXIHP3BRESP(), // AXI PS Slave HP3 BRESP[1:0], output
// AXI PS Slave ACP
// AXI PS Slave ACP: Clock, Reset
.SAXIACPACLK(), // AXI PS Slave ACP Clock, input
.SAXIACPARESETN(), // AXI PS Slave ACP Reset, output
// AXI PS Slave ACP: Read Address
.SAXIACPARADDR(), // AXI PS Slave ACP ARADDR[31:0], input
.SAXIACPARVALID(), // AXI PS Slave ACP ARVALID, input
.SAXIACPARREADY(), // AXI PS Slave ACP ARREADY, output
.SAXIACPARID(), // AXI PS Slave ACP ARID[2:0], input
.SAXIACPARLOCK(), // AXI PS Slave ACP ARLOCK[1:0], input
.SAXIACPARCACHE(), // AXI PS Slave ACP ARCACHE[3:0], input
.SAXIACPARPROT(), // AXI PS Slave ACP ARPROT[2:0], input
.SAXIACPARLEN(), // AXI PS Slave ACP ARLEN[3:0], input
.SAXIACPARSIZE(), // AXI PS Slave ACP ARSIZE[2:0], input
.SAXIACPARBURST(), // AXI PS Slave ACP ARBURST[1:0], input
.SAXIACPARQOS(), // AXI PS Slave ACP ARQOS[3:0], input
.SAXIACPARUSER(), // AXI PS Slave ACP ARUSER[4:0], input
// AXI PS Slave ACP: Read Data
.SAXIACPRDATA(), // AXI PS Slave ACP RDATA[63:0], output
.SAXIACPRVALID(), // AXI PS Slave ACP RVALID, output
.SAXIACPRREADY(), // AXI PS Slave ACP RREADY, input
.SAXIACPRID(), // AXI PS Slave ACP RID[2:0], output
.SAXIACPRLAST(), // AXI PS Slave ACP RLAST, output
.SAXIACPRRESP(), // AXI PS Slave ACP RRESP[1:0], output
// AXI PS Slave ACP: Write Address
.SAXIACPAWADDR(), // AXI PS Slave ACP AWADDR[31:0], input
.SAXIACPAWVALID(), // AXI PS Slave ACP AWVALID, input
.SAXIACPAWREADY(), // AXI PS Slave ACP AWREADY, output
.SAXIACPAWID(), // AXI PS Slave ACP AWID[2:0], input
.SAXIACPAWLOCK(), // AXI PS Slave ACP AWLOCK[1:0], input
.SAXIACPAWCACHE(), // AXI PS Slave ACP AWCACHE[3:0], input
.SAXIACPAWPROT(), // AXI PS Slave ACP AWPROT[2:0], input
.SAXIACPAWLEN(), // AXI PS Slave ACP AWLEN[3:0], input
.SAXIACPAWSIZE(), // AXI PS Slave ACP AWSIZE[1:0], input
.SAXIACPAWBURST(), // AXI PS Slave ACP AWBURST[1:0], input
.SAXIACPAWQOS(), // AXI PS Slave ACP AWQOS[3:0], input
.SAXIACPAWUSER(), // AXI PS Slave ACP AWUSER[4:0], input
// AXI PS Slave ACP: Write Data
.SAXIACPWDATA(), // AXI PS Slave ACP WDATA[63:0], input
.SAXIACPWVALID(), // AXI PS Slave ACP WVALID, input
.SAXIACPWREADY(), // AXI PS Slave ACP WREADY, output
.SAXIACPWID(), // AXI PS Slave ACP WID[2:0], input
.SAXIACPWLAST(), // AXI PS Slave ACP WLAST, input
.SAXIACPWSTRB(), // AXI PS Slave ACP WSTRB[7:0], input
// AXI PS Slave ACP: Write Responce
.SAXIACPBVALID(), // AXI PS Slave ACP BVALID, output
.SAXIACPBREADY(), // AXI PS Slave ACP BREADY, input
.SAXIACPBID(), // AXI PS Slave ACP BID[2:0], output
.SAXIACPBRESP(), // AXI PS Slave ACP BRESP[1:0], output
// Direct connection to PS package pads
.DDRA(), // PS DDRA[14:0], inout
.DDRBA(), // PS DDRBA[2:0], inout
.DDRCASB(), // PS DDRCASB, inout
.DDRCKE(), // PS DDRCKE, inout
.DDRCKP(), // PS DDRCKP, inout
.DDRCKN(), // PS DDRCKN, inout
.DDRCSB(), // PS DDRCSB, inout
.DDRDM(), // PS DDRDM[3:0], inout
.DDRDQ(), // PS DDRDQ[31:0], inout
.DDRDQSP(), // PS DDRDQSP[3:0], inout
.DDRDQSN(), // PS DDRDQSN[3:0], inout
.DDRDRSTB(), // PS DDRDRSTB, inout
.DDRODT(), // PS DDRODT, inout
.DDRRASB(), // PS DDRRASB, inout
.DDRVRN(), // PS DDRVRN, inout
.DDRVRP(), // PS DDRVRP, inout
.DDRWEB(), // PS DDRWEB, inout
.MIO(), // PS MIO[53:0], inout // clg225 has less
.PSCLK(), // PS PSCLK, inout
.PSPORB(), // PS PSPORB, inout
.PSSRSTB() // PS PSSRSTB, inout
);
endmodule
ddrc_test01_testbench.tf deleted 100644 → 0
View file @ 31a6b971
This source diff could not be displayed because it is too large. You can view the blob instead.
includes/x393_localparams.vh
View file @ a445ef42
......@@ -68,7 +68,7 @@
localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
localparam DQTRI_FIRST= 4'h7; // DQ tri-state control word, first when enabling output
localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
localparam WBUF_DLY_DFLT= 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_DFLT= DFLT_WBUF_DELAY; //4'h8; // 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_WLV= 4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
......
includes/x393_parameters.vh
View file @ a445ef42
......@@ -27,6 +27,7 @@
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
......@@ -99,7 +100,7 @@
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......@@ -203,6 +204,7 @@
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -232,6 +234,10 @@
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
\ No newline at end of file
includes/x393_tasks_mcntrl_buffers.vh
View file @ a445ef42
......@@ -86,6 +86,7 @@ task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
case (chn)
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
5: start_addr=MCONTR_BUF5_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write buffer = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
......
includes/x393_tasks_pio_sequences.vh
View file @ a445ef42
......@@ -47,11 +47,11 @@ task set_read_block;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0);
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i=1;i<64;i=i+1) begin
......@@ -62,11 +62,11 @@ task set_read_block;
end
// nop - all 3 below are the same? - just repeat?
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......@@ -188,11 +188,11 @@ task set_read_pattern;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0);
data <= func_encode_cmd( 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop (combine with previous?)
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i = 1; i < nrep; i = i + 1) begin
......@@ -206,11 +206,11 @@ task set_read_pattern;
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop, no write buffer - next page
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......
includes/x393_tasks_status.vh
View file @ a445ef42
......@@ -66,6 +66,7 @@ endtask
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
read_and_wait_status (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR);
end
endtask
......@@ -88,9 +89,11 @@ endtask
program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TILED_CHN5_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN5_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f,
end
endtask
......
memctrl/cmd_encod_linear_rd.v
View file @ a445ef42
......@@ -125,9 +125,9 @@ module cmd_encod_linear_rd #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_DCI);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
......
memctrl/cmd_encod_linear_wr.v
View file @ a445ef42
......@@ -208,74 +208,5 @@ module cmd_encod_linear_wr #(
// move to include?
`include "includes/x393_mcontr_encode_cmd.vh"
/*
function [31:0] func_encode_skip;
input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
input done; // end of sequence
input [2:0] bank; // bank (here OK to be any)
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
cke, // disable CKE
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0, // nop
buf_rst);
end
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column adderss
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
cke, // may be optimized (removed from here)?
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
buf_rst // Reserved for future use
};
end
endfunction
*/
endmodule
memctrl/cmd_encod_tiled_32_rd.v
View file @ a445ef42
......@@ -2,7 +2,7 @@
* Module: cmd_encod_tiled_32_rd
* Date:2015-02-218
* Author: andrey
* Description: Command sequencer generator for reading a tiled aread
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 32 bytes wide,
* then proceding to the next column (if >1).
......
memctrl/cmd_encod_tiled_rd.v
View file @ a445ef42
......@@ -2,7 +2,7 @@
* Module: cmd_encod_tiled_rd
* Date:2015-01-23
* Author: andrey
* Description: Command sequencer generator for reading a tiled aread
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
* then proceding to the next column (if >1).
......@@ -11,7 +11,7 @@
* AUTO RECHARGE will be applied only to the last column (single column OK).
* if number of rows >=8, that port is ignored. If number of rows is less than
* 5 (less for slower clock) without keep_open_in tRTP may be not matched.
*
* Seems that actual tile heigt mod 8 should be only 0, 6 or7
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_tiled_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -36,15 +36,16 @@ Can read less if just one column
TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary
number fo rows>1!
Need to insert pauses if activate in the first row and next column is too early
Known issues:
1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid)
2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width
is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and
frame full width? Seems easy to fix
*/
module cmd_encod_tiled_rd #(
// parameter BASEADDR = 0,
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
// parameter MIN_COL_INC= 3, // minimal number of zero column bits when incrementing row (after bank)
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10, // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
parameter FRAME_WIDTH_BITS= 13 // Maximal frame width - 8-word (16 bytes) bursts
......@@ -53,12 +54,9 @@ module cmd_encod_tiled_rd #(
input rst,
input clk,
// programming interface
// input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
// input cmd_stb, // strobe (with first byte) for the command a/d
input [2:0] start_bank, // bank address
input [ADDRESS_NUMBER-1:0] start_row, // memory row
input [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bit bursts
// input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [FRAME_WIDTH_BITS:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows_in_m1, // number of rows to read minus 1
input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
......@@ -126,22 +124,15 @@ module cmd_encod_tiled_rd #(
reg start_d; // start, delayed by 1 clocks
wire last_row;
reg [FULL_ADDR_NUMBER-1:0] row_col_bank; // RA,CA, BA - valid @pre_act;
/// reg [FULL_ADDR_NUMBER-1:0] row_col_bank_inc; // incremented RA,CA, BA - valid @pre_act_d;
// reg [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
wire [COLADDR_NUMBER-1:0] col_bank;// CA, BA - valid @ pre_read;
// reg [COLADDR_NUMBER-1:0] pre_col_bank;// CA, BA - valid @ pre_read;
wire enable_act;
// wire enable_autopre;
reg enable_autopre;
// reg pre_act_d;
// reg other_row; // other than first row (valid/changed @pre_act)
wire [2:0] next_bank_w;
wire [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] next_rowcol_w; // next row/col when bank rolls over (in 8-bursts)
reg loop_continue;
reg last_col_d; // delay by 1 pre_act cycles;
wire [FULL_ADDR_NUMBER-1:0] row_col_bank_next_w; // RA,CA, BA - valid @pre_act;
assign row_col_bank_next_w= last_row?
......@@ -162,17 +153,13 @@ module cmd_encod_tiled_rd #(
assign next_bank_w= row_col_bank[2:0]+1; //bank+1;
assign next_rowcol_w=row_col_bank[FULL_ADDR_NUMBER-1:3]+rowcol_inc;
// assign pre_act= rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
// assign pre_act= gen_run_d && rom_r[ENC_CMD_SHIFT+1]; //1 cycle before optional ACTIVATE
assign pre_act= gen_run && rom_cmd[1]; //1 cycle before optional ACTIVATE
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
//TODO:Add AUTOPRECHARGE + ACTIVATE when column crossed - No, caller should make sure there is no row address change in the same line
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
// else if (start) gen_run<= 1;
else if (start_d) gen_run<= 1; // delaying
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
if (rst) gen_run_d <= 0;
......@@ -189,31 +176,12 @@ module cmd_encod_tiled_rd #(
if (rst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+1;
else if (pre_act && last_row) top_rc <= top_rc+1; // may increment RA
/*
if (rst) pre_act_d <= 0;
/// else if (start_d) pre_act_d <= 0;
else pre_act_d <= pre_act;
if (rst) other_row <= 0;
else if (pre_act) other_row <= ~last_row;
*/
if (rst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
//TODO: maybe better to move 1 cicle later everything?
// else if (start) row_col_bank <= {start_row,start_col,start_bank}; // TODO: Use start_col,... and start, not start_d?
// else if (pre_act_d && ~other_row) row_col_bank <= {top_rc,bank};
// else if (pre_act_d && last_row) row_col_bank <= {top_rc,bank};
// else if (pre_act_d) row_col_bank <= row_col_bank_inc;
// else if (pre_act && last_row) row_col_bank <= {top_rc,bank};
// else if (pre_act) row_col_bank <= row_col_bank_inc;
else if (pre_act) row_col_bank <= row_col_bank_next_w;
/// if (rst) row_col_bank_inc<=0;
/// else row_col_bank_inc<=(&row_col_bank_inc[2:0]!=0)?
/// {row_col_bank_inc[FULL_ADDR_NUMBER-1:3],next_bank_w}:
/// {next_rowcol_w,row_col_bank_inc[2:0]};
if (rst) scan_row <= 0;
else if (start_d) scan_row <= 0;
......@@ -231,30 +199,14 @@ module cmd_encod_tiled_rd #(
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) last_col_d <= 0;
else if (start_d) last_col_d <= 0;
else if (pre_act) last_col_d <= last_col;
if (rst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
// else if (pre_act) enable_autopre <= last_col_d || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
//pre_col_bank
/*
if (rst) pre_col_bank<=0;
else if (start_d) pre_col_bank<= {col,bank};
else if (pre_act) pre_col_bank<= row_col_bank[COLADDR_NUMBER-1:0];
if (rst) col_bank<=0;
else if (start_d) col_bank<= {col,bank};
else if (pre_read) col_bank<= pre_col_bank; //row_col_bank[COLADDR_NUMBER-1:0];
*/
if (rst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
// else if (!start && !gen_run) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
......@@ -275,14 +227,14 @@ module cmd_encod_tiled_rd #(
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT);
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
......
memctrl/mcntrl393.v
View file @ a445ef42
......@@ -34,6 +34,7 @@ module mcntrl393 #(
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
//command interface parameters
......@@ -108,7 +109,7 @@ module mcntrl393 #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......@@ -188,6 +189,7 @@ module mcntrl393 #(
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -272,7 +274,7 @@ module mcntrl393 #(
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn3, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn3, // suspend transfers (from external line number comparator)
// Channel 4 (tiled tes)
// Channel 4 (tiled read)
input frame_start_chn4, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn4, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn4, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
......@@ -280,7 +282,14 @@ module mcntrl393 #(
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn4, // suspend transfers (from external line number comparator)
// Channel 5 (tiled write)
input frame_start_chn5, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn5, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn5, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done_chn5, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn5, // suspend transfers (from external line number comparator)
// DDR3 interface
......@@ -384,6 +393,17 @@ module mcntrl393 #(
wire buf_wpage_nxt_chn4;
wire [63:0] buf_wdata_chn4;
wire want_rq5;
wire need_rq5;
wire channel_pgm_en5;
wire [31:0] seq_data5x; // may be shared with other channel
wire seq_wr5x; // may be shared with other channel
wire seq_set5x; // may be shared with other channel
wire seq_done5;
wire rpage_nxt_chn5;
wire buf_rd_chn5;
wire [63:0] buf_rdata_chn5;
// Command tree - insert register layer if needed
wire [7:0] cmd_mcontr_ad;
wire cmd_mcontr_stb;
......@@ -395,6 +415,8 @@ module mcntrl393 #(
wire cmd_scanline_chn3_stb;
wire [7:0] cmd_tiled_chn4_ad;
wire cmd_tiled_chn4_stb;
wire [7:0] cmd_tiled_chn5_ad;
wire cmd_tiled_chn5_stb;
// Status tree:
......@@ -406,17 +428,21 @@ module mcntrl393 #(
wire status_ps_pio_rq; // PS PIO channels status request
wire status_ps_pio_start; // PS PIO channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn2_ad; // PS scanline channel2 (memory read) status byte-wide address/data
wire status_scanline_chn2_rq; // PS scanline channel2 (memory read) channels status request
wire status_scanline_chn2_start; // PS scanline channel2 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn2_ad; // PL scanline channel2 (memory read) status byte-wide address/data
wire status_scanline_chn2_rq; // PL scanline channel2 (memory read) channels status request
wire status_scanline_chn2_start; // PL scanline channel2 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn3_ad; // PS scanline channel3 (memory read) status byte-wide address/data
wire status_scanline_chn3_rq; // PS scanline channel3 (memory read) channels status request
wire status_scanline_chn3_start; // PS scanline channel3 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_scanline_chn3_ad; // PL scanline channel3 (memory read) status byte-wide address/data
wire status_scanline_chn3_rq; // PL scanline channel3 (memory read) channels status request
wire status_scanline_chn3_start; // PL scanline channel3 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn4_ad; // PS tiled channel4 (memory read) status byte-wide address/data
wire status_tiled_chn4_rq; // PS tiled channel4 (memory read) channels status request
wire status_tiled_chn4_start; // PS tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn4_ad; // PL tiled channel4 (memory read) status byte-wide address/data
wire status_tiled_chn4_rq; // PL tiled channel4 (memory read) channels status request
wire status_tiled_chn4_start; // PL tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_tiled_chn5_ad; // PL tiled channel5 (memory read) status byte-wide address/data
wire status_tiled_chn5_rq; // PL tiled channel5 (memory read) channels status request
wire status_tiled_chn5_start; // PL tiled channel5 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
// combinatorial early signals
wire select_cmd0_w;
......@@ -425,6 +451,7 @@ module mcntrl393 #(
wire select_buf2_w;
wire select_buf3_w;
wire select_buf4_w;
wire select_buf5_w;
// registered selects
reg select_cmd0;
reg select_buf0;
......@@ -432,6 +459,7 @@ module mcntrl393 #(
reg select_buf2;
reg select_buf3;
reg select_buf4;
reg select_buf5;
reg select_buf0_d; // delayed by 1 clock, for combining with regen?
reg select_buf2_d;
......@@ -445,6 +473,7 @@ module mcntrl393 #(
reg cmd_we;
reg buf1_we;
reg buf3_we;
reg buf5_we;
wire [BUFFER_DEPTH32-1:0] buf_raddr;
wire [31:0] buf0_data;
......@@ -487,15 +516,16 @@ module mcntrl393 #(
wire xfer_reset_page3; // "internal" buffer page reset, @posedge mclk
wire [2:0] tiled_rd_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rd_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rd_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rd_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rd_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rd_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rd_keep_open; // start generating commands
wire tiled_rd_xfer_partial; // start generating commands
wire [2:0] tiled_rw_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rw_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_rw_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_rw_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_rw_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_rw_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_rw_keep_open; // start generating commands
wire tiled_rw_xfer_partial; // start generating commands
wire tiled_rd_start; // start generating commands
wire tiled_wr_start; // start generating commands
wire [2:0] tiled_rd_chn4_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_rd_chn4_row; // memory row
......@@ -509,6 +539,16 @@ module mcntrl393 #(
wire xfer_reset_page4_pos; // "internal" buffer page reset, @posedge mclk
reg xfer_reset_page4_neg; // "internal" buffer page reset, @negedge mclk
wire [2:0] tiled_wr_chn5_bank; // bank address
wire [ADDRESS_NUMBER-1:0] tiled_wr_chn5_row; // memory row
wire [COLADDR_NUMBER-4:0] tiled_wr_chn5_col; // start memory column in 8-bursts
wire [FRAME_WIDTH_BITS:0] tiled_wr_chn5_rowcol_inc; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_WIDTH-1:0] tiled_wr_chn5_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [MAX_TILE_HEIGHT-1:0] tiled_wr_chn5_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire tiled_wr_chn5_keep_open; // start generating commands
wire tiled_wr_chn5_xfer_partial; // start generating commands
wire tiled_wr_chn5_start; // start generating commands
wire xfer_reset_page5; // "internal" buffer page reset, @posedge mclk
......@@ -523,6 +563,8 @@ module mcntrl393 #(
assign cmd_scanline_chn3_stb=cmd_stb;
assign cmd_tiled_chn4_ad= cmd_ad;
assign cmd_tiled_chn4_stb= cmd_stb;
assign cmd_tiled_chn5_ad= cmd_ad;
assign cmd_tiled_chn5_stb= cmd_stb;
......@@ -538,8 +580,9 @@ module mcntrl393 #(
assign buf4_regen= axird_regen && select_buf4_d;
assign page_ready_chn2=seq_done2;
assign page_ready_chn3=seq_done3;
assign page_ready_chn3=seq_done3; // TODO - check if it should not be rpage_next
assign page_ready_chn4=rpage_nxt_chn4;
assign page_ready_chn5=rpage_nxt_chn5; // ??? yes - seq_done is for every page
assign axird_selected=axird_selected_r;
......@@ -549,6 +592,7 @@ module mcntrl393 #(
assign select_buf2_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf3_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf4_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf5_w = ((axiwr_pre_awaddr ^ MCONTR_BUF5_WR_ADDR) & MCONTR_WR_MASK)==0;
always @ (posedge axi_rst or posedge axi_clk) begin
if (axi_rst) select_cmd0 <= 0;
......@@ -569,6 +613,9 @@ module mcntrl393 #(
if (axi_rst) select_buf4 <= 0;
else if (axird_start_burst) select_buf4 <= select_buf4_w;
if (axi_rst) select_buf5 <= 0;
else if (axiwr_start_burst) select_buf5 <= select_buf5_w;
if (axi_rst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf2_w ||select_buf4_w;
end
......@@ -578,6 +625,7 @@ module mcntrl393 #(
cmd_we <= axiwr_wen && select_cmd0;
buf1_we <= axiwr_wen && select_buf1;
buf3_we <= axiwr_wen && select_buf3;
buf5_we <= axiwr_wen && select_buf5;
select_buf0_d <= select_buf0;
select_buf2_d <= select_buf2;
......@@ -602,9 +650,9 @@ module mcntrl393 #(
.db_in4 (status_tiled_chn4_ad), // input[7:0]
.rq_in4 (status_tiled_chn4_rq), // input
.start_in4 (status_tiled_chn4_start), // output
.db_in5 (8'b0), // input[7:0]
.rq_in5 (1'b0), // input
.start_in5 (), // output
.db_in5 (status_tiled_chn5_ad), // input[7:0]
.rq_in5 (status_tiled_chn5_rq), // input
.start_in5 (status_tiled_chn5_start), // output
.db_in6 (8'b0), // input[7:0]
.rq_in6 (1'b0), // input
.start_in6 (), // output
......@@ -692,6 +740,57 @@ module mcntrl393 #(
.xfer_page_rst (xfer_reset_page4_pos) // output
);
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
.MCNTRL_TILED_STARTADDR (MCNTRL_TILED_STARTADDR),
.MCNTRL_TILED_FRAME_FULL_WIDTH (MCNTRL_TILED_FRAME_FULL_WIDTH),
.MCNTRL_TILED_WINDOW_WH (MCNTRL_TILED_WINDOW_WH),
.MCNTRL_TILED_WINDOW_X0Y0 (MCNTRL_TILED_WINDOW_X0Y0),
.MCNTRL_TILED_WINDOW_STARTXY (MCNTRL_TILED_WINDOW_STARTXY),
.MCNTRL_TILED_TILE_WHS (MCNTRL_TILED_TILE_WHS),
.MCNTRL_TILED_STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_CHN4_ADDR),
.MCNTRL_TILED_PENDING_CNTR_BITS(MCNTRL_TILED_PENDING_CNTR_BITS),
.MCNTRL_TILED_FRAME_PAGE_RESET (MCNTRL_TILED_FRAME_PAGE_RESET),
.MCNTRL_TILED_WRITE_MODE (1'b1)
) mcntrl_tiled_rw_chn5_i (
.rst(rst), // input
.mclk(mclk), // input
.cmd_ad (cmd_tiled_chn5_ad), // input[7:0]
.cmd_stb (cmd_tiled_chn5_stb), // input
.status_ad (status_tiled_chn5_ad), // output[7:0]
.status_rq (status_tiled_chn5_rq), // output
.status_start (status_tiled_chn5_start), // input
.frame_start (frame_start_chn5), // input
.next_page (next_page_chn5), // input
.frame_done (frame_done_chn5), // output
.frame_finished (), // output
.line_unfinished (line_unfinished_chn5), // output[15:0]
.suspend (suspend_chn5), // input
.xfer_want (want_rq5), // output
.xfer_need (need_rq5), // output
.xfer_grant (channel_pgm_en5), // input
.xfer_start (tiled_wr_chn5_start), // output
.xfer_bank (tiled_wr_chn5_bank), // output[2:0]
.xfer_row (tiled_wr_chn5_row), // output[14:0]
.xfer_col (tiled_wr_chn5_col), // output[6:0]
.rowcol_inc (tiled_wr_chn5_rowcol_inc), // output[13:0]
.num_rows_m1 (tiled_wr_chn5_num_rows_m1), // output[5:0]
.num_cols_m1 (tiled_wr_chn5_num_cols_m1), // output[5:0]
.keep_open (tiled_wr_chn5_keep_open), // output
.xfer_partial (tiled_wr_chn5_xfer_partial), // output
.xfer_page_done (seq_done5), // input
.xfer_page_rst (xfer_reset_page5) // output
);
cmd_encod_tiled_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -709,18 +808,53 @@ module mcntrl393 #(
.keep_open4 (tiled_rd_chn4_keep_open), // input
.partial4 (tiled_rd_chn4_xfer_partial), // input
.start4 (tiled_rd_chn4_start), // input
.bank (tiled_rd_bank), // output[2:0]
.row (tiled_rd_row), // output[14:0]
.col (tiled_rd_col), // output[6:0]
.rowcol_inc (tiled_rd_rowcol_inc), // output[13:0]
.num_rows (tiled_rd_num_rows_m1), // output[5:0]
.num_cols (tiled_rd_num_cols_m1), // output[5:0]
.keep_open (tiled_rd_keep_open), // output
.partial (tiled_rd_xfer_partial), // output
.bank5 (tiled_wr_chn5_bank), // input[2:0]
.row5 (tiled_wr_chn5_row), // input[14:0]
.col5 (tiled_wr_chn5_col), // input[6:0]
.rowcol_inc5 (tiled_wr_chn5_rowcol_inc), // input[13:0]
.num_rows5 (tiled_wr_chn5_num_rows_m1), // input[5:0]
.num_cols5 (tiled_wr_chn5_num_cols_m1), // input[5:0]
.keep_open5 (tiled_wr_chn5_keep_open), // input
.partial5 (tiled_wr_chn5_xfer_partial), // input
.start5 (tiled_wr_chn5_start), // input
.bank (tiled_rw_bank), // output[2:0]
.row (tiled_rw_row), // output[14:0]
.col (tiled_rw_col), // output[6:0]
.rowcol_inc (tiled_rw_rowcol_inc), // output[13:0]
.num_rows (tiled_rw_num_rows_m1), // output[5:0]
.num_cols (tiled_rw_num_cols_m1), // output[5:0]
.keep_open (tiled_rw_keep_open), // output
.partial (tiled_rw_xfer_partial), // output
.start_rd (tiled_rd_start), // output
.start_wr () // output
.start_wr (tiled_wr_start) // output
);
// with external defines, does not search module definition when creating closure for iverilog
// TODO: fix
`define USE_CMD_ENCOD_TILED_32_RD
`ifdef USE_CMD_ENCOD_TILED_32_RD
cmd_encod_tiled_32_rd #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_rd_start), // input
.enc_cmd (seq_data4x), // output[31:0] reg
.enc_wr (seq_wr4x), // output reg
.enc_done (seq_set4x) // output reg
);
`else
cmd_encod_tiled_rd #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
......@@ -729,21 +863,73 @@ module mcntrl393 #(
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rd_bank), // input[2:0]
.start_row (tiled_rd_row), // input[14:0]
.start_col (tiled_rd_col), // input[6:0]
.rowcol_inc_in (tiled_rd_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rd_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rd_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rd_keep_open), // input
.skip_next_page_in (tiled_rd_xfer_partial), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_rd_start), // input
.enc_cmd (seq_data4x), // output[31:0] reg
.enc_wr (seq_wr4x), // output reg
.enc_done (seq_set4x) // output reg
);
`endif
`undef USE_CMD_ENCOD_TILED_32_WR
`ifdef USE_CMD_ENCOD_TILED_32_WR
cmd_encod_tiled_32_wr #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_wr_start), // input
.enc_cmd (seq_data5x), // output[31:0] reg
.enc_wr (seq_wr5x), // output reg
.enc_done (seq_set5x) // output reg
);
`else
cmd_encod_tiled_wr #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.CMD_PAUSE_BITS(10),
.CMD_DONE_BIT(10)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
.start_col (tiled_rw_col), // input[6:0]
.rowcol_inc_in (tiled_rw_rowcol_inc), // input[13:0] // [21:0]
.num_rows_in_m1 (tiled_rw_num_rows_m1), // input[5:0]
.num_cols_in_m1 (tiled_rw_num_cols_m1), // input[5:0]
.keep_open_in (tiled_rw_keep_open), // input
.skip_next_page_in (tiled_rw_xfer_partial), // input
.start (tiled_wr_start), // input
.enc_cmd (seq_data5x), // output[31:0] reg
.enc_wr (seq_wr5x), // output reg
.enc_done (seq_set5x) // output reg
);
`endif
//
// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
// Port 2 (read DDR to AXI) buffer, linear
always @ (negedge mclk) begin
......@@ -769,7 +955,6 @@ module mcntrl393 #(
// Port 3 (write DDR from AXI) buffer, linear
mcntrl_1kx32w chn3_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
......@@ -800,6 +985,20 @@ module mcntrl393 #(
.data_in (buf_wdata_chn4) // input[63:0]
);
// Port 5 (write DDR from AXI) buffer, tiled
mcntrl_1kx32w chn5_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
.ext_we (buf5_we), // input
.ext_data_in (buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page5), // input TODO: Generate @ posedge mclk on frame start
.page_next (rpage_nxt_chn5), // input
.page (), // output[1:0]
.rd (buf_rd_chn5), // input
.data_out (buf_rdata_chn5) // output[63:0]
);
mcntrl_linear_rw #(
......@@ -1162,6 +1361,18 @@ module mcntrl393 #(
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.want_rq5 (want_rq5), // input
.need_rq5 (need_rq5), // input
.channel_pgm_en5 (channel_pgm_en5), // output reg
.seq_data5 (seq_data5x), // input[31:0]
.seq_wr5 (seq_wr5x), // input
.seq_set5 (seq_set5x), // input
.seq_done5 (seq_done5), // output
.rpage_nxt_chn5 (rpage_nxt_chn5), // output
.buf_run5 (),
.buf_rd_chn5 (buf_rd_chn5), // output
.buf_rdata_chn5 (buf_rdata_chn5), // input[63:0]
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
......
memctrl/mcntrl393_test01.v
View file @ a445ef42
......@@ -30,9 +30,12 @@ module mcntrl393_test01#(
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
)(
input rst,
input mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
......@@ -62,7 +65,15 @@ module mcntrl393_test01#(
input page_ready_chn4, // output
input frame_done_chn4, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4, // output[15:0]
output suspend_chn4 // input
output suspend_chn4, // input
output frame_start_chn5, // input
output next_page_chn5, // input
input page_ready_chn5, // output
input frame_done_chn5, // output
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5, // output[15:0]
output suspend_chn5 // input
);
localparam PAGE_BITS=4; // number of LSB to indicate pages read/written
localparam STATUS_PAYLOAD_BITS=FRAME_HEIGHT_BITS+PAGE_BITS+2;
......@@ -81,57 +92,75 @@ module mcntrl393_test01#(
wire [7:0] status_chn4_ad;
wire status_chn4_rq;
wire status_chn4_start; // input
wire [STATUS_PAYLOAD_BITS-1:0] status_chn5;
wire [7:0] status_chn5_ad;
wire status_chn5_rq;
wire status_chn5_start; // input
reg [PAGE_BITS-1:0] page_chn2;
reg [PAGE_BITS-1:0] page_chn3;
reg [PAGE_BITS-1:0] page_chn4;
reg [PAGE_BITS-1:0] page_chn5;
reg frame_start_chn2_r;
reg frame_start_chn3_r;
reg frame_start_chn4_r;
reg frame_start_chn5_r;
reg next_page_chn2_r;
reg next_page_chn3_r;
reg next_page_chn4_r;
reg next_page_chn5_r;
reg suspend_chn2_r;
reg suspend_chn3_r;
reg suspend_chn4_r;
reg suspend_chn5_r;
wire set_chh2_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_MODE); // set mode register for channel 2
wire set_chh2_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_STATUS_CNTRL); // control status reporting for channel 2
wire set_chh3_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_MODE); // set mode register for channel 3
wire set_chh3_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_STATUS_CNTRL); // control status reporting for channel 3
wire set_chh4_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_MODE); // set mode register for channel 4
wire set_chh4_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_STATUS_CNTRL); // control status reporting for channel 4
wire set_chn2_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_MODE); // set mode register for channel 2
wire set_chn2_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN2_STATUS_CNTRL); // control status reporting for channel 2
wire set_chn3_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_MODE); // set mode register for channel 3
wire set_chn3_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN3_STATUS_CNTRL); // control status reporting for channel 3
wire set_chn4_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_MODE); // set mode register for channel 4
wire set_chn4_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN4_STATUS_CNTRL); // control status reporting for channel 4
wire set_chn5_mode= cmd_we && (cmd_a== MCNTRL_TEST01_CHN5_MODE); // set mode register for channel 5
wire set_chn5_status= cmd_we && (cmd_a== MCNTRL_TEST01_CHN5_STATUS_CNTRL); // control status reporting for channel 5
wire cmd_frame_start_w=cmd_data[0];
wire cmd_next_page_w= cmd_data[1];
wire cmd_suspend_w= cmd_data[2];
reg frame_busy_chn2;
reg frame_busy_chn3;
reg frame_busy_chn4;
reg frame_busy_chn5;
reg frame_finished_chn2;
reg frame_finished_chn3;
reg frame_finished_chn4;
reg frame_finished_chn5;
assign frame_start_chn2 = frame_start_chn2_r;
assign frame_start_chn3 = frame_start_chn3_r;
assign frame_start_chn4 = frame_start_chn4_r;
assign frame_start_chn5 = frame_start_chn5_r;
assign next_page_chn2 = next_page_chn2_r;
assign next_page_chn3 = next_page_chn3_r;
assign next_page_chn4 = next_page_chn4_r;
assign next_page_chn5 = next_page_chn5_r;
assign suspend_chn2 = suspend_chn2_r;
assign suspend_chn3 = suspend_chn3_r;
assign suspend_chn4 = suspend_chn4_r;
assign suspend_chn5 = suspend_chn5_r;
assign status_chn2={page_chn2,line_unfinished_chn2,frame_finished_chn2, frame_busy_chn2};
assign status_chn3={page_chn3,line_unfinished_chn3,frame_finished_chn3, frame_busy_chn3};
assign status_chn4={page_chn4,line_unfinished_chn4,frame_finished_chn4, frame_busy_chn4};
assign status_chn5={page_chn5,line_unfinished_chn5,frame_finished_chn5, frame_busy_chn5};
always @ (posedge mclk) begin
frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chh3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chh4_mode && cmd_frame_start_w;
next_page_chn2_r <= set_chh2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chh3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chh4_mode && cmd_next_page_w;
frame_start_chn2_r <= set_chn2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chn3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chn4_mode && cmd_frame_start_w;
frame_start_chn5_r <= set_chn5_mode && cmd_frame_start_w;
next_page_chn2_r <= set_chn2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chn3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chn4_mode && cmd_next_page_w;
next_page_chn5_r <= set_chn5_mode && cmd_next_page_w;
end
always @ (posedge rst or posedge mclk) begin
......@@ -147,14 +176,21 @@ module mcntrl393_test01#(
else if (frame_start_chn4_r) page_chn4 <= 0;
else if (page_ready_chn4) page_chn4 <= page_chn4 + 1;
if (rst) page_chn5 <= 0;
else if (frame_start_chn5_r) page_chn5 <= 0;
else if (page_ready_chn5) page_chn5 <= page_chn5 + 1;
if (rst) suspend_chn2_r <= 0;
else if (set_chh2_mode) suspend_chn2_r <= cmd_suspend_w;
else if (set_chn2_mode) suspend_chn2_r <= cmd_suspend_w;
if (rst) suspend_chn3_r <= 0;
else if (set_chh3_mode) suspend_chn3_r <= cmd_suspend_w;
else if (set_chn3_mode) suspend_chn3_r <= cmd_suspend_w;
if (rst) suspend_chn4_r <= 0;
else if (set_chh4_mode) suspend_chn4_r <= cmd_suspend_w;
else if (set_chn4_mode) suspend_chn4_r <= cmd_suspend_w;
if (rst) suspend_chn5_r <= 0;
else if (set_chn5_mode) suspend_chn5_r <= cmd_suspend_w;
if (rst) frame_busy_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_busy_chn2 <= 1;
......@@ -168,6 +204,10 @@ module mcntrl393_test01#(
else if ( frame_start_chn4_r && !frame_done_chn4) frame_busy_chn4 <= 1;
else if (!frame_start_chn4_r && frame_done_chn4) frame_busy_chn4 <= 0;
if (rst) frame_busy_chn5 <= 0;
else if ( frame_start_chn5_r && !frame_done_chn5) frame_busy_chn5 <= 1;
else if (!frame_start_chn5_r && frame_done_chn5) frame_busy_chn5 <= 0;
if (rst) frame_finished_chn2 <= 0;
else if ( frame_start_chn2_r && !frame_done_chn2) frame_finished_chn2 <= 0;
else if (!frame_start_chn2_r && frame_done_chn2) frame_finished_chn2 <= 1;
......@@ -180,15 +220,20 @@ module mcntrl393_test01#(
else if ( frame_start_chn4_r && !frame_done_chn4) frame_finished_chn4 <= 0;
else if (!frame_start_chn4_r && frame_done_chn4) frame_finished_chn4 <= 1;
if (rst) frame_finished_chn5 <= 0;
else if ( frame_start_chn5_r && !frame_done_chn5) frame_finished_chn5 <= 0;
else if (!frame_start_chn5_r && frame_done_chn5) frame_finished_chn5 <= 1;
end
always @ (posedge mclk) begin
frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chh3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chh4_mode && cmd_frame_start_w;
next_page_chn2_r <= set_chh2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chh3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chh4_mode && cmd_next_page_w;
frame_start_chn2_r <= set_chn2_mode && cmd_frame_start_w;
frame_start_chn3_r <= set_chn3_mode && cmd_frame_start_w;
frame_start_chn4_r <= set_chn4_mode && cmd_frame_start_w;
frame_start_chn5_r <= set_chn5_mode && cmd_frame_start_w;
next_page_chn2_r <= set_chn2_mode && cmd_next_page_w;
next_page_chn3_r <= set_chn3_mode && cmd_next_page_w;
next_page_chn4_r <= set_chn4_mode && cmd_next_page_w;
next_page_chn5_r <= set_chn5_mode && cmd_next_page_w;
end
cmd_deser #(
......@@ -220,9 +265,9 @@ module mcntrl393_test01#(
.db_in2 (status_chn4_ad), // input[7:0]
.rq_in2 (status_chn4_rq), // input
.start_in2 (status_chn4_start), // output
.db_in3 (8'b0), // input[7:0]
.rq_in3 (1'b0), // input
.start_in3 (), // output
.db_in3 (status_chn5_ad), // input[7:0]
.rq_in3 (status_chn5_rq), // input
.start_in3 (status_chn5_start), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
......@@ -235,7 +280,7 @@ module mcntrl393_test01#(
) status_generate_chn2_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chh2_status), // input
.we (set_chn2_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn2), // input[25:0]
.ad (status_chn2_ad), // output[7:0]
......@@ -249,7 +294,7 @@ module mcntrl393_test01#(
) status_generate_chn3_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chh3_status), // input
.we (set_chn3_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn3), // input[25:0]
.ad (status_chn3_ad), // output[7:0]
......@@ -263,12 +308,26 @@ module mcntrl393_test01#(
) status_generate_chn4_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chh4_status), // input
.we (set_chn4_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn4), // input[25:0]
.ad (status_chn4_ad), // output[7:0]
.rq (status_chn4_rq), // output
.start (status_chn4_start) // input
);
status_generate #(
.STATUS_REG_ADDR(MCNTRL_TEST01_STATUS_REG_CHN5_ADDR),
.PAYLOAD_BITS(STATUS_PAYLOAD_BITS)
) status_generate_chn5_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_chn5_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_chn5), // input[25:0]
.ad (status_chn5_ad), // output[7:0]
.rq (status_chn5_rq), // output
.start (status_chn5_start) // input
);
endmodule
memctrl/mcntrl_tiled_rw.v
View file @ a445ef42
......@@ -173,7 +173,7 @@ module mcntrl_tiled_rw#(
// otherwise (smaller widths) round up to the nearest power of 2
reg [FRAME_WIDTH_BITS:0] window_width; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_height; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_m_tile_height; // (window height-tile height
// reg [FRAME_HEIGHT_BITS:0] window_m_tile_height; // (window height-tile height
reg [FRAME_WIDTH_BITS-1:0] window_x0; // (programmed) window left
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
......@@ -323,7 +323,7 @@ module mcntrl_tiled_rw#(
last_in_row <= last_in_row_w;
end
window_m_tile_height <= window_height - tile_rows;
// window_m_tile_height <= window_height - tile_rows;
end
// now have row start address, bank and row_left ;
......
memctrl/memctrl16.v
View file @ a445ef42
......@@ -94,7 +94,7 @@ module memctrl16 #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......
memctrl/phy/ddrc_sequencer.v
View file @ a445ef42
......@@ -413,6 +413,7 @@ module ddrc_sequencer #(
.buf_rdata (buf_rdata[63:0]), // input[63:0]
.buf_wr (buf_wr_ndly), // output
.buf_rd (buf_rd), // output
.buf_rst (), // output
.cmda_en (cmda_en), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
......
memctrl/phy/mcontr_sequencer.v
View file @ a445ef42
......@@ -64,7 +64,7 @@ module mcontr_sequencer #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc,// DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter PHASE_WIDTH = 8,
......
util_modules/mcont_from_chnbuf_reg.v
View file @ a445ef42
......@@ -48,7 +48,8 @@ module mcont_from_chnbuf_reg #(
else buf_run <= (ext_buf_rchn==CHN_NUMBER) && !ext_buf_rrefresh && ext_buf_rrun;
if (rst) latency_reg<= 0;
else latency_reg <= buf_rd_chn | (latency_reg << 1);
// else latency_reg <= buf_rd_chn | (latency_reg << 1);
else latency_reg <= {latency_reg[CHN_LATENCY-1:0], buf_rd_chn};
// if (rst) buf_done <= 0;
// else buf_done <= buf_chn_sel && seq_done;
......
x393.v
View file @ a445ef42
......@@ -20,7 +20,7 @@
*******************************************************************************/
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
//`define DEBUG_FIFO 1
`include ".editor_defines.vh"
module x393 #(
parameter MCONTR_WR_MASK = 'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
......@@ -32,6 +32,7 @@ module x393 #(
parameter MCONTR_BUF2_RD_ADDR = 'h0800, // AXI read address from buffer 2 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h0800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h0c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF5_WR_ADDR = 'h0c00, // AXI write address to buffer 5 (PL sequence, scanline, memory write)
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
......@@ -104,7 +105,7 @@ module x393 #(
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......@@ -208,6 +209,7 @@ module x393 #(
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN4_ADDR= 'h140,
parameter MCNTRL_TILED_CHN5_ADDR= 'h140,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
......@@ -237,9 +239,12 @@ module x393 #(
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_CHN5_MODE= 'ha, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN5_STATUS_CNTRL= 'hb, // control status reporting for channel 5
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN5_ADDR= 'h3f // status/readback register for channel 4
)(
// DDR3 interface
output SDRST, // DDR3 reset (active low)
......@@ -472,6 +477,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
wire frame_done_chn4; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn4; // output[15:0]
wire suspend_chn4; // input
wire frame_start_chn5; // input
wire next_page_chn5; // input
wire page_ready_chn5; // output
wire frame_done_chn5; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn5; // output[15:0]
wire suspend_chn5; // input
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
......@@ -500,9 +511,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_CHN5_MODE (MCNTRL_TEST01_CHN5_MODE),
.MCNTRL_TEST01_CHN5_STATUS_CNTRL (MCNTRL_TEST01_CHN5_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN5_ADDR (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR)
) mcntrl393_test01_i (
.rst(axi_rst), // input
.mclk (mclk), // input
......@@ -528,7 +542,13 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.page_ready_chn4 (page_ready_chn4), // input
.frame_done_chn4 (frame_done_chn4), // input
.line_unfinished_chn4 (line_unfinished_chn4), // input[15:0]
.suspend_chn4 (suspend_chn4) // output
.suspend_chn4 (suspend_chn4), // output
.frame_start_chn5 (frame_start_chn5), // output
.next_page_chn5 (next_page_chn5), // output
.page_ready_chn5 (page_ready_chn5), // input
.frame_done_chn5 (frame_done_chn5), // input
.line_unfinished_chn5 (line_unfinished_chn5), // input[15:0]
.suspend_chn5 (suspend_chn5) // output
);
// Interface to channels to read/write memory (including 4 page BRAM buffers)
......@@ -626,6 +646,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF3_WR_ADDR (MCONTR_BUF3_WR_ADDR),
.MCONTR_BUF4_RD_ADDR (MCONTR_BUF4_RD_ADDR),
.MCONTR_BUF5_WR_ADDR (MCONTR_BUF5_WR_ADDR),
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
......@@ -721,6 +742,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_CHN5_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -777,6 +799,12 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.frame_done_chn4 (frame_done_chn4), // output
.line_unfinished_chn4 (line_unfinished_chn4), // output[15:0]
.suspend_chn4 (suspend_chn4), // input
.frame_start_chn5 (frame_start_chn5), // input
.next_page_chn5 (next_page_chn5), // input
.page_ready_chn5 (page_ready_chn5), // output
.frame_done_chn5 (frame_done_chn5), // output
.line_unfinished_chn5 (line_unfinished_chn5), // output[15:0]
.suspend_chn5 (suspend_chn5), // input
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
......@@ -800,7 +828,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//MEMCLK
wire [63:0] gpio_in;
assign gpio_in={
assign gpio_in= {52'h0,tmp_debug};
/*
{
frst[3]?{
16'b0,
1'b1, // 1
......@@ -839,6 +869,7 @@ frst[3]?{
// dly_ready // 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
......@@ -853,6 +884,7 @@ frst[3]?{
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
......@@ -879,6 +911,7 @@ frst[3]?{
fifo_rst, // fclk[0], // 0/1
axi_rst_pre //axi_rst // 0
};
*/
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
......
x393_testbench01.sav
View file @ a445ef42
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Thu Feb 19 00:22:31 2015
[*] Fri Feb 20 01:10:48 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150218163406252.lxt"
[dumpfile_mtime] "Wed Feb 18 23:51:24 2015"
[dumpfile_size] 990238054
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150219175501126.lxt"
[dumpfile_mtime] "Fri Feb 20 01:04:32 2015"
[dumpfile_size] 503390527
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 46460000
[timestart] 0
[size] 1823 1180
[pos] 1927 0
*-21.698502 56251875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 2056 0
*-24.698502 64666875 55877500 55843010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.chn3_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.chn4_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.genblk4.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
......@@ -1290,12 +1290,6 @@ x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn2[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn3[0]
x393_testbench01.x393_i.mcntrl393_test01_i.page_ready_chn4[0]
x393_testbench01.x393_i.mcntrl393_test01_i.rst[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh2_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh2_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh3_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh3_status[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh4_mode[0]
x393_testbench01.x393_i.mcntrl393_test01_i.set_chh4_status[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.status_ad[7:0]
x393_testbench01.x393_i.mcntrl393_test01_i.status_chn2[21:0]
......@@ -1327,7 +1321,268 @@ x393_testbench01.x393_i.mcntrl393_test01_i.suspend_chn4_r[0]
-mcntrl393_test01
@22
x393_testbench01.ii[31:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.frame_start_chn5_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_finished[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.recalc_r[8:0]
@28
x393_testbench01.x393_i.mcntrl393_test01_i.next_page_chn5[0]
@22
x393_testbench01.x393_i.mcntrl393_test01_i.page_chn5[3:0]
@200
-
@22
x393_testbench01.write_block_scanline_chn.chn[31:0]
x393_testbench01.write_block_scanline_chn.start_addr[29:0]
@800200
-tiled_ch5
@28
x393_testbench01.x393_i.mcntrl393_i.select_buf5_w[0]
x393_testbench01.x393_i.mcntrl393_i.select_buf5[0]
x393_testbench01.x393_i.mcntrl393_i.buf5_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.last_row_w[0]
@200
-
@c00200
-ch5_buf
@22
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.data_out[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.ext_waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.raddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.rd[0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.chn5_buf_i.rpage_set[0]
@1401200
-ch5_buf
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.busy_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.calc_valid[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.chn_en[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.chn_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.chn_rst_d[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_a[3:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_ad[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_extra_pages[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_stb[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.cmd_wrmem[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.continued_tile[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.curr_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.curr_y[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_done_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_finished[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_finished_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_full_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_full_width_r[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_start[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_y8_r[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.frame_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.i[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.last_block[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.last_in_row[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.last_row_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.leftover_cols[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.lim_by_tile_width[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.line_start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.line_start_page_left[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.line_unfinished[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.line_unfinished_r0[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.line_unfinished_r1[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.lsw13_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.mem_page_left[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.mode_reg[4:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.msw_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.mul_rslt[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.mul_rslt_w[26:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.need_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.next_page[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.next_y[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.num_cols_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.num_cols_m1_w[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.num_cols_r[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.num_rows_m1_w[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.page_cntr[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.par_mod_r[8:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.pending_xfers[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.pgm_param_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.pre_want[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.recalc_r[8:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.remainder_tile_width[7:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.row_col_r[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.row_left[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.rowcol_inc[13:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_frame_width_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_mode_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_start_addr_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_status_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_tile_whs_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_window_start_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_window_wh_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.set_window_x0y0_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.start_addr[21:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.start_addr_r[21:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.start_not_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.start_x[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.start_y[15:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.status_ad[7:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.status_data[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.status_rq[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.status_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.suspend[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.tile_cols[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.tile_height_zero[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.tile_rows[6:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.tile_vstep[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.tile_vstep_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.tile_width_zero[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.want_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.window_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.window_width[13:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.window_x0[12:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.window_y0[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_bank[2:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_col[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_grant[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_limited_by_mem_page[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_limited_by_mem_page_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_need[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_page_done[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_page_done_d[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_page_rst[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_page_rst_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_partial[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_row[14:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn5_i.xfer_want[0]
@1000200
-tiled_ch5
@c00200
-encod_tiled_wr
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.gen_run[0]
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.full_cmd[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enable_autopre[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_read[0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.col_bank[9:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.cut_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enable_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enable_autopre[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enc_cmd[31:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enc_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.enc_wr[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.first_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.full_cmd[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.gen_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.gen_run_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.keep_open_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.last_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.last_row[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.loop_continue[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.next_bank_w[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.next_rowcol_w[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.num_cols128_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.num_cols_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.num_rows_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_done[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.pre_read[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rom_cmd[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rom_r[11:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rom_skip[1:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.row_col_bank[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.row_col_bank_next_w[24:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rowcol_inc_in[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.scan_col[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.scan_row[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.skip_next_page_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.start[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.start_bank[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.start_col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.start_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.start_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_wr_i.top_rc[21:0]
@1401200
-encod_tiled_wr
@c00200
-gtiled_ch4
@28
x393_testbench01.x393_i.mcntrl393_i.select_buf4[0]
......@@ -1375,10 +1630,8 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.want_r[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_row_w[0]
@23
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.window_m_tile_height[16:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.next_y[16:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_in_row_w[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.last_block[0]
......@@ -1625,11 +1878,16 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_row[14:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_start_r[2:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_tiled_rw_chn4_i.xfer_want[0]
@1000200
@1401200
-gtiled_ch4
@c00200
-encod_tiled
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols128_m2[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.scan_col[5:0]
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start[0]
......@@ -1639,7 +1897,6 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.row[14:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.col[6:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.rowcol_inc[13:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols128_m1[5:0]
@28
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.skip_next_page[0]
......@@ -1649,7 +1906,6 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.skip_next_page[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.start_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_run[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.enable_autopre[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_act[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.pre_read[0]
......@@ -1723,12 +1979,10 @@ x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.gen_run_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.keep_open[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.keep_open_in[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_col_d[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.last_row[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.loop_continue[0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.next_bank_w[2:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.next_rowcol_w[21:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols128_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_cols_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_rows_in_m1[5:0]
x393_testbench01.x393_i.mcntrl393_i.cmd_encod_tiled_rd_i.num_rows_m1[5:0]
......
x393_testbench01.tf
View file @ a445ef42
......@@ -31,10 +31,12 @@
//`define TEST_READ_BLOCK 1
`define TEST_SCANLINE_WRITE 1
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_WRITE 1
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ 1
`define TEST_READ_SHOW 1
`define TEST_READ_SHOW 1
`define TEST_TILED_WRITE 1
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_TILED_READ 1
......@@ -213,10 +215,10 @@ module x393_testbench01 #(
localparam TILED_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] TILED_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam TILED_KEEP_OPEN= 1'b0; //1'b1; // 1'b0; // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)
localparam TILED_KEEP_OPEN= 1'b1; //1'b1; // 1'b0; // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)
localparam TILE_WIDTH= 'h03; // 6-bit tile width (1..'h40)
localparam TILE_HEIGHT= 'h05; // 'h04; //'h06; // 6-bit tile height (1..'h40) // 4 - violation
localparam TILE_WIDTH= 'h04; // 6-bit tile width (1..'h40)
localparam TILE_HEIGHT= 'h08; //'h05; // 'h04; //'h06; // 6-bit tile height (1..'h40) // 4 - violation
localparam TILE_VSTEP= 'h04; // 6-bit tile vertical step, with no overlap it is equal to TILE_HEIGHT (1..'h40)
......@@ -229,7 +231,9 @@ module x393_testbench01 #(
//NUM_XFER_BITS=6
localparam SCANLINE_PAGES_PER_ROW= (WINDOW_WIDTH>>NUM_XFER_BITS)+((WINDOW_WIDTH[NUM_XFER_BITS-1:0]==0)?0:1);
localparam TILES_PER_ROW= (WINDOW_WIDTH/TILE_WIDTH)+ ((WINDOW_WIDTH % TILE_WIDTH==0)?0:1);
localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-TILE_HEIGHT)/TILE_VSTEP) + (((WINDOW_HEIGHT-TILE_HEIGHT)%TILE_VSTEP==0)?0:1) +1;
// localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-TILE_HEIGHT)/TILE_VSTEP) + (((WINDOW_HEIGHT-TILE_HEIGHT)%TILE_VSTEP==0)?0:1) +1;
// localparam TILE_ROWS_PER_WINDOW= (WINDOW_HEIGHT/TILE_VSTEP) + ((WINDOW_HEIGHT%TILE_VSTEP==0)?0:1);
localparam TILE_ROWS_PER_WINDOW= ((WINDOW_HEIGHT-1)/TILE_VSTEP) + 1;
localparam TILE_SIZE= TILE_WIDTH*TILE_HEIGHT;
......@@ -278,6 +282,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
enable_memcntrl(1); // enable memory controller
set_up;
axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY - used in synth. code
wait_phase_shifter_ready;
read_all_status;
// enable output for address/commands to DDR chip
......@@ -348,7 +354,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
axi_set_dqs_idelay_nominal;
// axi_set_dqs_odelay_nominal;
axi_set_dqs_odelay('h78);
axi_set_wbuf_delay(WBUF_DLY_DFLT);
axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY
`endif
`ifdef TEST_READ_PATTERN
schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
......@@ -404,18 +410,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
configure_channel_priority(3,0); // lowest priority channel 3
enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
// localparam TEST01_START_FRAME= 1;
// localparam TEST01_NEXT_PAGE= 2;
// localparam TEST01_SUSPEND= 4;
/*
integer SCANLINE_CUR_X;
integer SCANLINE_CUR_Y;
//SCANLINE_PAGES_PER_ROW
*/
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
// SCANLINE_CUR_X = WINDOW_X0 + ((ii % SCANLINE_PAGES_PER_ROW) << NUM_XFER_BITS);
// SCANLINE_CUR_Y = WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW);
// VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
SCANLINE_XFER_SIZE= ((SCANLINE_PAGES_PER_ROW>1)?
(
......@@ -435,11 +431,6 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
WINDOW_Y0 + (ii / SCANLINE_PAGES_PER_ROW)); // SCANLINE_CUR_Y);\
end
/*
localparam SCANLINE_FULL_XFER= 1<<NUM_XFER_BITS; // 64 - full page transfer in 8-bursts
localparam SCANLINE_LAST_XFER= WINDOW_WIDTH % (1<<NUM_XFER_BITS); // last page transfer size in a row
*/
for (ii=0;ii< (WINDOW_HEIGHT * SCANLINE_PAGES_PER_ROW) ;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
......@@ -469,7 +460,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
end
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE, TEST01_NEXT_PAGE);
end
`ifdef TEST_SCANLINE_WRITE_WAIT // Does it work?
`ifdef TEST_SCANLINE_WRITE_WAIT
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
......@@ -523,6 +514,61 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
end
`endif
`ifdef TEST_TILED_WRITE
// program to the
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_WINDOW_WH, WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_WINDOW_X0Y0, WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_TILE_WHS, TILE_WIDTH+(TILE_HEIGHT<<8)+(TILE_VSTEP<<16));
write_contol_register(MCNTRL_TILED_CHN5_ADDR + MCNTRL_TILED_MODE, {27'b0,TILED_KEEP_OPEN,TILED_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(5,0); // lowest priority channel 5
enable_memcntrl_channels(16'h002f); // channels 0,1,2,3 and 5 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_MODE, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
5, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1); // not equal to
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
5, // channel
(ii & 3),
TILE_SIZE,
WINDOW_X0 + ((ii % TILES_PER_ROW) * TILE_WIDTH),
WINDOW_Y0 + (ii / TILE_ROWS_PER_WINDOW)); // SCANLINE_CUR_Y);\
end
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_MODE, TEST01_NEXT_PAGE);
end
`ifdef TEST_TILED_WRITE_WAIT
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0); // equal to
`endif
`endif
`ifdef TEST_TILED_READ
// program to the
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
......@@ -534,7 +580,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
write_contol_register(MCNTRL_TILED_CHN4_ADDR + MCNTRL_TILED_MODE, {27'b0,TILED_KEEP_OPEN,TILED_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(4,0); // lowest priority channel 2
enable_memcntrl_channels(16'h001f); // channels 0,1,2,3,4 are enabled
enable_memcntrl_channels(16'h003f); // channels 0,1,2,3,4 and 5 are enabled
write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE, TEST01_START_FRAME);
for (ii=0;ii<(TILES_PER_ROW * TILE_ROWS_PER_WINDOW);ii = ii+1) begin
......@@ -564,6 +610,7 @@ end
initial begin
// #10000000;
#200000;
// #60000;
$display("finish testbench 2");
$finish;
end
......@@ -630,6 +677,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF3_WR_ADDR (MCONTR_BUF3_WR_ADDR),
.MCONTR_BUF4_RD_ADDR (MCONTR_BUF4_RD_ADDR),
.MCONTR_BUF5_WR_ADDR (MCONTR_BUF5_WR_ADDR),
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
......@@ -748,6 +796,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MAX_TILE_WIDTH (MAX_TILE_WIDTH),
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_CHN5_ADDR (MCNTRL_TILED_CHN5_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -769,9 +818,12 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCNTRL_TEST01_CHN3_STATUS_CNTRL (MCNTRL_TEST01_CHN3_STATUS_CNTRL),
.MCNTRL_TEST01_CHN4_MODE (MCNTRL_TEST01_CHN4_MODE),
.MCNTRL_TEST01_CHN4_STATUS_CNTRL (MCNTRL_TEST01_CHN4_STATUS_CNTRL),
.MCNTRL_TEST01_CHN5_MODE (MCNTRL_TEST01_CHN5_MODE),
.MCNTRL_TEST01_CHN5_STATUS_CNTRL (MCNTRL_TEST01_CHN5_STATUS_CNTRL),
.MCNTRL_TEST01_STATUS_REG_CHN2_ADDR (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN5_ADDR (MCNTRL_TEST01_STATUS_REG_CHN5_ADDR)
) x393_i (
.SDRST (SDRST), // DDR3 reset (active low)
.SDCLK (SDCLK), // output
......@@ -1196,6 +1248,7 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
case (chn)
1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
5: start_addr=MCONTR_BUF5_WR_ADDR + (page << 8); // it is actually tiled, not scanline
default: begin
$display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
......
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