Loading fpga_version.vh +2 −1 Original line number Original line Diff line number Diff line Loading @@ -35,7 +35,8 @@ * contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it * with at least one of the Free Software programs. * with at least one of the Free Software programs. */ */ parameter FPGA_VERSION = 32'h039300ba; //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03% parameter FPGA_VERSION = 32'h039300bb; //parallel, adding i2c almost full. -0.101/8, 79.37% // parameter FPGA_VERSION = 32'h039300ba; //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03% // parameter FPGA_VERSION = 32'h039300b9; //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64% // parameter FPGA_VERSION = 32'h039300b9; //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64% // parameter FPGA_VERSION = 32'h039300b8; //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% // parameter FPGA_VERSION = 32'h039300b8; //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% // parameter FPGA_VERSION = 32'h039300b7; //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92% // parameter FPGA_VERSION = 32'h039300b7; //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92% Loading py393/x393_export_c.py +1 −1 Original line number Original line Diff line number Diff line Loading @@ -1826,7 +1826,7 @@ class X393ExportC(object): dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data")) dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data")) dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)")) dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)")) dw.append(("busy", 10, 1,0, "I2C sequencer busy")) dw.append(("busy", 10, 1,0, "I2C sequencer busy")) dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update")) dw.append(("wr_full", 11, 1,0, "Write buffer almost full (14..3/4 in ASAP mode)")) dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number")) dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number")) dw.append(("req_clr", 16, 1,0, "Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)")) dw.append(("req_clr", 16, 1,0, "Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)")) dw.append(("reset_on", 17, 1,0, "Reset in progress")) dw.append(("reset_on", 17, 1,0, "Reset in progress")) Loading py393/x393_jpeg.py +3 −3 Original line number Original line Diff line number Diff line Loading @@ -1903,8 +1903,8 @@ set_gpio_ports 1 1 # enable software gpio pins and porta (camsync) set_gpio_pins 0 1 # pin 0 low, pin 1 - high set_gpio_pins 0 1 # pin 0 low, pin 1 - high set_camsync_period 31 # set bit duration set_camsync_period 31 # set bit duration set_camsync_period 7500 # 75 usec set_camsync_period 8000 # 80 usec set_camsync_delay 0 0 set_camsync_delay 0 400 set_camsync_delay 1 100 set_camsync_delay 1 100 set_camsync_delay 2 200 set_camsync_delay 2 200 set_camsync_delay 3 300 set_camsync_delay 3 300 Loading Loading @@ -2014,7 +2014,7 @@ jpeg_sim_multi 4 #set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None> #set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None> set_camsync_mode None None None 0 set_camsync_mode None None None 0 jpeg_sim_multi 4 jpeg_sim_multi 4 jpeg_sim_multi 4 jpeg_sim_multi 8 Loading py393/x393_sensor.py +2 −2 Original line number Original line Diff line number Diff line Loading @@ -240,7 +240,7 @@ class X393Sensor(object): print (" reset_on = %d"%((status>>17) & 1)) print (" reset_on = %d"%((status>>17) & 1)) print (" req_clr = %d"%((status>>16) & 1)) print (" req_clr = %d"%((status>>16) & 1)) print (" frame_num = %d"%((status>>12) & 0xf)) print (" frame_num = %d"%((status>>12) & 0xf)) print (" alive_fs = %d"%((status>>11) & 1)) print (" wr_full = %d"%((status>>11) & 1)) print (" busy = %d"%((status>>10) & 1)) print (" busy = %d"%((status>>10) & 1)) print (" i2c_fifo_lsb = %d"%((status>> 9) & 1)) print (" i2c_fifo_lsb = %d"%((status>> 9) & 1)) print (" i2c_fifo_nempty = %d"%((status>> 8) & 1)) print (" i2c_fifo_nempty = %d"%((status>> 8) & 1)) Loading Loading @@ -1326,7 +1326,7 @@ class X393Sensor(object): print ("print_status_sensor_i2c(%d):"%(num_sensor)) print ("print_status_sensor_i2c(%d):"%(num_sensor)) print (" reset_on = %d"%((status>> 7) & 1)) print (" reset_on = %d"%((status>> 7) & 1)) print (" req_clr = %d"%((status>> 6) & 1)) print (" req_clr = %d"%((status>> 6) & 1)) print (" alive_fs = %d"%((status>> 5) & 1)) print (" wr_full = %d"%((status>> 5) & 1)) print (" busy = %d"%((status>> 4) & 1)) print (" busy = %d"%((status>> 4) & 1)) print (" frame_num = %d"%((status>> 0) & 0xf)) print (" frame_num = %d"%((status>> 0) & 0xf)) Loading sensor/sensor_i2c.v +18 −5 Original line number Original line Diff line number Diff line Loading @@ -198,6 +198,14 @@ module sensor_i2c#( reg [5:0] fifo_fill; // number of words written to the other (not current) page, or difference wp-rp for the current reg [5:0] fifo_fill; // number of words written to the other (not current) page, or difference wp-rp for the current wire [5:0] fifo_wr_pointers_next; // pointer value to be written to fifo_wr_pointers_ram[wpage_wr] wire [5:0] fifo_wr_pointers_next; // pointer value to be written to fifo_wr_pointers_ram[wpage_wr] // Preventing overflow when many i2c commands are written in ASAP mode (stopped compressor) wire [1:0] send_diff= fifo_wr_pointers_outr[5:4] - rpointer[5:4]; // to determine buffer full in ASAP mode wire wr_full_w = (wpage0==wpage_wr)? // is it ASAP mode (i.e. sequencer is stopped, progr. 10359) send_diff[1]: // 1/4..3/4 full in ASAP mode (&fifo_wr_pointers_outw_r[5:2]); // current page almost full reg wr_full_r; // fifo_wr_pointers_outw_r assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0 assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0 assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0 assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0 assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ; assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ; Loading @@ -217,13 +225,13 @@ module sensor_i2c#( assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); /* reg alive_fs; reg alive_fs; always @ (posedge mclk) begin always @ (posedge mclk) begin if (set_status_w) alive_fs <= 0; if (set_status_w) alive_fs <= 0; else if (frame_sync) alive_fs <= 1; else if (frame_sync) alive_fs <= 1; end end */ cmd_deser #( cmd_deser #( .ADDR (SENSI2C_ABS_ADDR), .ADDR (SENSI2C_ABS_ADDR), Loading Loading @@ -258,7 +266,10 @@ module sensor_i2c#( .status ({reset_on, req_clr, .status ({reset_on, req_clr, fifo_fill[5:0], fifo_fill[5:0], frame_num[3:0], frame_num[3:0], alive_fs,busy, i2c_fifo_cntrl, i2c_fifo_nempty, wr_full_r, // alive_fs, busy, i2c_fifo_cntrl, i2c_fifo_nempty, i2c_fifo_dout[7:0], i2c_fifo_dout[7:0], sda_in, scl_in}), // input[25:0] sda_in, scl_in}), // input[25:0] .ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0] Loading @@ -281,6 +292,8 @@ module sensor_i2c#( ); ); always @ (posedge mclk) begin always @ (posedge mclk) begin wr_full_r <= wr_full_w; // write buffer is almost full if (wen) di_r <= di; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long if (wen) di_r <= di; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long wen_r <= {wen_r[0],wen}; // is it needed? wen_r <= {wen_r[0],wen}; // is it needed? // wen_fifo <= {wen_fifo[0],we_rel || we_abs}; // wen_fifo <= {wen_fifo[0],we_rel || we_abs}; Loading Loading @@ -387,7 +400,7 @@ module sensor_i2c#( else if (page_r_inc[0]) page_r <= page_r+1; else if (page_r_inc[0]) page_r <= page_r+1; `endif `endif //############ rpointer should start not from 0, but form value in another RAM??? //############ rpointer should start not from 0, but from the value in another RAM??? if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0; if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0; else if (i2c_run_d && ! i2c_run) rpointer[5:0] <= rpointer[5:0] + 1; else if (i2c_run_d && ! i2c_run) rpointer[5:0] <= rpointer[5:0] + 1; Loading Loading
fpga_version.vh +2 −1 Original line number Original line Diff line number Diff line Loading @@ -35,7 +35,8 @@ * contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it * with at least one of the Free Software programs. * with at least one of the Free Software programs. */ */ parameter FPGA_VERSION = 32'h039300ba; //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03% parameter FPGA_VERSION = 32'h039300bb; //parallel, adding i2c almost full. -0.101/8, 79.37% // parameter FPGA_VERSION = 32'h039300ba; //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03% // parameter FPGA_VERSION = 32'h039300b9; //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64% // parameter FPGA_VERSION = 32'h039300b9; //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64% // parameter FPGA_VERSION = 32'h039300b8; //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% // parameter FPGA_VERSION = 32'h039300b8; //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% // parameter FPGA_VERSION = 32'h039300b7; //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92% // parameter FPGA_VERSION = 32'h039300b7; //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92% Loading
py393/x393_export_c.py +1 −1 Original line number Original line Diff line number Diff line Loading @@ -1826,7 +1826,7 @@ class X393ExportC(object): dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data")) dw.append(("i2c_fifo_nempty", 8, 1,0, "I2C read FIFO has data")) dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)")) dw.append(("i2c_fifo_lsb", 9, 1,0, "I2C FIFO byte counter (odd/even bytes)")) dw.append(("busy", 10, 1,0, "I2C sequencer busy")) dw.append(("busy", 10, 1,0, "I2C sequencer busy")) dw.append(("alive_fs", 11, 1,0, "Sensor generated frame sync since last status update")) dw.append(("wr_full", 11, 1,0, "Write buffer almost full (14..3/4 in ASAP mode)")) dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number")) dw.append(("frame_num", 12, 4,0, "I2C sequencer frame number")) dw.append(("req_clr", 16, 1,0, "Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)")) dw.append(("req_clr", 16, 1,0, "Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)")) dw.append(("reset_on", 17, 1,0, "Reset in progress")) dw.append(("reset_on", 17, 1,0, "Reset in progress")) Loading
py393/x393_jpeg.py +3 −3 Original line number Original line Diff line number Diff line Loading @@ -1903,8 +1903,8 @@ set_gpio_ports 1 1 # enable software gpio pins and porta (camsync) set_gpio_pins 0 1 # pin 0 low, pin 1 - high set_gpio_pins 0 1 # pin 0 low, pin 1 - high set_camsync_period 31 # set bit duration set_camsync_period 31 # set bit duration set_camsync_period 7500 # 75 usec set_camsync_period 8000 # 80 usec set_camsync_delay 0 0 set_camsync_delay 0 400 set_camsync_delay 1 100 set_camsync_delay 1 100 set_camsync_delay 2 200 set_camsync_delay 2 200 set_camsync_delay 3 300 set_camsync_delay 3 300 Loading Loading @@ -2014,7 +2014,7 @@ jpeg_sim_multi 4 #set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None> #set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None> set_camsync_mode None None None 0 set_camsync_mode None None None 0 jpeg_sim_multi 4 jpeg_sim_multi 4 jpeg_sim_multi 4 jpeg_sim_multi 8 Loading
py393/x393_sensor.py +2 −2 Original line number Original line Diff line number Diff line Loading @@ -240,7 +240,7 @@ class X393Sensor(object): print (" reset_on = %d"%((status>>17) & 1)) print (" reset_on = %d"%((status>>17) & 1)) print (" req_clr = %d"%((status>>16) & 1)) print (" req_clr = %d"%((status>>16) & 1)) print (" frame_num = %d"%((status>>12) & 0xf)) print (" frame_num = %d"%((status>>12) & 0xf)) print (" alive_fs = %d"%((status>>11) & 1)) print (" wr_full = %d"%((status>>11) & 1)) print (" busy = %d"%((status>>10) & 1)) print (" busy = %d"%((status>>10) & 1)) print (" i2c_fifo_lsb = %d"%((status>> 9) & 1)) print (" i2c_fifo_lsb = %d"%((status>> 9) & 1)) print (" i2c_fifo_nempty = %d"%((status>> 8) & 1)) print (" i2c_fifo_nempty = %d"%((status>> 8) & 1)) Loading Loading @@ -1326,7 +1326,7 @@ class X393Sensor(object): print ("print_status_sensor_i2c(%d):"%(num_sensor)) print ("print_status_sensor_i2c(%d):"%(num_sensor)) print (" reset_on = %d"%((status>> 7) & 1)) print (" reset_on = %d"%((status>> 7) & 1)) print (" req_clr = %d"%((status>> 6) & 1)) print (" req_clr = %d"%((status>> 6) & 1)) print (" alive_fs = %d"%((status>> 5) & 1)) print (" wr_full = %d"%((status>> 5) & 1)) print (" busy = %d"%((status>> 4) & 1)) print (" busy = %d"%((status>> 4) & 1)) print (" frame_num = %d"%((status>> 0) & 0xf)) print (" frame_num = %d"%((status>> 0) & 0xf)) Loading
sensor/sensor_i2c.v +18 −5 Original line number Original line Diff line number Diff line Loading @@ -198,6 +198,14 @@ module sensor_i2c#( reg [5:0] fifo_fill; // number of words written to the other (not current) page, or difference wp-rp for the current reg [5:0] fifo_fill; // number of words written to the other (not current) page, or difference wp-rp for the current wire [5:0] fifo_wr_pointers_next; // pointer value to be written to fifo_wr_pointers_ram[wpage_wr] wire [5:0] fifo_wr_pointers_next; // pointer value to be written to fifo_wr_pointers_ram[wpage_wr] // Preventing overflow when many i2c commands are written in ASAP mode (stopped compressor) wire [1:0] send_diff= fifo_wr_pointers_outr[5:4] - rpointer[5:4]; // to determine buffer full in ASAP mode wire wr_full_w = (wpage0==wpage_wr)? // is it ASAP mode (i.e. sequencer is stopped, progr. 10359) send_diff[1]: // 1/4..3/4 full in ASAP mode (&fifo_wr_pointers_outw_r[5:2]); // current page almost full reg wr_full_r; // fifo_wr_pointers_outw_r assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0 assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0 assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0 assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0 assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ; assign pre_wpage0_inc = (!wen && !(|wen_r) && !wpage0_inc[0]) && (req_clr || reset_on) ; Loading @@ -217,13 +225,13 @@ module sensor_i2c#( assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); /* reg alive_fs; reg alive_fs; always @ (posedge mclk) begin always @ (posedge mclk) begin if (set_status_w) alive_fs <= 0; if (set_status_w) alive_fs <= 0; else if (frame_sync) alive_fs <= 1; else if (frame_sync) alive_fs <= 1; end end */ cmd_deser #( cmd_deser #( .ADDR (SENSI2C_ABS_ADDR), .ADDR (SENSI2C_ABS_ADDR), Loading Loading @@ -258,7 +266,10 @@ module sensor_i2c#( .status ({reset_on, req_clr, .status ({reset_on, req_clr, fifo_fill[5:0], fifo_fill[5:0], frame_num[3:0], frame_num[3:0], alive_fs,busy, i2c_fifo_cntrl, i2c_fifo_nempty, wr_full_r, // alive_fs, busy, i2c_fifo_cntrl, i2c_fifo_nempty, i2c_fifo_dout[7:0], i2c_fifo_dout[7:0], sda_in, scl_in}), // input[25:0] sda_in, scl_in}), // input[25:0] .ad (status_ad), // output[7:0] .ad (status_ad), // output[7:0] Loading @@ -281,6 +292,8 @@ module sensor_i2c#( ); ); always @ (posedge mclk) begin always @ (posedge mclk) begin wr_full_r <= wr_full_w; // write buffer is almost full if (wen) di_r <= di; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long if (wen) di_r <= di; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long wen_r <= {wen_r[0],wen}; // is it needed? wen_r <= {wen_r[0],wen}; // is it needed? // wen_fifo <= {wen_fifo[0],we_rel || we_abs}; // wen_fifo <= {wen_fifo[0],we_rel || we_abs}; Loading Loading @@ -387,7 +400,7 @@ module sensor_i2c#( else if (page_r_inc[0]) page_r <= page_r+1; else if (page_r_inc[0]) page_r <= page_r+1; `endif `endif //############ rpointer should start not from 0, but form value in another RAM??? //############ rpointer should start not from 0, but from the value in another RAM??? if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0; if (reset_cmd || page_r_inc[0]) rpointer[5:0] <= 6'h0; else if (i2c_run_d && ! i2c_run) rpointer[5:0] <= rpointer[5:0] + 1; else if (i2c_run_d && ! i2c_run) rpointer[5:0] <= rpointer[5:0] + 1; Loading