version 0xba, fixed introduced bug

 * contains all the components and scripts required to completely simulate it

 * with at least one of the Free Software programs.

 */

        parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%

        parameter FPGA_VERSION =          32'h039300ba;      //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03%

//        parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%

//      parameter FPGA_VERSION =          32'h039300b8;      //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% 

//      parameter FPGA_VERSION =          32'h039300b7;      //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%

//      parameter FPGA_VERSION =          32'h039300b6;      //parallel, working on histograms odd colors bug -0.207 /58,  79.68%

checkSclSda 1

cat /usr/local/verilog/x359.bit > /dev/sfpgaconfjtag1

#cat /usr/local/verilog/x359.bit > /dev/sfpgaconfjtag1

#jtag_set_pgm_mode 0 1

                     xfpgatdo_byte[7:0],

                     vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 

                     clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,

                     ps_out,

                     ps_rdy, ps_out,

                     xfpgatdo, senspgmin};

    assign hact_out = hact_r;