tested register writes, status generation, routing and reading

.gitignore

@@ -8,3 +8,4 @@ IVERILOG_INCLUDE.v
 x393.prj
 *DEBUG_VDT*
 *.kate-swp
+*.old

address_map.txt

@@ -56,7 +56,23 @@
     parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1,    // 8-bit refresh period
     parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2,    // 10 bits refresh address in the sequencer (PL) memory
     parameter MCONTR_TOP_16BIT_STATUS_CNTRL=    'h3,    // 8 bits - write to status control (and debug?)
+0x1080..10ff
+  0x1080..10ff - DLY_LD   // 8 bits :
+  0x1080..109f - set delay for SDD0-SDD7
+  0x10a0..10bf - set delay for SDD8-SDD15
+  0x10c0..10df - set delay for SD_CMDA
+  0x10e0       - set delay for MMCM
 
+  localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
+  localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090
+  localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
+  localparam LD_DLY_LANE1_IDELAY = DLY_LD+'h30; // 0x10b0
+  localparam LD_DLY_CMDA  =        DLY_LD+'h40; // 0x10c0
+  localparam LD_DLY_PHASE =        DLY_LD+'h60; // 0x10e0
+  localparam DLY_SET =             MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
+  
+  
+  
 ----
     parameter MCNTRL_TEST01_ADDR=       'h0f0,
     parameter MCNTRL_TEST01_MASK=       'h3f0

axi/axibram_read.v

@@ -18,6 +18,8 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
+ // Check that this fix did not break anything:
+`define USE_SHORT_REN_REGEN 
 module  axibram_read #(
     parameter ADDRESS_BITS = 10 // number of memory address bits
 )(
@@ -129,13 +131,24 @@ module  axibram_read #(
 // External memory interface
    assign  bram_rclk =  aclk;  // clock for read port
    assign  bram_raddr = read_in_progress?read_address[ADDRESS_BITS-1:0]:{ADDRESS_BITS{1'b1}};  // read address
+   
+`ifdef USE_SHORT_REN_REGEN   
+   reg bram_regen_r;
+   assign  bram_ren =   bram_reg_re_w && !pre_last_in_burst_r ;     // read port enable
+   assign  bram_regen = bram_regen_r;     // output register enable
+`else
    assign  bram_ren =   bram_reg_re_w;     // read port enable
    assign  bram_regen = bram_reg_re_w;     // output register enable
+`endif   
    
    assign  rdata[31:0] = bram_rdata;    // data out
 
     always @ (posedge  aclk or posedge  rst) begin
-    
+`ifdef USE_SHORT_REN_REGEN   
+      if   (rst)  bram_regen_r <= 0;
+      else        bram_regen_r <=  bram_ren;
+`endif    
+   
       if   (rst)                   pre_last_in_burst_r <= 0;
 //      else if (start_read_burst_w) pre_last_in_burst_r <= (read_left==4'b0);
       else if (bram_reg_re_w)      pre_last_in_burst_r <= (read_left==4'b0);
@@ -227,6 +240,7 @@ fifo_same_clock   #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
     raddr_i (
         .rst(rst),
         .clk(aclk),
+        .sync_rst(1'b0), // input
         .we(arvalid && arready),
         .re(start_read_burst_w),
         .data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),

includes/x393_localparams.vh

-// SuppressWarnings VEditor
-/*
-    localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000  << 2
-// SuppressWarnings VEditor
-    localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
-///    localparam BASEADDR_CMD0 =     CMD0_ADDR << 2;     // 'h0800 << 2 = 'h2000
-//    localparam BASEADDR_CTRL =     CONTROL_ADDR << 2;
-///    localparam BASEADDR_CTRL =     (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
-    localparam BASEADDR_STATUS =   STATUS_ADDR << 2;   // 'h0800 << 2 = 'h2000
-///    localparam BASEADDR_DLY_LD =  BASEADDR_CTRL | (DLY_LD_REL <<2);  // 'h080, address to generate delay load
-    localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2);  // 'h070, address to generate delay set
-    localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2);  // 'h000, address to set sequnecer channel and  run (4 LSB-s - channel)
+// S uppressWarnings VEditor
+  localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
+  localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090
+  localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
+  localparam LD_DLY_LANE1_IDELAY = DLY_LD+'h30; // 0x10b0
+  localparam LD_DLY_CMDA  =        DLY_LD+'h40; // 0x10c0
+  localparam LD_DLY_PHASE =        DLY_LD+'h60; // 0x10e0
+  localparam DLY_SET =             MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
 
-    localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
-    localparam BASEADDR_PATTERNS_TRI =BASEADDR_CTRL | (PATTERNS_TRI_REL<<2); // 'h021, address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
-    localparam BASEADDR_WBUF_DELAY =BASEADDR_CTRL | (WBUF_DELAY_REL<<2); // 'h022, extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
-// SuppressWarnings VEditor
-    localparam BASEADDR_PAGES =   BASEADDR_CTRL | (PAGES_REL<<2);    // 'h023, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
-    localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2);  // 'h024, address to enable('h825)/disable('h824) command/address outputs  
-    localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // 'h026 address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory     
-///    localparam BASEADDR_CKE_EN =  BASEADDR_CTRL | (CKE_EN_REL<<2);   // 'h028
-    
-// SuppressWarnings VEditor
-    localparam BASEADDR_DCI_RST =  BASEADDR_CTRL | (DCI_RST_REL<<2);   // 'h02a (+1 - enable)
-// SuppressWarnings VEditor
-    localparam BASEADDR_DLY_RST =  BASEADDR_CTRL | (DLY_RST_REL<<2);   // 'h02c (+1 - enable)
-      
-// SuppressWarnings VEditor
-    localparam BASEADDR_EXTRA =   BASEADDR_CTRL | (EXTRA_REL<<2);    // 'h02e, address to set extra parameters (currently just inv_clk_div)
-    
-    localparam BASEADDR_REFRESH_EN =   BASEADDR_CTRL | (REFRESH_EN_REL<<2);    // address to enable('h31) and disable ('h30) DDR refresh
-    localparam BASEADDR_REFRESH_PER =   BASEADDR_CTRL | (REFRESH_PER_REL<<2);    // address ('h32) to set refresh period in 32 x tCK
-    localparam BASEADDR_REFRESH_ADDR =   BASEADDR_CTRL | (REFRESH_ADDR_REL<<2);    // address ('h33)to set sequencer start address for DDR refresh
-    
-    
-    localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;  
-    localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);  
-    localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);  
-    localparam BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+('h30<<2);  
-
-    localparam BASEADDRESS_CMDA  = BASEADDR_DLY_LD+('h40<<2);
-    localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
-    localparam STATUS_PSHIFTER_RDY_MASK = 'h100;
-// SuppressWarnings VEditor - not yet used
-    localparam STATUS_LOCKED_MASK = 'h200;
-    localparam STATUS_SEQ_BUSY_MASK = 'h400;
-*/
 `ifdef use200Mhz
     localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
     localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs

includes/x393_tasks01.vh

@@ -16,6 +16,13 @@
         end
     endtask
 
+    task read_and_wait_w;
+    input [29:0] address;
+        begin
+            read_and_wait ({address,2'b0});
+        end
+    endtask
+
     task read_and_wait;
     input [31:0] address;
     begin
@@ -32,6 +39,14 @@
     end
     endtask
     
+    task axi_write_single_w; // address in bytes, not words
+        input [29:0] address;
+        input [31:0] data;
+        begin
+            axi_write_single ({address,2'b0},data);
+        end
+    endtask
+
     task axi_write_single; // address in bytes, not words
         input [31:0] address;
         input [31:0] data;

memctrl/mcntrl393.v

@@ -251,6 +251,7 @@ module  mcntrl393 #(
     input                        axird_regen, //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
 //   wire  [31:0]   axird_bram_rdata;  //      .data_out(rdata[31:0]),       // data out
     output              [31:0]   axird_rdata,  // combinatorial multiplexed (add external register layer, modify axibram_read?)     .data_out(rdata[31:0]),       // data out
+    output                       axird_selected, // axird_rdata contains cvalid data from this module 
 //   wire  [31:0]   port0_rdata;  //
 //   wire  [31:0]   status_rdata;  //
 
@@ -415,7 +416,14 @@ module  mcntrl393 #(
     wire                        status_tiled_chn4_rq;    // PS tiled channel4 (memory read) channels status request  
     wire                        status_tiled_chn4_start; // PS tiled channel4 (memory read) channels status packet transfer start (currently with 0 latency from status_root_rq)
 
-
+// combinatorial early signals
+    wire                         select_cmd0_w;
+    wire                         select_buf0_w;
+    wire                         select_buf1_w;
+    wire                         select_buf2_w;
+    wire                         select_buf3_w;
+    wire                         select_buf4_w;
+// registered selects
     reg                         select_cmd0;
     reg                         select_buf0;
     reg                         select_buf1;
@@ -427,7 +435,7 @@ module  mcntrl393 #(
     reg                         select_buf2_d;
     reg                         select_buf4_d;
 
-    
+    reg                         axird_selected_r; // this module provides output
     
 // Buffers R/W from AXI
     reg   [BUFFER_DEPTH32-1:0]  buf_waddr;
@@ -513,7 +521,7 @@ module  mcntrl393 #(
 
     
     
-// Ror now - combinatorial, maybe add registers (modify axibram_read)
+// For now - combinatorial, maybe add registers (modify axibram_read)
     assign buf_raddr=axird_raddr;    
     assign axird_rdata = (select_buf0 ? buf0_data : 32'b0) | (select_buf2 ? buf2_data : 32'b0) | (select_buf4 ? buf4_data : 32'b0); 
     
@@ -527,25 +535,37 @@ module  mcntrl393 #(
     assign page_ready_chn2=seq_done2;
     assign page_ready_chn3=seq_done3;
     assign page_ready_chn4=rpage_nxt_chn4;
+    
+    
+    assign axird_selected=axird_selected_r;
+    assign select_cmd0_w = ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
+    assign select_buf0_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
+    assign select_buf1_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
+    assign select_buf2_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
+    assign select_buf3_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
+    assign select_buf4_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
 
     always @ (axi_rst or axi_clk) begin
         if      (axi_rst)           select_cmd0 <= 0;
-        else if (axiwr_start_burst) select_cmd0 <= ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
+        else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
         
         if      (axi_rst)           select_buf0 <= 0;
-        else if (axird_start_burst) select_buf0 <= ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
+        else if (axird_start_burst) select_buf0 <= select_buf0_w;
         
         if      (axi_rst)           select_buf1 <= 0;
-        else if (axiwr_start_burst) select_buf1 <= ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
+        else if (axiwr_start_burst) select_buf1 <= select_buf1_w;
         
         if      (axi_rst)           select_buf2 <= 0;
-        else if (axird_start_burst) select_buf2 <= ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
+        else if (axird_start_burst) select_buf2 <= select_buf2_w;
         
         if      (axi_rst)           select_buf3 <= 0;
-        else if (axiwr_start_burst) select_buf3 <= ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
+        else if (axiwr_start_burst) select_buf3 <= select_buf3_w;
         
         if      (axi_rst)           select_buf4 <= 0;
-        else if (axird_start_burst) select_buf4 <= ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
+        else if (axird_start_burst) select_buf4 <= select_buf4_w;
+
+        if      (axi_rst)           axird_selected_r <= 0;
+        else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf1_w ||select_buf2_w;
     end
     always @ (axi_clk) begin
         if (axiwr_wen) buf_wdata  <= axiwr_data;

status_read.v

@@ -36,10 +36,18 @@ module  status_read#(
 )(
     input rst,
     input clk,
-    input [AXI_RD_ADDR_BITS-1:0] axi_pre_addr,     // status read address, 1 cycle ahead of read data
-    input                        pre_stb,          // read data request, with axi_pre_addr
-    output reg            [31:0] axi_status_rdata, // read data, 1 cycle latency from the address/stb
-    output reg                   data_valid,       // read data valid, 1 cycle latency from pre_stb, decoded address
+    input                        axi_clk,   // common for read and write channels
+    input [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr,     // status read address, 1 cycle ahead of read data
+//    input                        pre_stb,          // read data request, with axi_pre_addr
+//    output reg            [31:0] axi_status_rdata, // read data, 1 cycle latency from the address/stb
+//    output reg                   data_valid,       // read data valid, 1 cycle latency from pre_stb, decoded address
+    input                        axird_start_burst, // start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer
+    input     [STATUS_DEPTH-1:0] axird_raddr, //   .raddr(read_in_progress?read_address[9:0]:10'h3ff),    // read address
+    input                        axird_ren,   //      .ren(bram_reg_re_w) ,      // read port enable
+    input                        axird_regen, //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
+    output              [31:0]   axird_rdata,  // combinatorial multiplexed (add external register layer, modify axibram_read?)     .data_out(rdata[31:0]),       // data out
+    output                       axird_selected, // axird_rdata contains cvalid data from this module, vcalid next after axird_start_burst
+                                                 // so with ren/regen it may be delayed 1 more cycle
     input                  [7:0] ad,               // byte-serial status data from the sources
     input                        rq,               // request from sources to transfer status data
     output                       start             // acknowledge receiving of first byte (address), currently always ready
@@ -47,20 +55,61 @@ module  status_read#(
     localparam integer DATA_2DEPTH=(1<<STATUS_DEPTH)-1;
     reg  [31:0] ram [0:DATA_2DEPTH];
     reg         [STATUS_DEPTH-1:0] waddr;
-    wire        [STATUS_DEPTH-1:0] raddr;
+//    wire        [STATUS_DEPTH-1:0] raddr;
     reg                          we;
-    wire                         re;
+//    wire                         re;
     reg                  [31: 0] wdata;
     reg                          rq_r;
     reg                   [3:0]  dstb;
     
-    assign re= pre_stb && (((axi_pre_addr ^ STATUS_ADDR) & STATUS_ADDR_MASK) == 0);
-    assign raddr=axi_pre_addr[STATUS_DEPTH-1:0];
+    wire                         select_w;
+    reg                          select_r;
+    reg                          select_d;
+    
+    wire                         rd;
+    wire                         regen;
+    reg                 [31:0]   axi_status_rdata; 
+    reg                 [31:0]   axi_status_rdata_r;
+    
+// registering to match BRAM timing (so it is possible to instantioate it instead)    
+//    reg       [STATUS_DEPTH-1:0] raddr_r; //   .raddr(read_in_progress?read_address[9:0]:10'h3ff),    // read address
+//    reg                          rd_r;   //      .ren(bram_reg_re_w) ,      // read port enable
+//    reg                          regen_r; //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
+   
+    
+    
+    assign select_w = ((axird_pre_araddr ^ STATUS_ADDR) & STATUS_ADDR_MASK)==0;
+    assign rd =        axird_ren   && select_r;
+    assign regen =     axird_regen && select_d;
+    
+    
+    
+    
+//    assign re= pre_stb && (((axi_pre_addr ^ STATUS_ADDR) & STATUS_ADDR_MASK) == 0);
+//    assign raddr=axi_pre_addr[STATUS_DEPTH-1:0];
     assign start=rq && !rq_r;
+    assign axird_rdata=axi_status_rdata_r;
+    assign axird_selected = select_r; 
+    always @ (posedge rst or posedge axi_clk) begin
+        if      (rst)               select_r <= 0;
+        else if (axird_start_burst) select_r <= select_w;
+    end
+    always @ (posedge axi_clk) begin
+//        if (rd_r)     axi_status_rdata <= ram[raddr_r];
+//        if (regen_r)  axi_status_rdata_r <= axi_status_rdata;
+        if (rd)       axi_status_rdata <= ram[axird_raddr];
+        if (regen)    axi_status_rdata_r <= axi_status_rdata;
+        
+        select_d <=   select_r;
+//        raddr_r <=   axird_raddr;
+//        rd_r <=      rd;
+//        regen_r <=   regen;
+    end
     
     always @ (posedge rst or posedge clk) begin
-        if (rst) data_valid <= 0;
-        else     data_valid <= re;
+    
+//        if (rst) data_valid <= 0;
+//        else     data_valid <= re;
         
         if (rst) rq_r <= 0;
         else     rq_r <= rq;
@@ -99,8 +148,7 @@ module  status_read#(
     end
     
     always @ (posedge clk) begin
-        if (we)  ram[waddr]  <= wdata; // shifted data here
-        if (re)  axi_status_rdata<= ram[raddr];
+        if (we)     ram[waddr]  <= wdata; // shifted data here
     end
                              
 

util_modules/status_router2.v

@@ -70,7 +70,8 @@ module  status_router2 (
 ///    assign snd_pre_start=|fifo_nempty && !snd_rest_r && !start_out; // no channel change after 
 //    assign rq_out=(snd_rest_r && !snd_last_byte) || |fifo_nempty;
     assign rq_out=(snd_rest_r || |fifo_nempty) && !snd_last_byte ;
-    assign early_chn= (snd_rest_r & ~snd_last_byte)?current_chn_r:chn_sel_w;
+//    assign early_chn= (snd_rest_r & ~snd_last_byte)?current_chn_r:chn_sel_w;
+    assign early_chn= snd_rest_r? current_chn_r: chn_sel_w;
     assign db_out=early_chn?fifo1_out:fifo0_out;
     assign fifo_nempty=fifo_nempty_pre & ~fifo_last_byte;
     

x393.v

@@ -349,21 +349,25 @@ module  x393 #(
    wire  [31:0]   axird_rdata;  //      .data_out(rdata[31:0]),       // data out
 //   wire  [31:0]   port0_rdata;  //
    wire  [31:0]   status_rdata;  //
-   wire           status_valid; /// SuppressThisWarning VEditor ****** never used - supposed to be always valid?
+   wire           status_selected;
+   wire  [31:0]   mcntrl_axird_rdata; // read data from the memory controller 
+   wire           mcntrl_axird_selected; // memory controoler has valid data output on mcntrl_axird_rdata 
 
    wire        mclk;
 
    wire [11:0] tmp_debug; 
    
 //   reg    select_port0; // May be used later!
-   reg  select_status;
    wire axiwr_dev_busy;
    wire axird_dev_busy;
    
    assign axird_dev_ready = ~axird_dev_busy; //may combine (AND) multiple sources if needed
    assign axird_dev_busy = 1'b0; // always for now
-//   assign axird_rdata= select_port0? port0_rdata[31:0]:(select_status?status_rdata[31:0]:32'bx);
-   assign axird_rdata= select_status?status_rdata[31:0]:32'bx;
+// Use this later    
+//   assign axird_rdata= ({32{status_selected}} & status_rdata[31:0]) | ({32{mcntrl_axird_selected}} & mcntrl_axird_rdata[31:0]);
+//Debug with this (to show 'x)   
+   assign axird_rdata= status_selected?status_rdata[31:0] : (mcntrl_axird_selected? mcntrl_axird_rdata[31:0]:'bx);
+   
    assign axiwr_dev_ready = ~axiwr_dev_busy; //may combine (AND) multiple sources if needed
 
 // Clock and reset from PS
@@ -378,17 +382,6 @@ module  x393 #(
 BUFG bufg_axi_rst_i   (.O(axi_rst),.I(axi_rst_pre));
 BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
    
-//always @ (posedge axi_aclk) begin
-//   port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
-//end
-
-always @ (posedge axi_rst or posedge axi_aclk) begin
- //   if (axi_rst) select_port0 <= 1'b0;
- //   else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
-    if (axi_rst) select_status <= 1'b0;
-    else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
-    
-end
 
 `ifdef DEBUG_FIFO
         wire    waddr_under, wdata_under, wresp_under; 
@@ -593,15 +586,18 @@ end
     ) status_read_i (
         .rst              (axi_rst), // input
         .clk              (mclk), // input
-        .axi_pre_addr     (axird_pre_araddr), // input[12:0] 
-        .pre_stb          (axird_start_burst), // input
-        .axi_status_rdata (status_rdata[31:0]), // output[31:0] reg 
-        .data_valid       (status_valid), // output reg 
+        .axi_clk          (axird_bram_rclk), // input == axi_aclk
+        .axird_pre_araddr (axird_pre_araddr), // input[7:0] 
+        .axird_start_burst(axird_start_burst), // input
+        .axird_raddr      (axird_raddr[STATUS_DEPTH-1:0]), // input[7:0] 
+        .axird_ren        (axird_ren), // input
+        .axird_regen      (axird_regen), // input
+        .axird_rdata      (status_rdata), // output[31:0] 
+        .axird_selected   (status_selected), // output
         .ad               (status_root_ad), // input[7:0] 
         .rq               (status_root_rq), // input
         .start            (status_root_start) // output
     );
-    
 
 // mux status info from the memory controller and other modules    
     status_router2 status_router2_top_i (
@@ -748,7 +744,7 @@ end
         .status_rq            (status_mcontr_rq),   // input request to send status downstream
         .status_start         (status_mcontr_start), // Acknowledge of the first status packet byte (address)
         
-        .axi_clk              (axi_aclk), // input - same?
+        .axi_clk              (axird_bram_rclk), // axi_aclk), // input - same?
         .axiwr_pre_awaddr     (axiwr_pre_awaddr), // input[12:0] 
         .axiwr_start_burst    (axiwr_start_burst), // input
         .axiwr_waddr          (axiwr_waddr[BUFFER_DEPTH32-1:0]), // input[9:0] 
@@ -760,8 +756,8 @@ end
         .axird_raddr          (axird_raddr[BUFFER_DEPTH32-1:0]), // input[9:0] 
         .axird_ren            (axird_ren), // input
         .axird_regen          (axird_regen), // input
-        .axird_rdata          (axird_rdata), // output[31:0]
- 
+        .axird_rdata          (mcntrl_axird_rdata), // output[31:0]
+        .axird_selected       (mcntrl_axird_selected), // output 
  //TODO:        
         .frame_start_chn2     (frame_start_chn2), // input
         .next_page_chn2       (next_page_chn2), // input
@@ -959,7 +955,7 @@ frst[3]?{
         .pre_araddr  (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0] 
         .start_burst (axird_start_burst), // output
         .dev_ready   (axird_dev_ready), // input
-        .bram_rclk   (axird_bram_rclk), // output //SuppressThisWarning ISExst Assignment to axird_bram_rclk ignored, since the identifier is never used
+        .bram_rclk   (axird_bram_rclk), // output //S uppressThisWarning ISExst Assignment to axird_bram_rclk ignored, since the identifier is never used
         .bram_raddr  (axird_raddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0] 
         .bram_ren    (axird_ren), // output
         .bram_regen  (axird_regen), // output