Commit 9a7406b4 authored by Andrey Filippov's avatar Andrey Filippov

synchromized molre frame parameter transitions

parent 4bb4f227
This diff is collapsed.
...@@ -68,6 +68,9 @@ module cmprs_frame_sync#( ...@@ -68,6 +68,9 @@ module cmprs_frame_sync#(
output frame_start_dst, // @mclk - trigger receive (tiled) memory channel (it will take care of single/repetitive output frame_start_dst, // @mclk - trigger receive (tiled) memory channel (it will take care of single/repetitive
// this output either follows vsync_late (reclocks it) or generated in non-bonded mode // this output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory) // (compress from memory)
input frame_start_conf, // memory controller confirmed frame_start_dst - normally delayed by 1 clock,
// or more if there were outstanding memory transactions.
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?) input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
input frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
...@@ -77,7 +80,8 @@ module cmprs_frame_sync#( ...@@ -77,7 +80,8 @@ module cmprs_frame_sync#(
input [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line in this (compressor) channel input [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line in this (compressor) channel
input [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges) in this (compressor channel input [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges) in this (compressor channel
input frames_in_sync, // frame number in destination memory channel is valid for bonded mode input frames_in_sync, // frame number in destination memory channel is valid for bonded mode
input frame_done, // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input frame_done, // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory\
input last_mb_started, // @ xclk - last mb started running, safe to assume memory channel is done
output reg suspend, // suspend reading data for this channel - waiting for the source data output reg suspend, // suspend reading data for this channel - waiting for the source data
input stuffer_running, // @xclk2x stuffer is running/flushing input stuffer_running, // @xclk2x stuffer is running/flushing
...@@ -115,6 +119,7 @@ module cmprs_frame_sync#( ...@@ -115,6 +119,7 @@ module cmprs_frame_sync#(
reg cmprs_en_d; reg cmprs_en_d;
reg suspend_end; // suspend at the end of the current frame until frame number changes reg suspend_end; // suspend at the end of the current frame until frame number changes
// reg cmprs_en_xclk; // reg cmprs_en_xclk;
wire last_mb_started_mclk;
assign frame_start_dst = frame_start_dst_r[0]; assign frame_start_dst = frame_start_dst_r[0];
assign cmprs_en_extend = cmprs_en_extend_r; assign cmprs_en_extend = cmprs_en_extend_r;
...@@ -128,6 +133,7 @@ module cmprs_frame_sync#( ...@@ -128,6 +133,7 @@ module cmprs_frame_sync#(
if (mrst) cmprs_en_extend_r <= 0; if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1; else if (cmprs_en) cmprs_en_extend_r <= 1;
else if ((timeout == 0) || !stuffer_running_mclk_r) cmprs_en_extend_r <= 0; else if ((timeout == 0) || !stuffer_running_mclk_r) cmprs_en_extend_r <= 0;
end end
always @ (posedge mclk) begin always @ (posedge mclk) begin
...@@ -139,21 +145,21 @@ module cmprs_frame_sync#( ...@@ -139,21 +145,21 @@ module cmprs_frame_sync#(
cmprs_en_d <= cmprs_en; cmprs_en_d <= cmprs_en;
/// broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse // broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r; aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0; if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
/// else if (broken_frame || aborted_frame) force_flush_long <= 1; // else if (broken_frame || aborted_frame) force_flush_long <= 1;
else if (aborted_frame) force_flush_long <= 1; else if (aborted_frame) force_flush_long <= 1;
// if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
/// if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0; // last_mb_start[2] is used as emergency turn off reading_frame if memory channel did not generate frame_done (i.e. wrong frame height)
if (!cmprs_en || frame_done ) reading_frame_r <= 0; // TODO: Consider the opposite - frame_done, but not got the last MB?
if (!cmprs_en || frame_done || last_mb_started_mclk) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1; else if (frame_started_mclk) reading_frame_r <= 1;
// if (!cmprs_en || frame_start_dst_r[0]) frame_start_pend_r <= 0; // if (!cmprs_run || frame_start_dst_r[0]) frame_start_pend_r <= 0;
if (!cmprs_run || frame_start_dst_r[0]) frame_start_pend_r <= 0; if (!cmprs_run || frame_start_conf) frame_start_pend_r <= 0;
// else if (cmprs_run && vsync_late && reading_frame_r) frame_start_pend_r <= 1;
else if ((cmprs_run && vsync_late && reading_frame_r) || else if ((cmprs_run && vsync_late && reading_frame_r) ||
(frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1; (frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1;
// else if (frame_start_dst_r[0]) frame_start_pend_r <= 0; // else if (frame_start_dst_r[0]) frame_start_pend_r <= 0;
...@@ -168,8 +174,10 @@ module cmprs_frame_sync#( ...@@ -168,8 +174,10 @@ module cmprs_frame_sync#(
frame_start_dst_r[0] <= cmprs_en && (cmprs_run ? frame_start_dst_r[0] <= cmprs_en && (cmprs_run ?
((vsync_late && !reading_frame_r) || (frame_start_pend_r && frame_done)): ((vsync_late && !reading_frame_r) || (frame_start_pend_r && frame_done)):
cmprs_standalone); cmprs_standalone);
// modified - now bit 0 is disconnected from 1..5, 1 gets from memory channel controller, may be delayed
if (!cmprs_en) frame_start_dst_r[5:1] <=0; if (!cmprs_en) frame_start_dst_r[5:1] <=0;
else frame_start_dst_r[5:1] <= frame_start_dst_r[4:0]; // else frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];
else frame_start_dst_r[5:1] <= {frame_start_dst_r[4:1],frame_start_conf};
if (!cmprs_en) bonded_mode <= 0; if (!cmprs_en) bonded_mode <= 0;
else if (cmprs_run) bonded_mode <= 1; else if (cmprs_run) bonded_mode <= 1;
...@@ -188,6 +196,8 @@ module cmprs_frame_sync#( ...@@ -188,6 +196,8 @@ module cmprs_frame_sync#(
// pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy()); // pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy()); pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
pulse_cross_clock last_mb_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(last_mb_started), .out_pulse(last_mb_started_mclk),.busy());
endmodule endmodule
...@@ -169,6 +169,8 @@ module compressor393 # ( ...@@ -169,6 +169,8 @@ module compressor393 # (
output [3:0] frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive output [3:0] frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory) // (compress from memory)
input [3:0] frame_start_conf, // memory controller confirmed frame_start_dst - normally delayed by 1 clock,
// or more if there were outstanding memory transactions.
input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?) input [4*FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [4*LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel input [4*LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
input [3:0] frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input [3:0] frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
...@@ -438,6 +440,7 @@ module compressor393 # ( ...@@ -438,6 +440,7 @@ module compressor393 # (
.next_page_chn (next_page[i]), // output .next_page_chn (next_page[i]), // output
.frame_start_dst (frame_start_dst[i]), // output .frame_start_dst (frame_start_dst[i]), // output
.frame_start_conf (frame_start_conf[i]), // input
.line_unfinished_src (line_unfinished_src[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0] .line_unfinished_src (line_unfinished_src[FRAME_HEIGHT_BITS * i +: FRAME_HEIGHT_BITS]), // input[15:0]
.frame_number_src (frame_number_src[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0] .frame_number_src (frame_number_src[LAST_FRAME_BITS * i +: LAST_FRAME_BITS]), // input[15:0]
.frame_done_src (frame_done_src[i]), // input .frame_done_src (frame_done_src[i]), // input
......
...@@ -155,6 +155,9 @@ module jp_channel#( ...@@ -155,6 +155,9 @@ module jp_channel#(
output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// this output either follows vsync_late (reclocks it) or generated in non-bonded mode // this output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory) // (compress from memory)
input frame_start_conf, // memory controller confirmed frame_start_dst - normally delayed by 1 clock,
// or more if there were outstanding memory transactions.
input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?) input [FRAME_HEIGHT_BITS-1:0] line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel input [LAST_FRAME_BITS-1:0] frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
input frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory input frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
...@@ -582,7 +585,8 @@ module jp_channel#( ...@@ -582,7 +585,8 @@ module jp_channel#(
.rst (!cmprs_en_mclk), .rst (!cmprs_en_mclk),
.src_clk (mclk), .src_clk (mclk),
.dst_clk (hclk), .dst_clk (hclk),
.in_pulse (frame_start_dst), // .in_pulse (frame_start_dst),
.in_pulse (frame_start_conf),
.out_pulse (dbg_frame_start_hclk), .out_pulse (dbg_frame_start_hclk),
.busy ()); .busy ());
...@@ -725,7 +729,8 @@ module jp_channel#( ...@@ -725,7 +729,8 @@ module jp_channel#(
.color_sat_we (set_color_saturation_w), // input - write color saturation values .color_sat_we (set_color_saturation_w), // input - write color saturation values
.coring_we (set_coring_w), // input - write color saturation values .coring_we (set_coring_w), // input - write color saturation values
.di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used) .di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used)
.frame_start (frame_start_dst), // input @mclk // .frame_start (frame_start_dst), // input @mclk
.frame_start (frame_start_conf), // input @mclk
.frame_start_xclk (frame_start_xclk), // output re-clocked, parameters are copied during this pulse .frame_start_xclk (frame_start_xclk), // output re-clocked, parameters are copied during this pulse
.cmprs_en_mclk (cmprs_en_mclk), // output .cmprs_en_mclk (cmprs_en_mclk), // output
.cmprs_en_extend (cmprs_en_extend), // input .cmprs_en_extend (cmprs_en_extend), // input
...@@ -796,6 +801,8 @@ module jp_channel#( ...@@ -796,6 +801,8 @@ module jp_channel#(
.frame_start_dst (frame_start_dst), // output reg @mclk - trigger receive (tiled) memory channel (it will take care of .frame_start_dst (frame_start_dst), // output reg @mclk - trigger receive (tiled) memory channel (it will take care of
// single/repetitive modes itself this output either follows vsync_late (reclocks it) // single/repetitive modes itself this output either follows vsync_late (reclocks it)
// or generated in non-bonded mode (compress from memory once) // or generated in non-bonded mode (compress from memory once)
.frame_start_conf (frame_start_conf), // input: memory controller confirmed cmprs_frame_start_dst - normally delayed by 1 clock,
// or more if there were outstanding memory transactions.
.line_unfinished_src(line_unfinished_src), // input[15:0] - number of the current (unfinished ) line, in the source (sensor) channel .line_unfinished_src(line_unfinished_src), // input[15:0] - number of the current (unfinished ) line, in the source (sensor) channel
.frame_number_src (frame_number_src), // input[15:0] - current frame number (for multi-frame ranges) in the source (sensor) channel .frame_number_src (frame_number_src), // input[15:0] - current frame number (for multi-frame ranges) in the source (sensor) channel
.frame_done_src (frame_done_src), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory .frame_done_src (frame_done_src), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
...@@ -804,7 +811,8 @@ module jp_channel#( ...@@ -804,7 +811,8 @@ module jp_channel#(
.line_unfinished (line_unfinished_dst), // input[15:0] - number of the current (unfinished ) line in this (compressor) channel .line_unfinished (line_unfinished_dst), // input[15:0] - number of the current (unfinished ) line in this (compressor) channel
.frame_number (frame_number_dst), // input[15:0] - current frame number (for multi-frame ranges) in this (compressor channel .frame_number (frame_number_dst), // input[15:0] - current frame number (for multi-frame ranges) in this (compressor channel
.frames_in_sync (frames_in_sync), // frame number in destination memory channel is valid for bonded mode .frames_in_sync (frames_in_sync), // frame number in destination memory channel is valid for bonded mode
.frame_done (frame_done_dst), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory .frame_done (frame_done_dst), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
.last_mb_started (last_mb && mb_pre2_first_out), // input
.suspend (suspend), // output reg - suspend reading data for this channel - waiting for the source data .suspend (suspend), // output reg - suspend reading data for this channel - waiting for the source data
.stuffer_running (stuffer_running), // input .stuffer_running (stuffer_running), // input
.force_flush_long (force_flush_long), // output reg - @ mclk tried to start frame compression before the previous one was finished .force_flush_long (force_flush_long), // output reg - @ mclk tried to start frame compression before the previous one was finished
......
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h039300ae; // parallel, increasing sesnsor-channels maximal delays to 12 bits parameter FPGA_VERSION = 32'h039300ae; // parallel, increasing sesnsor-channels maximal delays to 12 bits -0.091/25, 79.89%
// parameter FPGA_VERSION = 32'h039300ad; // parallel, resetting frame_pre_run. All met, 79.97% // parameter FPGA_VERSION = 32'h039300ad; // parallel, resetting frame_pre_run. All met, 79.97%
// parameter FPGA_VERSION = 32'h039300ac; // parallel, adding reset needed_page in compressor -0.012 (2), 79.39% // parameter FPGA_VERSION = 32'h039300ac; // parallel, adding reset needed_page in compressor -0.012 (2), 79.39%
// parameter FPGA_VERSION = 32'h039300ab; // parallel, more on frame sync in compressor All met, 79.04% // parameter FPGA_VERSION = 32'h039300ab; // parallel, more on frame sync in compressor All met, 79.04%
......
...@@ -298,6 +298,7 @@ ...@@ -298,6 +298,7 @@
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode) parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse
......
...@@ -262,6 +262,7 @@ module mcntrl393 #( ...@@ -262,6 +262,7 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode) parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
...@@ -343,6 +344,7 @@ module mcntrl393 #( ...@@ -343,6 +344,7 @@ module mcntrl393 #(
input [3:0] cmprs_frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive input [3:0] cmprs_frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory) // (compress from memory)
output [3:0] cmprs_frame_start_conf, // @mclk lags by 1 from cmprs_frame_start_dst, more if there are outstanding memory transactions
output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?) output [4*FRAME_HEIGHT_BITS-1:0] cmprs_line_unfinished_src,// number of the current (unfinished ) line, in the source (sensor) channel (RELATIVE TO FRAME, NOT WINDOW?)
output [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel output [4*LAST_FRAME_BITS-1:0] cmprs_frame_number_src, // current frame number (for multi-frame ranges) in the source (sensor) channel
output [3:0] cmprs_frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory output [3:0] cmprs_frame_done_src, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
...@@ -1116,6 +1118,7 @@ module mcntrl393 #( ...@@ -1116,6 +1118,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT) .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
) mcntrl_linear_wr_sensor_i ( ) mcntrl_linear_wr_sensor_i (
...@@ -1191,7 +1194,9 @@ module mcntrl393 #( ...@@ -1191,7 +1194,9 @@ module mcntrl393 #(
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_COPY_FRAME (MCONTR_LINTILE_COPY_FRAME) .MCONTR_LINTILE_COPY_FRAME (MCONTR_LINTILE_COPY_FRAME),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE)
) mcntrl_tiled_rd_compressor_i ( ) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -1201,6 +1206,7 @@ module mcntrl393 #( ...@@ -1201,6 +1206,7 @@ module mcntrl393 #(
.status_rq (status_cmprs_rq[i]), // output .status_rq (status_cmprs_rq[i]), // output
.status_start (status_cmprs_start[i]), // input .status_start (status_cmprs_start[i]), // input
.frame_start (cmprs_frame_start_dst[i]), // input .frame_start (cmprs_frame_start_dst[i]), // input
.frame_start_conf (cmprs_frame_start_conf[i]), // output
.next_page (cmprs_next_page[i]), // input compressor consumed page cmprs_buf_wpage_nxt? .next_page (cmprs_next_page[i]), // input compressor consumed page cmprs_buf_wpage_nxt?
.frame_done (cmprs_frame_done_dst[i]), // output .frame_done (cmprs_frame_done_dst[i]), // output
.frame_finished (), // output .frame_finished (), // output
...@@ -1270,6 +1276,7 @@ module mcntrl393 #( ...@@ -1270,6 +1276,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT) .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
...@@ -1345,6 +1352,7 @@ module mcntrl393 #( ...@@ -1345,6 +1352,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT) .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
) mcntrl_linear_rw_chn3_i ( ) mcntrl_linear_rw_chn3_i (
...@@ -1418,7 +1426,8 @@ module mcntrl393 #( ...@@ -1418,7 +1426,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME), .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED) .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE)
) mcntrl_tiled_rw_chn2_i ( ) mcntrl_tiled_rw_chn2_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -1428,6 +1437,7 @@ module mcntrl393 #( ...@@ -1428,6 +1437,7 @@ module mcntrl393 #(
.status_rq (status_tiled_chn2_rq), // output .status_rq (status_tiled_chn2_rq), // output
.status_start (status_tiled_chn2_start), // input .status_start (status_tiled_chn2_start), // input
.frame_start (frame_start_chn2), // input .frame_start (frame_start_chn2), // input
.frame_start_conf (), // output
.next_page (next_page_chn2), // input .next_page (next_page_chn2), // input
.frame_done (frame_done_chn2), // output .frame_done (frame_done_chn2), // output
.frame_finished (), // output .frame_finished (), // output
...@@ -1490,7 +1500,8 @@ module mcntrl393 #( ...@@ -1490,7 +1500,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME), .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED) .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE)
) mcntrl_tiled_rw_chn4_i ( ) mcntrl_tiled_rw_chn4_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -1500,6 +1511,7 @@ module mcntrl393 #( ...@@ -1500,6 +1511,7 @@ module mcntrl393 #(
.status_rq (status_tiled_chn4_rq), // output .status_rq (status_tiled_chn4_rq), // output
.status_start (status_tiled_chn4_start), // input .status_start (status_tiled_chn4_start), // input
.frame_start (frame_start_chn4), // input .frame_start (frame_start_chn4), // input
.frame_start_conf (), // output
.next_page (next_page_chn4), // input .next_page (next_page_chn4), // input
.frame_done (frame_done_chn4), // output .frame_done (frame_done_chn4), // output
.frame_finished (), // output .frame_finished (), // output
......
...@@ -78,6 +78,7 @@ module mcntrl_linear_rw #( ...@@ -78,6 +78,7 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the // TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive - // first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
...@@ -176,9 +177,11 @@ module mcntrl_linear_rw #( ...@@ -176,9 +177,11 @@ module mcntrl_linear_rw #(
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
// SuppressWarnings VEditor unused // SuppressWarnings VEditor unused
wire calc_valid; // calculated registers have valid values wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channel (continue ones in progress), enable frame_start_late inputs wire chn_en; // enable requests by channel (continue ones in progress), enable frame_start_late inputs
wire chn_rst; // resets command, including fifo; wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off reg chn_rst_d; // delayed by 1 cycle do detect turning off
wire abort_en; // enable frame abort (mode register bit)
reg aborting_r; // waiting pending memory transactions at if the frame was not finished at frame sync
// reg xfer_reset_page_r; // reg xfer_reset_page_r;
reg xfer_page_rst_r=1; reg xfer_page_rst_r=1;
reg xfer_page_rst_pos=1; reg xfer_page_rst_pos=1;
...@@ -199,6 +202,7 @@ module mcntrl_linear_rw #( ...@@ -199,6 +202,7 @@ module mcntrl_linear_rw #(
reg busy_r; reg busy_r;
reg want_r; reg want_r;
reg want_d; // want_r delayed (no gap to pending_xfers)
reg need_r; reg need_r;
reg frame_done_r; reg frame_done_r;
reg frame_finished_r; reg frame_finished_r;
...@@ -232,7 +236,7 @@ module mcntrl_linear_rw #( ...@@ -232,7 +236,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [12:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset} reg [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0 reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0 reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
...@@ -262,6 +266,8 @@ module mcntrl_linear_rw #( ...@@ -262,6 +266,8 @@ module mcntrl_linear_rw #(
wire set_start_delay_w; wire set_start_delay_w;
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4 // if total number of pages in a frame is not multiple of 4
// wire
assign frame_number = frame_number_current; assign frame_number = frame_number_current;
...@@ -284,7 +290,7 @@ module mcntrl_linear_rw #( ...@@ -284,7 +290,7 @@ module mcntrl_linear_rw #(
// Set parameter registers // Set parameter registers
always @(posedge mclk) begin always @(posedge mclk) begin
if (mrst) mode_reg <= 0; if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[12:0]; // 4:0]; // [4:0]; else if (set_mode_w) mode_reg <= cmd_data[14:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0; if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w; else single_frame_r <= single_frame_w;
...@@ -393,7 +399,7 @@ module mcntrl_linear_rw #( ...@@ -393,7 +399,7 @@ module mcntrl_linear_rw #(
// accelerating pre_want: // accelerating pre_want:
// assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ; // assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend ;
// last_block was too late to inclusde in pre_want_r1, moving it here // last_block was too late to inclusde in pre_want_r1, moving it here
assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend && !last_block; assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !suspend && !last_block && !aborting_r;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r}); assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
assign last_row_w= next_y==window_height; assign last_row_w= next_y==window_height;
...@@ -410,6 +416,8 @@ module mcntrl_linear_rw #( ...@@ -410,6 +416,8 @@ module mcntrl_linear_rw #(
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT]; assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED]; assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE]; assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit? assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we; assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0; localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
...@@ -439,7 +447,6 @@ module mcntrl_linear_rw #( ...@@ -439,7 +447,6 @@ module mcntrl_linear_rw #(
always @(posedge mclk) begin // Handling skip/reject always @(posedge mclk) begin // Handling skip/reject
if (mrst) xfer_reject_r <= 0; if (mrst) xfer_reject_r <= 0;
else xfer_reject_r <= xfer_grant && !chn_rst && skip_run; else xfer_reject_r <= xfer_grant && !chn_rst && skip_run;
if (mrst) xfer_start_r <= 0; if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r}; else xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r};
...@@ -478,6 +485,7 @@ module mcntrl_linear_rw #( ...@@ -478,6 +485,7 @@ module mcntrl_linear_rw #(
if (mrst) want_r <= 0; if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0; else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0;
else if (pre_want && (page_cntr > {1'b0,cmd_extra_pages})) want_r <= 1; else if (pre_want && (page_cntr > {1'b0,cmd_extra_pages})) want_r <= 1;
want_d <= want_r;
end end
...@@ -571,10 +579,15 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -571,10 +579,15 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (frame_start_r[0]) continued_xfer <= 1'b0; else if (frame_start_r[0]) continued_xfer <= 1'b0;
else if (xfer_start_r[0]) continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change else if (xfer_start_r[0]) continued_xfer <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
// single cycle (sent out) // single cycle (sent out), will alos reset busy, set frame_finished, ...
if (mrst) frame_done_r <= 0; if (mrst) frame_done_r <= 0;
else frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0); // else frame_done_r <= busy_r && (last_block || aborting_r) && xfer_done_d && (pending_xfers==0);
else frame_done_r <= busy_r && (pending_xfers==0) &&
((last_block && xfer_done_d) || (aborting_r && !want_r && !want_d));
if (!busy_r) aborting_r <= 0;
else if (abort_en && busy_r && frame_start) aborting_r <= 1; // Early frame start, not delayed
// turns and stays on (used in status) // turns and stays on (used in status)
if (mrst) frame_finished_r <= 0; if (mrst) frame_finished_r <= 0;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0; else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
......
This diff is collapsed.
...@@ -1040,6 +1040,7 @@ MULT_SAXI_IRQLEN_ADDR__RAW = str ...@@ -1040,6 +1040,7 @@ MULT_SAXI_IRQLEN_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
SENS_GAMMA_BUFFER = int
GPIO_SET_PINS__RAW = str GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str AFI_MUX_BUF_LATENCY__RAW = str
...@@ -1505,6 +1506,7 @@ CMPRS_AFIMUX_STATUS_CNTRL = int ...@@ -1505,6 +1506,7 @@ CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_CBIT_FRAMES__RAW = str CMPRS_CBIT_FRAMES__RAW = str
SLEW_DQS = str SLEW_DQS = str
MCONTR_WR_MASK = int MCONTR_WR_MASK = int
MCONTR_LINTILE_ABORT_LATE = int
CMPRS_FRMT_MBCM1 = int CMPRS_FRMT_MBCM1 = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str GPIO_IOSTANDARD__TYPE = str
...@@ -1540,7 +1542,6 @@ LOGGER_PAGE_MSG = int ...@@ -1540,7 +1542,6 @@ LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str INITIALIZE_OFFSET__TYPE = str
SENSOR_FIFO_DELAY__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str LOGGER_CONF_IMU_BITS__TYPE = str
IDELAY_VALUE__TYPE = str IDELAY_VALUE__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str SENSOR_IMAGE_TYPE2__RAW = str
...@@ -1584,6 +1585,7 @@ QUADRANTS_PXD_HACT_VACT__RAW = str ...@@ -1584,6 +1585,7 @@ QUADRANTS_PXD_HACT_VACT__RAW = str
MCONTR_CMPRS_STATUS_INC__RAW = str MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int CMPRS_CBIT_CMODE_JP4DIFFHDR = int
TABLE_CORING_INDEX__RAW = str TABLE_CORING_INDEX__RAW = str
MCONTR_LINTILE_ABORT_LATE__TYPE = str
SENSI2C_CMD_RESET__TYPE = str SENSI2C_CMD_RESET__TYPE = str
MCONTR_ARBIT_ADDR__TYPE = str MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str CAMSYNC_TRIG_DELAY1__RAW = str
...@@ -2103,6 +2105,7 @@ HIST_SAXI_EN = int ...@@ -2103,6 +2105,7 @@ HIST_SAXI_EN = int
RTC_SET_SEC = int RTC_SET_SEC = int
MCONTR_LINTILE_SINGLE__TYPE = str MCONTR_LINTILE_SINGLE__TYPE = str
DLY_DQ_IDELAY__RAW = str DLY_DQ_IDELAY__RAW = str
MCONTR_LINTILE_ABORT_LATE__RAW = str
SENSOR_CTRL_RADDR__RAW = str SENSOR_CTRL_RADDR__RAW = str
CMPRS_MONO16 = int CMPRS_MONO16 = int
REF_JITTER1 = float REF_JITTER1 = float
...@@ -2131,7 +2134,7 @@ HISPI_CAPACITANCE__RAW = str ...@@ -2131,7 +2134,7 @@ HISPI_CAPACITANCE__RAW = str
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
HISPI_DIFF_TERM__RAW = str HISPI_DIFF_TERM__RAW = str
BUF_IPCLK_SENS2__TYPE = str BUF_IPCLK_SENS2__TYPE = str
SENS_GAMMA_BUFFER = int SENSOR_FIFO_DELAY__TYPE = str
CMDFRAMESEQ_ABS__TYPE = str CMDFRAMESEQ_ABS__TYPE = str
NUM_CYCLES_06__RAW = str NUM_CYCLES_06__RAW = str
SENS_JTAG_TDI = int SENS_JTAG_TDI = int
......
...@@ -351,6 +351,7 @@ class X393Cmprs(object): ...@@ -351,6 +351,7 @@ class X393Cmprs(object):
command, command,
reset_frame = False, reset_frame = False,
copy_frame = False, copy_frame = False,
abort_late = False,
verbose = 1): verbose = 1):
""" """
Control memory access (write) of a sensor channel Control memory access (write) of a sensor channel
...@@ -361,7 +362,8 @@ class X393Cmprs(object): ...@@ -361,7 +362,8 @@ class X393Cmprs(object):
single - acquire single frame , single - acquire single frame ,
repetitive - repetitive mode repetitive - repetitive mode
@param reset_frame - reset frame number @param reset_frame - reset frame number
@param copy_frame copy frame number from the master channel (non-persistent) @param copy_frame - copy frame number from the master channel (non-persistent)
@param abort_late - abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
@param vebose - verbose level @param vebose - verbose level
""" """
try: try:
...@@ -372,6 +374,7 @@ class X393Cmprs(object): ...@@ -372,6 +374,7 @@ class X393Cmprs(object):
command = command, command = command,
reset_frame = reset_frame, reset_frame = reset_frame,
copy_frame = copy_frame, copy_frame = copy_frame,
abort_late = abort_late,
verbose = verbose) verbose = verbose)
return return
except: except:
...@@ -410,7 +413,8 @@ class X393Cmprs(object): ...@@ -410,7 +413,8 @@ class X393Cmprs(object):
write_mem = False, write_mem = False,
enable = en, enable = en,
chn_reset = rst, chn_reset = rst,
copy_frame = copy_frame) copy_frame = copy_frame,
abort_late = abort_late)
self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE, mode) self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE, mode)
if verbose > 0 : if verbose > 0 :
...@@ -434,7 +438,8 @@ class X393Cmprs(object): ...@@ -434,7 +438,8 @@ class X393Cmprs(object):
tile_vstep, # = 16 tile_vstep, # = 16
tile_height, #= 18 tile_height, #= 18
extra_pages, extra_pages,
disable_need): disable_need,
abort_late = False):
""" """
Setup memory controller for a compressor channel Setup memory controller for a compressor channel
@param num_sensor - sensor port number (0..3) @param num_sensor - sensor port number (0..3)
...@@ -452,6 +457,7 @@ class X393Cmprs(object): ...@@ -452,6 +457,7 @@ class X393Cmprs(object):
@param tile_height tile height: 18 for color JPEG, 16 fore JP$ flavors, @param tile_height tile height: 18 for color JPEG, 16 fore JP$ flavors,
@param extra_pages extra pages needed (1) @param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sensor channels - they can not wait @param disable_need disable need (preference to sensor channels - they can not wait
@param abort_late abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
""" """
# tile_vstep = 16 # tile_vstep = 16
# tile_height= 18 # tile_height= 18
...@@ -467,7 +473,8 @@ class X393Cmprs(object): ...@@ -467,7 +473,8 @@ class X393Cmprs(object):
extra_pages = extra_pages, extra_pages = extra_pages,
write_mem = False,