started simulation (99191719) · Commits · Elphel / x393

.editor_defines.vh

+4 −0

Original line number	Original line	Diff line number	Diff line
	// This file may be used to define same pre-processor macros to be included into each parsed file		// This file may be used to define same pre-processor macros to be included into each parsed file

			// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
			`define IVERILOG 1

	// It can be used to check different `ifdef branches		// It can be used to check different `ifdef branches
	//`define XIL_TIMING //Simprim		//`define XIL_TIMING //Simprim
	`define den4096Mb 1		`define den4096Mb 1

.settings/com.elphel.vdt.FPGA_project.prefs

+3 −3

Original line number	Original line	Diff line number	Diff line
	FPGA_project_0_SimulationTopFile=ddrc_test01_testbench.tf		FPGA_project_0_SimulationTopFile=x393_testbench01.tf
	FPGA_project_1_SimulationTopModule=ddrc_test01_testbench		FPGA_project_1_SimulationTopModule=x393_testbench01
	FPGA_project_2_ImplementationTopFile=ddrc_test01.v		FPGA_project_2_ImplementationTopFile=x393.v
	FPGA_project_4_part=xc7z030fbg484-1		FPGA_project_4_part=xc7z030fbg484-1
	com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->		com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
	eclipse.preferences.version=1		eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

+2 −1

Original line number	Original line	Diff line number	Diff line
	com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->		com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->
	eclipse.preferences.version=1		eclipse.preferences.version=1
	iverilog_77_Param_Exe=/usr/local/bin/iverilog		iverilog_77_Param_Exe=/usr/local/bin/iverilog
	iverilog_78_VVP_Exe=/usr/local/bin/vvp		iverilog_78_VVP_Exe=/usr/local/bin/vvp
	@@ -6,4 +6,5 @@ iverilog_81_TopModulesOther=glbl<-@\#\#@->
	iverilog_83_ExtraFiles=glbl.v<-@\#\#@->		iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
	iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->/home/andrey/git/x393/includes<-@\#\#@->		iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->/home/andrey/git/x393/includes<-@\#\#@->
	iverilog_88_ShowNoProblem=true		iverilog_88_ShowNoProblem=true
			iverilog_89_ShowNoProblem=true
	iverilog_99_GrepFindErrWarn=error\|warning\|sorry		iverilog_99_GrepFindErrWarn=error\|warning\|sorry

address_map.txt

+24 −7

Original line number	Original line	Diff line number	Diff line
	@@ -104,6 +104,20 @@
	// Read back current address (fro debugging)?		// Read back current address (fro debugging)?
	parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)		parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)

			== test module (8-bit):
			parameter MCNTRL_TEST01_ADDR= 'h0f0,
			parameter MCNTRL_TEST01_MASK= 'h3f0,
			parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
			parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
			parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
			parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
			parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
			parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
			parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
			parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
			parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
			parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4


	// Status read address		// Status read address
	parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers		parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
	@@ -114,7 +128,10 @@
	parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2		parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
	parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,		parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
	parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,		parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
	parameter MCNTRL_TILED_STATUS_REG_CH4_ADDR= 'h5,		parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
			parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
			parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
			parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4

	================================ OLD =======================================================		================================ OLD =======================================================
	Control addresses (in original ddrc_test01)		Control addresses (in original ddrc_test01)

cmd_mux.v

+19 −19

Original line number	Original line	Diff line number	Diff line
	@@ -108,22 +108,22 @@ module cmd_mux #(
	// always @ (seq_length_rom_a) begin		// always @ (seq_length_rom_a) begin
	always @*		always @*
	case (seq_length_rom_a) // just temporary - fill out later		case (seq_length_rom_a) // just temporary - fill out later
	4'h00:seq_length <= NUM_CYCLES_00;		4'h0:seq_length <= NUM_CYCLES_00;
	4'h01:seq_length <= NUM_CYCLES_01;		4'h1:seq_length <= NUM_CYCLES_01;
	4'h02:seq_length <= NUM_CYCLES_02;		4'h2:seq_length <= NUM_CYCLES_02;
	4'h03:seq_length <= NUM_CYCLES_03;		4'h3:seq_length <= NUM_CYCLES_03;
	4'h04:seq_length <= NUM_CYCLES_04;		4'h4:seq_length <= NUM_CYCLES_04;
	4'h05:seq_length <= NUM_CYCLES_05;		4'h5:seq_length <= NUM_CYCLES_05;
	4'h06:seq_length <= NUM_CYCLES_06;		4'h6:seq_length <= NUM_CYCLES_06;
	4'h07:seq_length <= NUM_CYCLES_07;		4'h7:seq_length <= NUM_CYCLES_07;
	4'h08:seq_length <= NUM_CYCLES_08;		4'h8:seq_length <= NUM_CYCLES_08;
	4'h09:seq_length <= NUM_CYCLES_09;		4'h9:seq_length <= NUM_CYCLES_09;
	4'h0a:seq_length <= NUM_CYCLES_10;		4'ha:seq_length <= NUM_CYCLES_10;
	4'h0b:seq_length <= NUM_CYCLES_11;		4'hb:seq_length <= NUM_CYCLES_11;
	4'h0c:seq_length <= NUM_CYCLES_12;		4'hc:seq_length <= NUM_CYCLES_12;
	4'h0d:seq_length <= NUM_CYCLES_13;		4'hd:seq_length <= NUM_CYCLES_13;
	4'h0e:seq_length <= NUM_CYCLES_14;		4'he:seq_length <= NUM_CYCLES_14;
	4'h0f:seq_length <= NUM_CYCLES_15;		4'hf:seq_length <= NUM_CYCLES_15;
	endcase		endcase
	always @ (posedge rst or posedge mclk) begin		always @ (posedge rst or posedge mclk) begin
	if (rst) seq_busy_r<=0;		if (rst) seq_busy_r<=0;
	@@ -137,7 +137,7 @@ module cmd_mux #(
	4'h6: seq_busy_r<=5'h1f;		4'h6: seq_busy_r<=5'h1f;
	default: seq_busy_r<=5'h00;		default: seq_busy_r<=5'h00;
	endcase		endcase
	end else seq_busy_r <= {1'b0,seq_busy_r[3:0]};		end else seq_busy_r <= {1'b0,seq_busy_r[4:1]};
	end		end
	end		end

	@@ -150,7 +150,7 @@ module cmd_mux #(
	end		end
	always @ (posedge mclk) begin		always @ (posedge mclk) begin
	if (start_w) par_ad <={cmdseq_full_r?cseq_wdata_r:wdata_fifo_out,{(16-AXI_WR_ADDR_BITS){1'b0}},cmdseq_full_r?cseq_waddr_r:waddr_fifo_out};		if (start_w) par_ad <={cmdseq_full_r?cseq_wdata_r:wdata_fifo_out,{(16-AXI_WR_ADDR_BITS){1'b0}},cmdseq_full_r?cseq_waddr_r:waddr_fifo_out};
	else par_ad <={8'b0,par_ad[39:0]};		else par_ad <={8'b0,par_ad[47:8]};
	end		end

	assign cseq_ackn= cseq_wr_en && (!cmdseq_full_r \|\| can_start_w); // cmddseq_full has priority over axi, so (can_start_w && cmdseq_full_r)		assign cseq_ackn= cseq_wr_en && (!cmdseq_full_r \|\| can_start_w); // cmddseq_full has priority over axi, so (can_start_w && cmdseq_full_r)
	@@ -173,7 +173,7 @@ module cmd_mux #(
	) fifo_cross_clocks_i (		) fifo_cross_clocks_i (
	.rst (rst), // input		.rst (rst), // input
	.rclk (mclk), // input		.rclk (mclk), // input
	.wclk (clk), // input		.wclk (axi_clk), // input
	.we (wr_en && selected), // input		.we (wr_en && selected), // input
	.re (start_axi_w), // input		.re (start_axi_w), // input
	.data_in ({waddr[AXI_WR_ADDR_BITS-1:0],wdata[31:0]}), // input[15:0]		.data_in ({waddr[AXI_WR_ADDR_BITS-1:0],wdata[31:0]}), // input[15:0]

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