Skip to content

X
x393
Commit 99191719 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

started simulation

parent 575da59a
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 779 additions and 84 deletions
.editor_defines.vh
View file @ 99191719
// This file may be used to define same pre-processor macros to be included into each parsed file
// TODO: Fix VDT - without IVERILOG defined, closure does not include modules needed for Icarus
`define IVERILOG 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
......
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 99191719
FPGA_project_0_SimulationTopFile=ddrc_test01_testbench.tf
FPGA_project_1_SimulationTopModule=ddrc_test01_testbench
FPGA_project_2_ImplementationTopFile=ddrc_test01.v
FPGA_project_0_SimulationTopFile=x393_testbench01.tf
FPGA_project_1_SimulationTopModule=x393_testbench01
FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ 99191719
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->
eclipse.preferences.version=1
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
......@@ -6,4 +6,5 @@ iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->/home/andrey/git/x393/includes<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry
address_map.txt
View file @ 99191719
......@@ -104,17 +104,34 @@
// Read back current address (fro debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
== test module (8-bit):
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h3f0,
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
// Status read address
parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
parameter STATUS_ADDR_MASK = 'h1400, // AXI write address of status registers
parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CH4_ADDR= 'h5,
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0,//8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1,//8 or less bits: status register address to use for memory controller
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
parameter MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e // status/readback register for channel 4
================================ OLD =======================================================
Control addresses (in original ddrc_test01)
......
cmd_mux.v
View file @ 99191719
......@@ -108,22 +108,22 @@ module cmd_mux #(
// always @ (seq_length_rom_a) begin
always @*
case (seq_length_rom_a) // just temporary - fill out later
4'h00:seq_length <= NUM_CYCLES_00;
4'h01:seq_length <= NUM_CYCLES_01;
4'h02:seq_length <= NUM_CYCLES_02;
4'h03:seq_length <= NUM_CYCLES_03;
4'h04:seq_length <= NUM_CYCLES_04;
4'h05:seq_length <= NUM_CYCLES_05;
4'h06:seq_length <= NUM_CYCLES_06;
4'h07:seq_length <= NUM_CYCLES_07;
4'h08:seq_length <= NUM_CYCLES_08;
4'h09:seq_length <= NUM_CYCLES_09;
4'h0a:seq_length <= NUM_CYCLES_10;
4'h0b:seq_length <= NUM_CYCLES_11;
4'h0c:seq_length <= NUM_CYCLES_12;
4'h0d:seq_length <= NUM_CYCLES_13;
4'h0e:seq_length <= NUM_CYCLES_14;
4'h0f:seq_length <= NUM_CYCLES_15;
4'h0:seq_length <= NUM_CYCLES_00;
4'h1:seq_length <= NUM_CYCLES_01;
4'h2:seq_length <= NUM_CYCLES_02;
4'h3:seq_length <= NUM_CYCLES_03;
4'h4:seq_length <= NUM_CYCLES_04;
4'h5:seq_length <= NUM_CYCLES_05;
4'h6:seq_length <= NUM_CYCLES_06;
4'h7:seq_length <= NUM_CYCLES_07;
4'h8:seq_length <= NUM_CYCLES_08;
4'h9:seq_length <= NUM_CYCLES_09;
4'ha:seq_length <= NUM_CYCLES_10;
4'hb:seq_length <= NUM_CYCLES_11;
4'hc:seq_length <= NUM_CYCLES_12;
4'hd:seq_length <= NUM_CYCLES_13;
4'he:seq_length <= NUM_CYCLES_14;
4'hf:seq_length <= NUM_CYCLES_15;
endcase
always @ (posedge rst or posedge mclk) begin
if (rst) seq_busy_r<=0;
......@@ -137,7 +137,7 @@ module cmd_mux #(
4'h6: seq_busy_r<=5'h1f;
default: seq_busy_r<=5'h00;
endcase
end else seq_busy_r <= {1'b0,seq_busy_r[3:0]};
end else seq_busy_r <= {1'b0,seq_busy_r[4:1]};
end
end
......@@ -150,7 +150,7 @@ module cmd_mux #(
end
always @ (posedge mclk) begin
if (start_w) par_ad <={cmdseq_full_r?cseq_wdata_r:wdata_fifo_out,{(16-AXI_WR_ADDR_BITS){1'b0}},cmdseq_full_r?cseq_waddr_r:waddr_fifo_out};
else par_ad <={8'b0,par_ad[39:0]};
else par_ad <={8'b0,par_ad[47:8]};
end
assign cseq_ackn= cseq_wr_en && (!cmdseq_full_r || can_start_w); // cmddseq_full has priority over axi, so (can_start_w && cmdseq_full_r)
......@@ -173,7 +173,7 @@ module cmd_mux #(
) fifo_cross_clocks_i (
.rst (rst), // input
.rclk (mclk), // input
.wclk (clk), // input
.wclk (axi_clk), // input
.we (wr_en && selected), // input
.re (start_axi_w), // input
.data_in ({waddr[AXI_WR_ADDR_BITS-1:0],wdata[31:0]}), // input[15:0]
......
includes/x393_localparams.vh
View file @ 99191719
// SuppressWarnings VEditor
/*
localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000 << 2
// SuppressWarnings VEditor
localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
localparam BASEADDR_CMD0 = CMD0_ADDR << 2; // 'h0800 << 2 = 'h2000
/// localparam BASEADDR_CMD0 = CMD0_ADDR << 2; // 'h0800 << 2 = 'h2000
// localparam BASEADDR_CTRL = CONTROL_ADDR << 2;
localparam BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
/// localparam BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
localparam BASEADDR_STATUS = STATUS_ADDR << 2; // 'h0800 << 2 = 'h2000
localparam BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2); // 'h080, address to generate delay load
/// localparam BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2); // 'h080, address to generate delay load
localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2); // 'h070, address to generate delay set
localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2); // 'h000, address to set sequnecer channel and run (4 LSB-s - channel)
......@@ -17,7 +18,7 @@
localparam BASEADDR_PAGES = BASEADDR_CTRL | (PAGES_REL<<2); // 'h023, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2); // 'h024, address to enable('h825)/disable('h824) command/address outputs
localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // 'h026 address to activate('h827)/deactivate('h826) active-low reset signal to DDR3 memory
localparam BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2); // 'h028
/// localparam BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2); // 'h028
// SuppressWarnings VEditor
localparam BASEADDR_DCI_RST = BASEADDR_CTRL | (DCI_RST_REL<<2); // 'h02a (+1 - enable)
......@@ -43,7 +44,7 @@
// SuppressWarnings VEditor - not yet used
localparam STATUS_LOCKED_MASK = 'h200;
localparam STATUS_SEQ_BUSY_MASK = 'h400;
*/
`ifdef use200Mhz
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'hb0; // idelay dqs
......
includes/x393_parameters.vh
View file @ 99191719
......@@ -195,7 +195,7 @@
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
......
includes/x393_simulation_parameters.vh
View file @ 99191719
......@@ -3,6 +3,5 @@
parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
parameter integer AXI_TASK_HOLD=1.0,
parameter integer ADDRESS_NUMBER=15
parameter integer AXI_TASK_HOLD=1.0
includes/x393_tasks01.vh
View file @ 99191719
......@@ -15,9 +15,6 @@
B_LAG <= lag;
end
endtask
reg [11:0] GLOBAL_WRITE_ID=0;
reg [11:0] GLOBAL_READ_ID=0;
task read_and_wait;
input [31:0] address;
......
memctrl/cmd_encod_tiled_rd.v
View file @ 99191719
......@@ -242,9 +242,9 @@ module cmd_encod_tiled_rd #(
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h10: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT));
4'h11: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'h12: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
4'ha: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT));
4'hb: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'hc: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
endcase
end
......
memctrl/mcntrl_linear_rw.v
View file @ 99191719
......@@ -219,7 +219,8 @@ module mcntrl_linear_rw #(
assign pgm_param_w= cmd_we;
integer i;
localparam EXTRA_BITS={COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}};
// localparam EXTRA_BITS={ADDRESS_NUMBER-3-COLADDR_NUMBER-3{1'b0}};
// localparam EXTRA_BITS={COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}};
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
......@@ -227,7 +228,8 @@ module mcntrl_linear_rw #(
row_left <= window_width - curr_x; // 14 bits - 13 bits
mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?(1<<NUM_XFER_BITS):row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
xfer_num128_r<= (mem_page_left> {{EXTRA_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// xfer_num128_r<= (mem_page_left> {EXTRA_BITS, lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// VDT bug? next line gives a warning
// xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
last_in_row <= last_in_row_w;
......
memctrl/mcntrl_ps_pio.v
View file @ 99191719
......@@ -20,7 +20,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
`undef DEBUG_FIFO
module mcntrl_ps_pio#(
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
......
phy/mcontr_sequencer.v
View file @ 99191719
......@@ -179,6 +179,7 @@ module mcontr_sequencer #(
reg [ 3:0] dqs_tri_on_pattern=DFLT_DQS_TRI_ON_PATTERN; // DQS tri-state control word, first when enabling output
reg [ 3:0] dqs_tri_off_pattern=DFLT_DQS_TRI_OFF_PATTERN;// DQS tri-state control word, first after disabling output
reg [ 3:0] wbuf_delay=DFLT_WBUF_DELAY;
wire [ 3:0] wbuf_delay_m1;
wire [2:0] phy_16bit_addr;
wire [15:0] phy_16bit_data;
......@@ -299,7 +300,6 @@ module mcontr_sequencer #(
.data (dly_data), // output[31:0]
.we( ld_delay) // output
);
// generate on/off dependent on lsb and 0-bit commands
cmd_deser #(
.ADDR (MCONTR_PHY_0BIT_ADDR),
......@@ -592,11 +592,12 @@ module mcontr_sequencer #(
.din({buf_rst,buf_wr_ndly}), // input
.dout({buf_rst_d, buf_wr}) // output reg
);
assign wbuf_delay_m1=wbuf_delay-1;
dly_16 #(4) buf_wchn_dly_i (
.clk(mclk), // input
.rst(1'b0), // input
.dly(wbuf_delay[3:0]-1), // input[3:0]
.dly(wbuf_delay_m1), //wbuf_delay[3:0]-1), // input[3:0]
.din(run_chn_d), // input
.dout(run_chn_w_d) // output reg
);
......
util_modules/cmd_deser.v
View file @ 99191719
......@@ -58,7 +58,7 @@ module cmd_deser#(
.ADDR_MASK(ADDR_MASK),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) i_cmd_deser_single (
) i_cmd_deser_dual (
.rst(rst),
.clk(clk),
.ad(ad),
......@@ -74,7 +74,7 @@ module cmd_deser#(
.NUM_CYCLES(NUM_CYCLES),
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) i_cmd_deser_single (
) i_cmd_deser_multi (
.rst(rst),
.clk(clk),
.ad(ad),
......@@ -163,7 +163,7 @@ module cmd_deser_dual#(
always @ (posedge clk) begin
if ((match_low && stb) || (match_high && stb_d)) deser_r[15:0] <= {ad,deser_r[15:8]};
end
assign data={DATA_WIDTH{1'b0}};
assign data=0; // {DATA_WIDTH{1'b0}};
assign addr=deser_r[ADDR_WIDTH-1:0];
endmodule
......@@ -198,9 +198,10 @@ module cmd_deser_multi#(
always @ (posedge rst or posedge clk) begin
if (rst) stb_d <= 1'b0;
else stb_d <= match_low && stb;
if (rst) sr <= 0;
else if (match_high && stb_d) sr <= {NUM_CYCLES-1{1'b1}};
else sr <= {1'b0,sr[NUM_CYCLES-3:0]};
if (rst) sr <= 0;
// else if (match_high && stb_d) sr <= {NUM_CYCLES-1{1'b1}};
else if (match_high && stb_d) sr <= 1 << (NUM_CYCLES-2);
else sr <= {1'b0,sr[NUM_CYCLES-2:1]};
end
always @ (posedge clk) begin
if ((match_low && stb) || (match_high && stb_d) || (|sr)) deser_r[8*NUM_CYCLES-1:0] <= {ad,deser_r[8*NUM_CYCLES-1:8]};
......
util_modules/mcont_from_chnbuf_reg.v
View file @ 99191719
......@@ -48,8 +48,8 @@ module mcont_from_chnbuf_reg #(
if (rst) latency_reg<= 0;
else latency_reg <= buf_rd_chn | (latency_reg << 1);
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
// if (rst) buf_done <= 0;
// else buf_done <= buf_chn_sel && seq_done;
end
// always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
......
util_modules/status_generate.v
View file @ 99191719
......@@ -19,10 +19,14 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
// mode bits: 0 disable status generation, 1 single status request, 2 - auto status, keep specified seq number, 3 - auto, inc sequence number
// mode bits:
// 0 disable status generation,
// 1 single status request,
// 2 - auto status, keep specified seq number,
// 3 - auto, inc sequence number
module status_generate #(
parameter STATUS_REG_ADDR=7, // status register address to direct data to
parameter PAYLOAD_BITS=26 //6 // >=2! (2..26)
parameter PAYLOAD_BITS=15 //6 // >=2! (2..26)
)(
input rst,
input clk,
......@@ -41,6 +45,7 @@ module status_generate #(
localparam ALIGNED_STATUS_WIDTH=((NUM_BYTES-2)<<3)+2; // 2 ->2,
// ugly solution to avoid warnings in unused "if" branch
localparam ALIGNED_STATUS_BIT_2=(ALIGNED_STATUS_WIDTH>2)?2:0;
wire [1:0] mode_w;
reg [1:0] mode;
reg [5:0] seq;
reg [PAYLOAD_BITS-1:0] status_r; // "frozen" status to be sent;
......@@ -54,25 +59,28 @@ module status_generate #(
reg [NUM_BYTES-2:0] rq_r;
assign aligned_status=(ALIGNED_STATUS_WIDTH==PAYLOAD_BITS)?status:{{(ALIGNED_STATUS_WIDTH-PAYLOAD_BITS){1'b0}},status};
assign ad=data[7:0];
assign ad=data[7:0];
assign need_to_send=cmd_pend || (mode[1] && status_changed_r); // latency
assign rq=rq_r[0]; // NUM_BYTES-2];
assign snd_rest=rq_r[0] && !rq_r[NUM_BYTES-2];
assign mode_w=wd[7:6];
always @ (posedge rst or posedge clk) begin
if (rst) status_changed_r <= 0;
else status_changed_r <= (status_changed_r && !start) || (status_r != status);
if (rst) status_changed_r <= 0;
// else status_changed_r <= (status_changed_r && !start) || (status_r != status);
else if (start) status_changed_r <= 0;
else status_changed_r <= status_changed_r || (status_r != status);
if (rst) mode <= 0;
else if (we) mode <= wd[7:6];
else if (we) mode <= mode_w; // wd[7:6];
if (rst) seq <= 0;
else if (we) seq <= wd[5:0];
else if ((mode==3) && start) seq <= seq+1;
if (rst) cmd_pend <= 0;
else if (we) cmd_pend <= 1;
else if (start) cmd_pend <= 0;
if (rst) cmd_pend <= 0;
else if (we && (mode_w!=0)) cmd_pend <= 1;
else if (start) cmd_pend <= 0;
if (rst) status_r<=0;
else if (start) status_r<=status;
......
util_modules/status_router2.v
View file @ 99191719
......@@ -47,8 +47,9 @@ module status_router2 (
assign start_rcv=~fifo_half_full & ~rcv_rest_r & rq_in;
wire [7:0] fifo0_out;
wire [7:0] fifo1_out;
wire [1:0] fifo_last_byte;
wire [1:0] fifo_nempty;
wire [1:0] fifo_last_byte;
wire [1:0] fifo_nempty_pre; // pure fifo output
wire [1:0] fifo_nempty; // safe version, zeroed for last byte
wire [1:0] fifo_re;
reg next_chn;
reg current_chn_r;
......@@ -57,23 +58,34 @@ module status_router2 (
wire snd_last_byte;
wire chn_sel_w;
wire early_chn;
wire set_other_only_w; // window to initiate other channel only, same channel must wait
assign chn_sel_w=(&fifo_nempty)?next_chn:&fifo_nempty[1];
assign chn_sel_w=(&fifo_nempty)?next_chn : fifo_nempty[1];
assign fifo_re=start_out?{chn_sel_w,~chn_sel_w}:(snd_rest_r?{current_chn_r,~current_chn_r}:2'b0);
assign snd_last_byte=current_chn_r?fifo_last_byte[1]:fifo_last_byte[0];
// assign snd_last_byte=current_chn_r?fifo_last_byte[1]:fifo_last_byte[0];
assign snd_last_byte=current_chn_r?(fifo_nempty_pre[1] && fifo_last_byte[1]):(fifo_nempty_pre[0] && fifo_last_byte[0]);
assign set_other_only_w=snd_last_byte && (current_chn_r? fifo_nempty[0]:fifo_nempty[1]);
assign snd_pre_start=|fifo_nempty && (!snd_rest_r || snd_last_byte);
assign rq_out=(snd_rest_r && !snd_last_byte) || |fifo_nempty;
/// assign snd_pre_start=|fifo_nempty && !snd_rest_r && !start_out; // no channel change after
// assign rq_out=(snd_rest_r && !snd_last_byte) || |fifo_nempty;
assign rq_out=(snd_rest_r || |fifo_nempty) && !snd_last_byte ;
assign early_chn= (snd_rest_r & ~snd_last_byte)?current_chn_r:chn_sel_w;
assign db_out=early_chn?fifo1_out:fifo0_out;
assign fifo_nempty=fifo_nempty_pre & ~fifo_last_byte;
always @ (posedge rst or posedge clk) begin
if (rst) rcv_rest_r<= 0;
else rcv_rest_r <= (rcv_rest_r & rq_in) | start_rcv;
if (rst) next_chn<= 0;
else if (|fifo_re) next_chn <= fifo_re[0];
if (rst) current_chn_r<= 0;
else if (snd_pre_start) current_chn_r <= chn_sel_w;
else if (|fifo_re) next_chn <= fifo_re[0]; // just to be fair
if (rst) current_chn_r <= 0;
if (set_other_only_w) current_chn_r <= ~current_chn_r;
else if (snd_pre_start) current_chn_r <= chn_sel_w;
/// else if (|fifo_nempty && !snd_rest_r) current_chn_r <= chn_sel_w;
//|fifo_nempty && (!snd_rest_r
if (rst) snd_rest_r<= 0;
else snd_rest_r <= (snd_rest_r & ~snd_last_byte) | start_out;
......@@ -90,7 +102,7 @@ module status_router2 (
.re (fifo_re[0]), // input
.data_in ({rcv_rest_r[0] & ~rq_in[0], db_in0}), // input[8:0] MSB marks last byte
.data_out ({fifo_last_byte[0],fifo0_out}), // output[8:0]
.nempty (fifo_nempty[0]), // output
.nempty (fifo_nempty_pre[0]), // output
.half_full (fifo_half_full[0]) // output reg
`ifdef DEBUG_FIFO
,.under(), // output reg
......@@ -111,7 +123,7 @@ module status_router2 (
.re (fifo_re[1]), // input
.data_in ({rcv_rest_r[1] & ~rq_in[1], db_in1}), // input[8:0] MSB marks last byte
.data_out ({fifo_last_byte[1],fifo1_out}), // output[8:0]
.nempty (fifo_nempty[1]), // output
.nempty (fifo_nempty_pre[1]), // output
.half_full (fifo_half_full[1]) // output reg
`ifdef DEBUG_FIFO
,.under(), // output reg
......
x393.v
View file @ 99191719
......@@ -421,9 +421,9 @@ end
`endif
//TODO: The following is the interface to the frame-based command sequencer (not yet implemnted)
wire [AXI_WR_ADDR_BITS-1:0] cseq_waddr; /// SuppressThisWarning VEditor ****** command sequencer write address (output to command multiplexer)
wire cseq_wr_en; /// SuppressThisWarning VEditor ****** command sequencer write enable (output to command multiplexer) - keep until cseq_ackn received
wire [31:0] cseq_wdata; /// SuppressThisWarning VEditor ****** command sequencer write data (output to command multiplexer)
wire [AXI_WR_ADDR_BITS-1:0] cseq_waddr; /// S uppressThisWarning VEditor ****** command sequencer write address (output to command multiplexer)
wire cseq_wr_en; /// S uppressThisWarning VEditor ****** command sequencer write enable (output to command multiplexer) - keep until cseq_ackn received
wire [31:0] cseq_wdata; /// S uppressThisWarning VEditor ****** command sequencer write data (output to command multiplexer)
wire cseq_ackn; /// SuppressThisWarning VEditor ****** ackn to command sequencer, command sequencer should de-assert cseq_wr_en
// parallel address/data - where higher bandwidth (single-cycle) is needed
wire [AXI_WR_ADDR_BITS-1:0] par_waddr; /// SuppressThisWarning VEditor ****** multiplexed address (full, parallel) to slave devices
......@@ -490,6 +490,11 @@ end
assign status_other_rq = status_test01_rq;
assign status_test01_start = status_other_start;
// missing command sequencer:
assign cseq_waddr='bx; // command sequencer write address (output to command multiplexer)
assign cseq_wr_en= 0; // command sequencer write enable (output to command multiplexer) - keep until cseq_ackn received
assign cseq_wdata='bx; // command sequencer write data (output to command multiplexer)
// channel test module
mcntrl393_test01 #(
......
x393_testbench01.sav 0 → 100644
View file @ 99191719
This diff is collapsed.
x393_testbench01.v → x393_testbench01.tf
View file @ 99191719
......@@ -21,7 +21,6 @@
`timescale 1ns/1ps
`define use200Mhz 1
`define DEBUG_FIFO 1
module x393_testbench01 #(
`include "includes/x393_parameters.vh"
`include "includes/x393_simulation_parameters.vh"
......@@ -56,7 +55,7 @@ module x393_testbench01 #(
wire DQSU; // inout
wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization"
wire MEMCLK;
// wire MEMCLK;
// Simulation signals
reg [11:0] ARID_IN_r;
......@@ -186,7 +185,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
`endif
$dumpfile(lxtname);
// SuppressWarnings VEditor : assigned in $readmem() system task
$dumpvars(0,ddrc_test01_testbench);
$dumpvars(0,x393_testbench01);
CLK <=1'b0;
RST <= 1'bx;
AR_SET_CMD_r <= 1'b0;
......@@ -202,6 +201,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
//set simulation-only parameters
axi_set_b_lag(0); //(1);
axi_set_rd_lag(0);
program_status_all(3); // mode auto with sequence number increment
//...
end
......@@ -435,8 +435,8 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.SDDMU (SDDMU), // inout
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.DUMMY_TO_KEEP(DUMMY_TO_KEEP), // to keep PS7 signals from "optimization"
.MEMCLK (MEMCLK)
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
// ,.MEMCLK (MEMCLK)
);
// Micron DDR3 memory model
/* Instance of Micron DDR3 memory model */
......@@ -763,6 +763,39 @@ simul_axi_read simul_axi_read_i(
// SuppressWarnings VEditor all - these variables are just for viewing, not used anywhere else
reg DEBUG1, DEBUG2, DEBUG3;
reg [11:0] GLOBAL_WRITE_ID=0;
reg [11:0] GLOBAL_READ_ID=0;
task program_status_all;
input [1:0] mode;
begin
program_status (MCONTR_PHY_16BIT_ADDR, MCONTR_PHY_STATUS_CNTRL, mode,0); //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
program_status (MCONTR_TOP_16BIT_ADDR, MCONTR_TOP_16BIT_STATUS_CNTRL, mode,0); //MCONTR_TOP_STATUS_REG_ADDR= 'h1,
program_status (MCNTRL_PS_ADDR, MCNTRL_PS_STATUS_CNTRL, mode,0); //MCNTRL_PS_STATUS_REG_ADDR= 'h2,
program_status (MCNTRL_SCANLINE_CHN2_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,0); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,0); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,0); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,0); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,0); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,0); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
end
endtask
task program_status;
input [29:0] base_addr;
input [7:0] reg_addr;
input [1:0] mode;
// mode bits:
// 0 disable status generation,
// 1 single status request,
// 2 - auto status, keep specified seq number,
// 3 - auto, inc sequence number
input [5:0] seq_number;
begin
axi_write_single(((CONTROL_ADDR+{2'b0,base_addr}+reg_addr)<<2), {24'b0,mode,seq_number});
end
endtask
`include "includes/x393_tasks01.vh"
endmodule
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment