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Commit 94f77f4d authored by Andrey Filippov's avatar Andrey Filippov
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started top module for memory controller with channle buffers, added cascaded status multiplexers

parent 0adb43af
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.editor_defines
View file @ 94f77f4d
...@@ -23,8 +23,10 @@ ...@@ -23,8 +23,10 @@
`undef def_read_mem_chn3 `undef def_read_mem_chn3
`define def_scanline_chn3 `define def_scanline_chn3
// chn 4 is disabled // chn 4 is enabled
`undef def_enable_mem_chn4 `define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_tiled_chn4
// chn 5 is disabled // chn 5 is disabled
`undef def_enable_mem_chn5 `undef def_enable_mem_chn5
......
memctrl/cmd_encod_linear_mux.v
View file @ 94f77f4d
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* Date:2015-01-31 * Date:2015-01-31
* Author: andrey * Author: andrey
* Description: Multiplex parameters from multiple channels sharing the same * Description: Multiplex parameters from multiple channels sharing the same
* linear command encoder (cmd_encod_linear_rd or cmd_encod_linear_wr) * linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr)
* Latency 1 clcok cycle * Latency 1 clcok cycle
* *
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> . * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
...@@ -145,86 +145,173 @@ module cmd_encod_linear_mux#( ...@@ -145,86 +145,173 @@ module cmd_encod_linear_mux#(
output [ADDRESS_NUMBER-1:0] row, // memory row output [ADDRESS_NUMBER-1:0] row, // memory row
output [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bursts output [COLADDR_NUMBER-4:0] start_col, // start memory column in 8-bursts
output [5:0] num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) output [5:0] num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output start // start generating commands output start_rd, // start generating commands in cmd_encod_linear_rd
output start_wr // start generating commands in cmd_encod_linear_wr
); );
reg [2:0] bank_r; // bank address reg [2:0] bank_r; // bank address
reg [ADDRESS_NUMBER-1:0] row_r; // memory row reg [ADDRESS_NUMBER-1:0] row_r; // memory row
reg [COLADDR_NUMBER-4:0] start_col_r;// start memory column in 8-bursts reg [COLADDR_NUMBER-4:0] start_col_r;// start memory column in 8-bursts
reg [5:0] num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) reg [5:0] num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
reg start_r; // start generating commands reg start_rd_r; // start generating commands
reg start_wr_r; // start generating commands
wire [2:0] bank_w; // bank address wire [2:0] bank_w; // bank address
wire [ADDRESS_NUMBER-1:0] row_w; // memory row wire [ADDRESS_NUMBER-1:0] row_w; // memory row
wire [COLADDR_NUMBER-4:0] start_col_w;// start memory column in 8-bursts wire [COLADDR_NUMBER-4:0] start_col_w;// start memory column in 8-bursts
wire [5:0] num128_w; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [5:0] num128_w; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire start_w; // start generating commands wire start_rd_w; // start generating commands
wire start_wr_w; // start generating commands
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+1; localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+2;
localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0; localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0;
assign bank = bank_r; assign bank = bank_r;
assign row = row_r; assign row = row_r;
assign start_col = start_col_r; assign start_col = start_col_r;
assign num128 = num128_r; assign num128 = num128_r;
assign start = start_r; assign start_rd = start_rd_r;
assign {bank_w, row_w, start_col_w, num128_w, start_w} = 0 assign start_wr = start_wr_r;
localparam [15:0] CHN_RD_MEM={
`ifdef def_read_mem_chn15
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn14
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn13
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn12
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn11
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn10
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn9
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn8
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn7
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn6
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn5
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn4
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn3
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn2
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn1
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn0
1'b1};
`else
1'b0};
`endif
assign {bank_w, row_w, start_col_w, num128_w, start_rd_w, start_wr_w} = 0
`ifdef def_scanline_chn0 `ifdef def_scanline_chn0
| (start0?{bank0, row0, start_col0, num128_0,1'b1}:PAR_DEFAULT) | (start0?{bank0, row0, start_col0, num128_0,CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn1 `ifdef def_scanline_chn1
| (start1?{bank1, row1, start_col1, num128_1,1'b1}:PAR_DEFAULT) | (start1?{bank1, row1, start_col1, num128_1,CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn2 `ifdef def_scanline_chn2
| (start2?{bank2, row2, start_col2, num128_2,1'b1}:PAR_DEFAULT) | (start2?{bank2, row2, start_col2, num128_2,CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn3 `ifdef def_scanline_chn3
| (start3?{bank3, row3, start_col3, num128_3,1'b1}:PAR_DEFAULT) | (start3?{bank3, row3, start_col3, num128_3,CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn4 `ifdef def_scanline_chn4
| (start4?{bank4, row4, start_col4, num128_4,1'b1}:PAR_DEFAULT) | (start4?{bank4, row4, start_col4, num128_4,CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn5 `ifdef def_scanline_chn5
| (start5?{bank5, row5, start_col5, num128_5,1'b1}:PAR_DEFAULT) | (start5?{bank5, row5, start_col5, num128_5,CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn6 `ifdef def_scanline_chn6
| (start6?{bank6, row6, start_col6, num128_6,1'b1}:PAR_DEFAULT) | (start6?{bank6, row6, start_col6, num128_6,CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn7 `ifdef def_scanline_chn7
| (start7?{bank7, row7, start_col7, num128_7,1'b1}:PAR_DEFAULT) | (start7?{bank7, row7, start_col7, num128_7,CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn8 `ifdef def_scanline_chn8
| (start8?{bank8, row8, start_col8, num128_8,1'b1}:PAR_DEFAULT) | (start8?{bank8, row8, start_col8, num128_8,CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn9 `ifdef def_scanline_chn9
| (start9?{bank9, row9, start_col9, num128_9,1'b1}:PAR_DEFAULT) | (start9?{bank9, row9, start_col9, num128_9,CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn10 `ifdef def_scanline_chn10
| (start10?{bank10, row10, start_col10, num128_10,1'b1}:PAR_DEFAULT) | (start10?{bank10, row10, start_col10, num128_10,CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn11 `ifdef def_scanline_chn11
| (start11?{bank11, row11, start_col11, num128_11,1'b1}:PAR_DEFAULT) | (start11?{bank11, row11, start_col11, num128_11,CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn12 `ifdef def_scanline_chn12
| (start12?{bank12, row12, start_col12, num128_12,1'b1}:PAR_DEFAULT) | (start12?{bank12, row12, start_col12, num128_12,CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn13 `ifdef def_scanline_chn13
| (start13?{bank13, row13, start_col13, num128_13,1'b1}:PAR_DEFAULT) | (start13?{bank13, row13, start_col13, num128_13,CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn14 `ifdef def_scanline_chn14
| (start14?{bank14, row14, start_col14, num128_14,1'b1}:PAR_DEFAULT) | (start14?{bank14, row14, start_col14, num128_14,CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
`endif `endif
`ifdef def_scanline_chn15 `ifdef def_scanline_chn15
| (start15?{bank15, row15, start_col15, num128_15,1'b1}:PAR_DEFAULT) | (start15?{bank15, row15, start_col15, num128_15,CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
`endif `endif
; ;
always @ (posedge clk) begin always @ (posedge clk) begin
if (start_w) begin if (start_rd_w || start_wr_w) begin
bank_r <= bank_w; bank_r <= bank_w;
row_r <= row_w; row_r <= row_w;
start_col_r <= start_col_w; start_col_r <= start_col_w;
num128_r <= num128_w; num128_r <= num128_w;
end end
start_r <= start_w; start_rd_r <= start_rd_w;
start_wr_r <= start_wr_w;
end end
......
memctrl/cmd_encod_tiled_mux.v 0 → 100644
View file @ 94f77f4d
/*******************************************************************************
* Module: cmd_encod_tiled_mux
* Date:2015-01-31
* Author: andrey
* Description: Multiplex parameters from multiple channels sharing the same
* tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr)
* Latency 1 clcok cycle
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* cmd_encod_tiled_mux.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmd_encod_tiled_mux.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmd_encod_tiled_mux #(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10
) (
input clk,
`ifdef def_tiled_chn0
input [2:0] bank0, // bank address
input [ADDRESS_NUMBER-1:0] row0, // memory row
input [COLADDR_NUMBER-4:0] col0, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc0, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows0, // number of rows to read minus 1
input [5:0] num_cols0, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open0, // keep banks open (for <=8 banks only
input start0, // start generating commands
`endif
`ifdef def_tiled_chn1
input [2:0] bank1, // bank address
input [ADDRESS_NUMBER-1:0] row1, // memory row
input [COLADDR_NUMBER-4:0] col1, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc1, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows1, // number of rows to read minus 1
input [5:0] num_cols1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open1, // keep banks open (for <=8 banks only
input start1, // start generating commands
`endif
`ifdef def_tiled_chn2
input [2:0] bank2, // bank address
input [ADDRESS_NUMBER-1:0] row2, // memory row
input [COLADDR_NUMBER-4:0] col2, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc2, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows2, // number of rows to read minus 1
input [5:0] num_cols2, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open2, // keep banks open (for <=8 banks only
input start2, // start generating commands
`endif
`ifdef def_tiled_chn3
input [2:0] bank3, // bank address
input [ADDRESS_NUMBER-1:0] row3, // memory row
input [COLADDR_NUMBER-4:0] col3, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc3, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows3, // number of rows to read minus 1
input [5:0] num_cols3, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open3, // keep banks open (for <=8 banks only
input start3, // start generating commands
`endif
`ifdef def_tiled_chn4
input [2:0] bank4, // bank address
input [ADDRESS_NUMBER-1:0] row4, // memory row
input [COLADDR_NUMBER-4:0] col4, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc4, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows4, // number of rows to read minus 1
input [5:0] num_cols4, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open4, // keep banks open (for <=8 banks only
input start4, // start generating commands
`endif
`ifdef def_tiled_chn5
input [2:0] bank5, // bank address
input [ADDRESS_NUMBER-1:0] row5, // memory row
input [COLADDR_NUMBER-4:0] col5, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc5, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows5, // number of rows to read minus 1
input [5:0] num_cols5, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open5, // keep banks open (for <=8 banks only
input start5, // start generating commands
`endif
`ifdef def_tiled_chn6
input [2:0] bank6, // bank address
input [ADDRESS_NUMBER-1:0] row6, // memory row
input [COLADDR_NUMBER-4:0] col6, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc6, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows6, // number of rows to read minus 1
input [5:0] num_cols6, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open6, // keep banks open (for <=8 banks only
input start6, // start generating commands
`endif
`ifdef def_tiled_chn7
input [2:0] bank7, // bank address
input [ADDRESS_NUMBER-1:0] row7, // memory row
input [COLADDR_NUMBER-4:0] col7, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc7, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows7, // number of rows to read minus 1
input [5:0] num_cols7, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open7, // keep banks open (for <=8 banks only
input start7, // start generating commands
`endif
`ifdef def_tiled_chn8
input [2:0] bank8, // bank address
input [ADDRESS_NUMBER-1:0] row8, // memory row
input [COLADDR_NUMBER-4:0] col8, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc8, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows8, // number of rows to read minus 1
input [5:0] num_cols8, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open8, // keep banks open (for <=8 banks only
input start8, // start generating commands
`endif
`ifdef def_tiled_chn9
input [2:0] bank9, // bank address
input [ADDRESS_NUMBER-1:0] row9, // memory row
input [COLADDR_NUMBER-4:0] col9, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc9, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows9, // number of rows to read minus 1
input [5:0] num_cols9, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open9, // keep banks open (for <=8 banks only
input start9, // start generating commands
`endif
`ifdef def_tiled_chn10
input [2:0] bank10, // bank address
input [ADDRESS_NUMBER-1:0] row10, // memory row
input [COLADDR_NUMBER-4:0] col10, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc10, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows10, // number of rows to read minus 1
input [5:0] num_cols10, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open10, // keep banks open (for <=8 banks only
input start10, // start generating commands
`endif
`ifdef def_tiled_chn11
input [2:0] bank11, // bank address
input [ADDRESS_NUMBER-1:0] row11, // memory row
input [COLADDR_NUMBER-4:0] col11, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc11, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows11, // number of rows to read minus 1
input [5:0] num_cols11, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open11, // keep banks open (for <=8 banks only
input start11, // start generating commands
`endif
`ifdef def_tiled_chn12
input [2:0] bank12, // bank address
input [ADDRESS_NUMBER-1:0] row12, // memory row
input [COLADDR_NUMBER-4:0] col12, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc12, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows12, // number of rows to read minus 1
input [5:0] num_cols12, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open12, // keep banks open (for <=8 banks only
input start12, // start generating commands
`endif
`ifdef def_tiled_chn13
input [2:0] bank13, // bank address
input [ADDRESS_NUMBER-1:0] row13, // memory row
input [COLADDR_NUMBER-4:0] col13, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc13, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows13, // number of rows to read minus 1
input [5:0] num_cols13, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open13, // keep banks open (for <=8 banks only
input start13, // start generating commands
`endif
`ifdef def_tiled_chn14
input [2:0] bank14, // bank address
input [ADDRESS_NUMBER-1:0] row14, // memory row
input [COLADDR_NUMBER-4:0] col14, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc14, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows14, // number of rows to read minus 1
input [5:0] num_cols14, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open14, // keep banks open (for <=8 banks only
input start14, // start generating commands
`endif
`ifdef def_tiled_chn15
input [2:0] bank15, // bank address
input [ADDRESS_NUMBER-1:0] row15, // memory row
input [COLADDR_NUMBER-4:0] col15, // start memory column in 8-bit bursts
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc15, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows15, // number of rows to read minus 1
input [5:0] num_cols15, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open15, // keep banks open (for <=8 banks only
input start15, // start generating commands
`endif
output [2:0] bank, // bank address
output [ADDRESS_NUMBER-1:0] row, // memory row
output [COLADDR_NUMBER-4:0] col, // start memory column in 8-bit bursts
output [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
output [5:0] num_rows, // number of rows to read minus 1
output [5:0] num_cols, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // keep banks open (for <=8 banks only
output start_rd, // start generating commands in cmd_encod_linear_rd
output start_wr // start generating commands in cmd_encod_linear_wr
);
reg [2:0] bank_r; // bank address
reg [ADDRESS_NUMBER-1:0] row_r; // memory row
reg [COLADDR_NUMBER-4:0] col_r; // start memory column in 8-bit bursts
reg [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_r; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
reg [5:0] num_rows_r; // number of rows to read minus 1
reg [5:0] num_cols_r; // number of 16-pixel columns to read (rows first_r; then columns) - 1
reg keep_open_r; // keep banks open (for <=8 banks only
reg start_rd_r; // start generating commands in cmd_encod_linear_rd
reg start_wr_r; // start generating commands in cmd_encod_linear_wr
wire [2:0] bank_w; // bank address
wire [ADDRESS_NUMBER-1:0] row_w; // memory row
wire [COLADDR_NUMBER-4:0] col_w; // start memory column in 8-bit bursts
wire [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_w; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
wire [5:0] num_rows_w; // number of rows to read minus 1
wire [5:0] num_cols_w; // number of 16-pixel columns to read (rows first_r; then columns) - 1
wire keep_open_w; // keep banks open (for <=8 banks only
wire start_rd_w; // start generating commands in cmd_encod_linear_rd
wire start_wr_w; // start generating commands in cmd_encod_linear_wr
localparam PAR_WIDTH=3+ADDRESS_NUMBER+COLADDR_NUMBER-3+ADDRESS_NUMBER+COLADDR_NUMBER-3+6+6+1+2;
localparam [PAR_WIDTH-1:0] PAR_DEFAULT=0;
assign bank = bank_r;
assign row = row_r;
assign col = col_r;
assign rowcol_inc = rowcol_inc_r; // increment {row.col} when bank rolls over_r; removed 3 LSBs (in 8-bursts)
assign num_rows = num_rows_r; // number of rows to read minus 1
assign num_cols = num_cols_r; // number of 16-pixel columns to read (rows first_r; then columns) - 1
assign keep_open = keep_open_r; // keep banks open (for <=8 banks only
assign start_rd = start_rd_r;
assign start_wr = start_wr_r;
localparam [15:0] CHN_RD_MEM={
`ifdef def_read_mem_chn15
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn14
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn13
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn12
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn11
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn10
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn9
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn8
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn7
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn6
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn5
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn4
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn3
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn2
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn1
1'b1,
`else
1'b0,
`endif
`ifdef def_read_mem_chn0
1'b1};
`else
1'b0};
`endif
assign {bank_w, row_w, col_w, rowcol_inc_w, num_rows_w, num_cols_w, keep_open_w, start_rd_w, start_wr_w} = 0
`ifdef def_tiled_chn0
| (start0?{bank0, row0, col0, rowcol_inc0, num_rows0, num_cols0, keep_open0, CHN_RD_MEM[0],~CHN_RD_MEM[0]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn1
| (start1?{bank1, row1, col1, rowcol_inc1, num_rows1, num_cols1, keep_open1, CHN_RD_MEM[1],~CHN_RD_MEM[1]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn2
| (start2?{bank2, row2, col2, rowcol_inc2, num_rows2, num_cols2, keep_open2, CHN_RD_MEM[2],~CHN_RD_MEM[2]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn3
| (start3?{bank3, row3, col3, rowcol_inc3, num_rows3, num_cols3, keep_open3, CHN_RD_MEM[3],~CHN_RD_MEM[3]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn4
| (start4?{bank4, row4, col4, rowcol_inc4, num_rows4, num_cols4, keep_open4, CHN_RD_MEM[4],~CHN_RD_MEM[4]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn5
| (start5?{bank5, row5, col5, rowcol_inc5, num_rows5, num_cols5, keep_open5, CHN_RD_MEM[5],~CHN_RD_MEM[5]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn6
| (start6?{bank6, row6, col6, rowcol_inc6, num_rows6, num_cols6, keep_open6, CHN_RD_MEM[6],~CHN_RD_MEM[6]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn7
| (start7?{bank7, row7, col7, rowcol_inc7, num_rows7, num_cols7, keep_open7, CHN_RD_MEM[7],~CHN_RD_MEM[7]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn8
| (start8?{bank8, row8, col8, rowcol_inc8, num_rows8, num_cols8, keep_open8, CHN_RD_MEM[8],~CHN_RD_MEM[8]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn9
| (start9?{bank9, row9, col9, rowcol_inc9, num_rows9, num_cols9, keep_open9, CHN_RD_MEM[9],~CHN_RD_MEM[9]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn10
| (start10?{bank10, row10, col10, rowcol_inc10, num_rows10, num_cols10, keep_open10, CHN_RD_MEM[10],~CHN_RD_MEM[10]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn11
| (start11?{bank11, row11, col11, rowcol_inc11, num_rows11, num_cols11, keep_open11, CHN_RD_MEM[11],~CHN_RD_MEM[11]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn12
| (start12?{bank12, row12, col12, rowcol_inc12, num_rows12, num_cols12, keep_open12, CHN_RD_MEM[12],~CHN_RD_MEM[12]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn13
| (start13?{bank13, row13, col13, rowcol_inc13, num_rows13, num_cols13, keep_open13, CHN_RD_MEM[13],~CHN_RD_MEM[13]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn14
| (start14?{bank14, row14, col14, rowcol_inc14, num_rows14, num_cols14, keep_open14, CHN_RD_MEM[14],~CHN_RD_MEM[14]}:PAR_DEFAULT)
`endif
`ifdef def_tiled_chn15
| (start15?{bank15, row15, col15, rowcol_inc15, num_rows15, num_cols15, keep_open15, CHN_RD_MEM[15],~CHN_RD_MEM[15]}:PAR_DEFAULT)
`endif
;
always @ (posedge clk) begin
if (start_rd_w || start_wr_w) begin
bank_r <= bank_w;
row_r <= row_w;
col_r <= col_w;
rowcol_inc_r <= rowcol_inc_w;
num_rows_r <= num_rows_w;
num_cols_r <= num_cols_w;
keep_open_r <= keep_open_w;
end
start_rd_r <= start_rd_w;
start_wr_r <= start_wr_w;
end
endmodule
memctrl/cmd_encod_tiled_rd.v
View file @ 94f77f4d
...@@ -48,7 +48,6 @@ module cmd_encod_tiled_rd #( ...@@ -48,7 +48,6 @@ module cmd_encod_tiled_rd #(
input [5:0] num_rows_in_m1, // number of rows to read minus 1 input [5:0] num_rows_in_m1, // number of rows to read minus 1
input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1 input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open_in, // keep banks open (for <=8 banks only input keep_open_in, // keep banks open (for <=8 banks only
input start, // start generating commands input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command output reg enc_wr, // write encoded command
......
memctrl/mcntrl393.v 0 → 100644
View file @ 94f77f4d
/*******************************************************************************
* Module: mcntrl393
* Date:2015-01-31
* Author: andrey
* Description: Top level memory controller for 393 camera, includes channel buffers
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcntrl393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl393.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcntrl393 #(
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
// 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
// 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
// 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // enable/disable active-low reset signal to DDR3 memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
//0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h3f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h3f8, // address mask to generate sequencer channel/run
// 0x1050 - PATTERNS // 16 bits
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// 0x1053 - EXTRA_REL // 1 bit - set extra parameters (currently just inv_clk_div)
// 0x1054 - STATUS_CNTRL // 8 bits - write to status control
parameter MCONTR_PHY_16BIT_PATTERNS = 'h0, // set DQM and DQS patterns (16'h0055)
parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter MCONTR_PHY_16BIT_WBUF_DELAY = 'h2, // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
parameter MCONTR_PHY_16BIT_EXTRA = 'h3, // ? bits - set extra parameters (currently just inv_clk_div)
parameter MCONTR_PHY_STATUS_CNTRL = 'h4, // write to status control (8-bit)
//0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h3f0, // Address mask to set channel priorities
//0x1070..1077 - 16-bit top memory controller:
parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h3f8, // address mask to set mcontr top control registers
// 0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
// 0x1071 - REFRESH_PERIOD // 8-bit refresh period
// 0x1072 - REFRESH_ADDRESS // 10 bits
// 0x1073 - STATUS_CNTRL // 8 bits - write to status control (and debug?)
parameter MCONTR_TOP_16BIT_CHN_EN = 'h0, // 16 bits per-channel enable (want/need requests)
parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1, // 8-bit refresh period
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
// Status read address
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 0, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h6, // write levelling - 7!
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
parameter DFLT_REFRESH_ADDR= 10'h0, // refresh sequence address in command memory
parameter DFLT_REFRESH_PERIOD= 8'h0, // default 8-bit refresh period (scale?)
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
//
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MCNTRL_SCANLINE_CHN2_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h3, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h4, // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h5, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h6, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2 // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
) (
input rst_in,
input clk_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
input cmd0_clk, // clock to write commend sequencer from PS
input cmd0_we, // write enble to write commend sequencer from PS
input [9:0] cmd0_addr, // address write commend sequencer from PS
input [31:0] cmd0_data, // data to write commend sequencer from PS
// DDR3 interface
output SDRST, // DDR3 reset (active low)
output SDCLK, // DDR3 clock differential output, positive
output SDNCLK,// DDR3 clock differential output, negative
output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
output [2:0] SDBA, // output bank address ports
output SDWE, // output WE port
output SDRAS, // output RAS port
output SDCAS, // output CAS port
output SDCKE, // output Clock Enable port
output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads
output SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad
output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad
inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here?
);
wire rst=rst_in;
wire [7:0] status_mcontr_ad; // Memory controller status byte-wide address/data
wire status_mcontr_rq; // Memory controller status request
wire status_mcontr_start; // Memory controller status packet transfer start (currently with 0 latency from status_root_rq)
// Not yet connected
wire [7:0] status_other_ad; // Other status byte-wide address/data
wire status_other_rq; // Other status request
wire status_other_start; // Other status packet transfer start (currently with 0 latency from status_root_rq)
status_router2 status_router2_mctrl_top_i (
.rst (rst), // input
.clk (mclk), // input
.db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output
.db_in1 (status_other_ad), // input[7:0]
.rq_in1 (status_other_rq), // input
.start_in1 (status_other_start), // output
.db_out (status_ad), // output[7:0]
.rq_out (status_rq), // output
.start_out (status_start) // input
);
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_SCANLINE_ADDR (MCNTRL_SCANLINE_CHN2_ADDR),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
.MCNTRL_SCANLINE_STATUS_CNTRL (MCNTRL_SCANLINE_STATUS_CNTRL),
.MCNTRL_SCANLINE_STARTADDR (MCNTRL_SCANLINE_STARTADDR),
.MCNTRL_SCANLINE_FRAME_FULL_WIDTH (MCNTRL_SCANLINE_FRAME_FULL_WIDTH),
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS)
) mcntrl_linear_rw_chn2_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad(), // input[7:0]
.cmd_stb(), // input
.status_ad(), // output[7:0]
.status_rq(), // output
.status_start(), // input
.frame_start(), // input
.next_page(), // input
.frame_done(), // output
.line_unfinished(), // output[15:0]
.suspend(), // input
.xfer_want(), // output
.xfer_need(), // output
.xfer_grant(), // input
.xfer_start(), // output
.xfer_bank(), // output[2:0]
.xfer_row(), // output[14:0]
.xfer_col(), // output[6:0]
.xfer_num128(), // output[5:0]
.xfer_done(), // input
.xfer_page() // output[1:0]
);
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
.NUM_XFER_BITS (NUM_XFER_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.MCNTRL_SCANLINE_ADDR (MCNTRL_SCANLINE_CHN3_ADDR),
.MCNTRL_SCANLINE_MASK (MCNTRL_SCANLINE_MASK),
.MCNTRL_SCANLINE_MODE (MCNTRL_SCANLINE_MODE),
.MCNTRL_SCANLINE_STATUS_CNTRL (MCNTRL_SCANLINE_STATUS_CNTRL),
.MCNTRL_SCANLINE_STARTADDR (MCNTRL_SCANLINE_STARTADDR),
.MCNTRL_SCANLINE_FRAME_FULL_WIDTH (MCNTRL_SCANLINE_FRAME_FULL_WIDTH),
.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_ADDR),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS)
) mcntrl_linear_rw_chn3_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad(), // input[7:0]
.cmd_stb(), // input
.status_ad(), // output[7:0]
.status_rq(), // output
.status_start(), // input
.frame_start(), // input
.next_page(), // input
.frame_done(), // output
.line_unfinished (), // output[15:0]
.suspend(), // input
.xfer_want(), // output
.xfer_need(), // output
.xfer_grant(), // input
.xfer_start(), // output
.xfer_bank(), // output[2:0]
.xfer_row(), // output[14:0]
.xfer_col(), // output[6:0]
.xfer_num128(), // output[5:0]
.xfer_done(), // input
.xfer_page() // output[1:0]
);
/* Instance template for module mcntrl_ps_pio */
mcntrl_ps_pio #(
.MCNTRL_PS_ADDR (MCNTRL_PS_ADDR), //'h100),
.MCNTRL_PS_MASK (MCNTRL_PS_MASK), //'h3e0),
.MCNTRL_PS_STATUS_REG_ADDR (MCNTRL_PS_STATUS_REG_ADDR), //'h2),
.MCNTRL_PS_EN_RST (MCNTRL_PS_EN_RST), //'h0),
.MCNTRL_PS_CMD (MCNTRL_PS_CMD), //'h1),
.MCNTRL_PS_STATUS_CNTRL (MCNTRL_PS_STATUS_CNTRL) //'h2)
) mcntrl_ps_pio_i (
.rst (rst), // input
.mclk (mclk), // input
.cmd_ad(), // input[7:0]
.cmd_stb(), // input
.status_ad(), // output[7:0]
.status_rq(), // output
.status_start(), // input
.port0_clk(), // input
.port0_re(), // input
.port0_regen(), // input
.port0_addr(), // input[9:0]
.port0_data(), // output[31:0]
.port1_clk(), // input
.port1_we(), // input
.port1_addr(), // input[9:0]
.port1_data(), // input[31:0]
.want_rq0(), // output reg
.need_rq0(), // output reg
.channel_pgm_en0(), // input
.seq_data0(), // output[9:0]
.seq_set0(), // output
.seq_done0(), // input
.buf_wr_chn0(), // input
.buf_waddr_chn0(), // input[6:0]
.buf_wdata_chn0(), // input[63:0]
.want_rq1(), // output reg
.need_rq1(), // output reg
.channel_pgm_en1(), // input
.seq_done1(), // input
.buf_rd_chn1(), // input
.buf_raddr_chn1(), // input[6:0]
.buf_rdata_chn1() // output[63:0]
);
/* Instance template for module cmd_encod_linear_mux */
cmd_encod_linear_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER)
) cmd_encod_linear_mux_i (
.clk (mclk), // input
.bank2(), // input[2:0]
.row2(), // input[14:0]
.start_col2(), // input[6:0]
.num128_2(), // input[5:0]
.start2(), // input
.bank3(), // input[2:0]
.row3(), // input[14:0]
.start_col3(), // input[6:0]
.num128_3(), // input[5:0]
.start3(), // input
.bank(), // output[2:0]
.row(), // output[14:0]
.start_col(), // output[6:0]
.num128(), // output[5:0]
.start_rd(), // output
.start_wr() // output
);
/* Instance template for module cmd_encod_tiled_mux */
cmd_encod_tiled_mux #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER)
) cmd_encod_tiled_mux_i (
.clk (mclk), // input
.bank4(), // input[2:0]
.row4(), // input[14:0]
.col4(), // input[6:0]
.rowcol_inc4(), // input[21:0]
.num_rows4(), // input[5:0]
.num_cols4(), // input[5:0]
.keep_open4(), // input
.start4(), // input
.bank(), // output[2:0]
.row(), // output[14:0]
.col(), // output[6:0]
.rowcol_inc(), // output[21:0]
.num_rows(), // output[5:0]
.num_cols(), // output[5:0]
.keep_open(), // output
.start_rd(), // output
.start_wr() // output
);
memctrl16 #(
.DLY_LD (DLY_LD),
.DLY_LD_MASK (DLY_LD_MASK),
.MCONTR_PHY_0BIT_ADDR (MCONTR_PHY_0BIT_ADDR),
.MCONTR_PHY_0BIT_ADDR_MASK (MCONTR_PHY_0BIT_ADDR_MASK),
.MCONTR_PHY_0BIT_DLY_SET (MCONTR_PHY_0BIT_DLY_SET),
.MCONTR_PHY_0BIT_CMDA_EN (MCONTR_PHY_0BIT_CMDA_EN),
.MCONTR_PHY_0BIT_SDRST_ACT (MCONTR_PHY_0BIT_SDRST_ACT),
.MCONTR_PHY_0BIT_CKE_EN (MCONTR_PHY_0BIT_CKE_EN),
.MCONTR_PHY_0BIT_DCI_RST (MCONTR_PHY_0BIT_DCI_RST),
.MCONTR_PHY_0BIT_DLY_RST(MCONTR_PHY_0BIT_DLY_RST),
.MCONTR_TOP_0BIT_ADDR(MCONTR_TOP_0BIT_ADDR),
.MCONTR_TOP_0BIT_ADDR_MASK(MCONTR_TOP_0BIT_ADDR_MASK),
.MCONTR_TOP_0BIT_MCONTR_EN(MCONTR_TOP_0BIT_MCONTR_EN),
.MCONTR_TOP_0BIT_REFRESH_EN(MCONTR_TOP_0BIT_REFRESH_EN),
.MCONTR_PHY_16BIT_ADDR(MCONTR_PHY_16BIT_ADDR),
.MCONTR_PHY_16BIT_ADDR_MASK(MCONTR_PHY_16BIT_ADDR_MASK),
.MCONTR_PHY_16BIT_PATTERNS(MCONTR_PHY_16BIT_PATTERNS),
.MCONTR_PHY_16BIT_PATTERNS_TRI(MCONTR_PHY_16BIT_PATTERNS_TRI),
.MCONTR_PHY_16BIT_WBUF_DELAY(MCONTR_PHY_16BIT_WBUF_DELAY),
.MCONTR_PHY_16BIT_EXTRA(MCONTR_PHY_16BIT_EXTRA),
.MCONTR_PHY_STATUS_CNTRL(MCONTR_PHY_STATUS_CNTRL),
.MCONTR_ARBIT_ADDR(MCONTR_ARBIT_ADDR),
.MCONTR_ARBIT_ADDR_MASK(MCONTR_ARBIT_ADDR_MASK),
.MCONTR_TOP_16BIT_ADDR(MCONTR_TOP_16BIT_ADDR),
.MCONTR_TOP_16BIT_ADDR_MASK(MCONTR_TOP_16BIT_ADDR_MASK),
.MCONTR_TOP_16BIT_CHN_EN(MCONTR_TOP_16BIT_CHN_EN),
.MCONTR_TOP_16BIT_REFRESH_PERIOD(MCONTR_TOP_16BIT_REFRESH_PERIOD),
.MCONTR_TOP_16BIT_REFRESH_ADDRESS(MCONTR_TOP_16BIT_REFRESH_ADDRESS),
.MCONTR_TOP_16BIT_STATUS_CNTRL(MCONTR_TOP_16BIT_STATUS_CNTRL),
.MCONTR_PHY_STATUS_REG_ADDR(MCONTR_PHY_STATUS_REG_ADDR),
.MCONTR_TOP_STATUS_REG_ADDR(MCONTR_TOP_STATUS_REG_ADDR),
.CHNBUF_READ_LATENCY(CHNBUF_READ_LATENCY),
.DFLT_DQS_PATTERN(DFLT_DQS_PATTERN),
.DFLT_DQM_PATTERN(DFLT_DQM_PATTERN),
.DFLT_DQ_TRI_ON_PATTERN(DFLT_DQ_TRI_ON_PATTERN),
.DFLT_DQ_TRI_OFF_PATTERN(DFLT_DQ_TRI_OFF_PATTERN),
.DFLT_DQS_TRI_ON_PATTERN(DFLT_DQS_TRI_ON_PATTERN),
.DFLT_DQS_TRI_OFF_PATTERN(DFLT_DQS_TRI_OFF_PATTERN),
.DFLT_WBUF_DELAY(DFLT_WBUF_DELAY),
.DFLT_INV_CLK_DIV(DFLT_INV_CLK_DIV),
.DFLT_CHN_EN(DFLT_CHN_EN),
.DFLT_REFRESH_ADDR(DFLT_REFRESH_ADDR),
.DFLT_REFRESH_PERIOD(DFLT_REFRESH_PERIOD),
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.PHASE_WIDTH (PHASE_WIDTH),
.SLEW_DQ (SLEW_DQ),
.SLEW_DQS (SLEW_DQS),
.SLEW_CMDA (SLEW_CMDA),
.SLEW_CLK (SLEW_CLK),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
.REF_JITTER1 (REF_JITTER1),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) memctrl16_i (
.rst_in (rst_in), // input
.clk_in (clk_in), // input
.mclk (mclk), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
.status_rq (status_mcontr_rq), // input request to send status downstream
.status_start (status_mcontr_start), // Acknowledge of the first status packet byte (address)
.cmd0_clk (cmd0_clk), // input
.cmd0_we (cmd0_we), // input
.cmd0_addr (cmd0_addr), // input[9:0]
.cmd0_data (cmd0_data), // input[31:0]
.want_rq0 (want_rq0), // input
.need_rq0 (need_rq0), // input
.channel_pgm_en0 (channel_pgm_en0), // output reg
.seq_data0 (seq_data0), // input[31:0]
.seq_wr0 (seq_wr0), // input
.seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.want_rq1 (want_rq1), // input
.need_rq1 (need_rq1), // input
.channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_data1 (seq_data1), // input[31:0]
.seq_wr1 (seq_wr1), // input
.seq_set1 (seq_set1), // input
.seq_done1 (seq_done1), // output
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
.need_rq2 (need_rq2), // input
.channel_pgm_en2 (channel_pgm_en2), // output reg
.seq_data2 (seq_data2), // input[31:0]
.seq_wr2 (seq_wr2), // input
.seq_set2 (seq_set2), // input
.seq_done2 (seq_done2), // output
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.want_rq3 (want_rq3), // input
.need_rq3 (need_rq3), // input
.channel_pgm_en3 (channel_pgm_en3), // output reg
.seq_data3 (seq_data3), // input[31:0]
.seq_wr3 (seq_wr3), // input
.seq_set3 (seq_set3), // input
.seq_done3 (seq_done3), // output
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
.need_rq4 (need_rq4), // input
.channel_pgm_en4 (channel_pgm_en4), // output reg
.seq_data4 (seq_data4), // input[31:0]
.seq_wr4 (seq_wr4), // input
.seq_set4 (seq_set4), // input
.seq_done4 (seq_done4), // output
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
.SDA (SDA), // output[14:0]
.SDBA (SDBA), // output[2:0]
.SDWE (SDWE), // output
.SDRAS (SDRAS), // output
.SDCAS (SDCAS), // output
.SDCKE (SDCKE), // output
.SDODT (SDODT), // output
.SDD (SDD), // inout[15:0]
.SDDML (SDDML), // output
.DQSL (DQSL), // inout
.NDQSL (NDQSL), // inout
.SDDMU (SDDMU), // output
.DQSU (DQSU), // inout
.NDQSU (NDQSU), // inout
.tmp_debug (tmp_debug) // output[11:0]
);
endmodule
util_modules/status_router16.v 0 → 100644
View file @ 94f77f4d
/*******************************************************************************
* Module: status_router16
* Date:2015-01-31
* Author: andrey
* Description: Routes status data from 16 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* status_router16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* status_router16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module status_router16(
input rst,
input clk,
// 4 input channels
input [7:0] db_in0,
input rq_in0,
output start_in0, // only for the first cycle, combinatorial
input [7:0] db_in1,
input rq_in1,
output start_in1, // only for the first cycle, combinatorial
input [7:0] db_in2,
input rq_in2,
output start_in2, // only for the first cycle, combinatorial
input [7:0] db_in3,
input rq_in3,
output start_in3, // only for the first cycle, combinatorial
input [7:0] db_in4,
input rq_in4,
output start_in4, // only for the first cycle, combinatorial
input [7:0] db_in5,
input rq_in5,
output start_in5, // only for the first cycle, combinatorial
input [7:0] db_in6,
input rq_in6,
output start_in6, // only for the first cycle, combinatorial
input [7:0] db_in7,
input rq_in7,
output start_in7, // only for the first cycle, combinatorial
input [7:0] db_in8,
input rq_in8,
output start_in8, // only for the first cycle, combinatorial
input [7:0] db_in9,
input rq_in9,
output start_in9, // only for the first cycle, combinatorial
input [7:0] db_in10,
input rq_in10,
output start_in10, // only for the first cycle, combinatorial
input [7:0] db_in11,
input rq_in11,
output start_in11, // only for the first cycle, combinatorial
input [7:0] db_in12,
input rq_in12,
output start_in12, // only for the first cycle, combinatorial
input [7:0] db_in13,
input rq_in13,
output start_in13, // only for the first cycle, combinatorial
input [7:0] db_in14,
input rq_in14,
output start_in14, // only for the first cycle, combinatorial
input [7:0] db_in15,
input rq_in15,
output start_in15, // only for the first cycle, combinatorial
// output (multiplexed) channel
output [7:0] db_out,
output rq_out,
input start_out // only for the first cycle, combinatorial
);
wire [7:0] db_int [1:0];
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
.db_in1 (db_int[1]), // input[7:0]
.rq_in1 (rq_int[1]), // input
.start_in1 (start_int[1]), // output
.db_out (db_out), // output[7:0]
.rq_out (rq_out), // output
.start_out (start_out) // input
);
status_router8 status_router8_01234567_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
.db_in1 (db_in1), // input[7:0]
.rq_in1 (rq_in1), // input
.start_in1 (start_in1), // output
.db_in2 (db_in2), // input[7:0]
.rq_in2 (rq_in2), // input
.start_in2 (start_in2), // output
.db_in3 (db_in3), // input[7:0]
.rq_in3 (rq_in3), // input
.start_in3 (start_in3), // output
.db_in4 (db_in4), // input[7:0]
.rq_in4 (rq_in4), // input
.start_in4 (start_in4), // output
.db_in5 (db_in5), // input[7:0]
.rq_in5 (rq_in5), // input
.start_in5 (start_in5), // output
.db_in6 (db_in6), // input[7:0]
.rq_in6 (rq_in6), // input
.start_in6 (start_in6), // output
.db_in7 (db_in7), // input[7:0]
.rq_in7 (rq_in7), // input
.start_in7 (start_in7), // output
.db_out (db_int[0]), // output[7:0]
.rq_out (rq_int[0]), // output
.start_out (start_int[0]) // input
);
status_router8 status_router8_89abcdef_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_in8), // input[7:0]
.rq_in0 (rq_in8), // input
.start_in0 (start_in8), // output
.db_in1 (db_in9), // input[7:0]
.rq_in1 (rq_in9), // input
.start_in1 (start_in9), // output
.db_in2 (db_in10), // input[7:0]
.rq_in2 (rq_in10), // input
.start_in2 (start_in10), // output
.db_in3 (db_in11), // input[7:0]
.rq_in3 (rq_in11), // input
.start_in3 (start_in11), // output
.db_in4 (db_in12), // input[7:0]
.rq_in4 (rq_in12), // input
.start_in4 (start_in12), // output
.db_in5 (db_in13), // input[7:0]
.rq_in5 (rq_in13), // input
.start_in5 (start_in13), // output
.db_in6 (db_in14), // input[7:0]
.rq_in6 (rq_in14), // input
.start_in6 (start_in14), // output
.db_in7 (db_in15), // input[7:0]
.rq_in7 (rq_in15), // input
.start_in7 (start_in15), // output
.db_out (db_int[1]), // output[7:0]
.rq_out (rq_int[1]), // output
.start_out (start_int[1]) // input
);
endmodule
util_modules/status_router4.v 0 → 100644
View file @ 94f77f4d
/*******************************************************************************
* Module: status_router4
* Date:2015-01-31
* Author: andrey
* Description: Routes status data from 4 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* status_router4.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* status_router4.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module status_router4(
input rst,
input clk,
// 4 input channels
input [7:0] db_in0,
input rq_in0,
output start_in0, // only for the first cycle, combinatorial
input [7:0] db_in1,
input rq_in1,
output start_in1, // only for the first cycle, combinatorial
input [7:0] db_in2,
input rq_in2,
output start_in2, // only for the first cycle, combinatorial
input [7:0] db_in3,
input rq_in3,
output start_in3, // only for the first cycle, combinatorial
// output (multiplexed) channel
output [7:0] db_out,
output rq_out,
input start_out // only for the first cycle, combinatorial
);
wire [7:0] db_int [1:0];
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
.db_in1 (db_int[1]), // input[7:0]
.rq_in1 (rq_int[1]), // input
.start_in1 (start_int[1]), // output
.db_out (db_out), // output[7:0]
.rq_out (rq_out), // output
.start_out (start_out) // input
);
status_router2 status_router2_01_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
.db_in1 (db_in1), // input[7:0]
.rq_in1 (rq_in1), // input
.start_in1 (start_in1), // output
.db_out (db_int[0]), // output[7:0]
.rq_out (rq_int[0]), // output
.start_out (start_int[0]) // input
);
status_router2 status_router2_23_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_in2), // input[7:0]
.rq_in0 (rq_in2), // input
.start_in0 (start_in2), // output
.db_in1 (db_in3), // input[7:0]
.rq_in1 (rq_in3), // input
.start_in1 (start_in3), // output
.db_out (db_int[1]), // output[7:0]
.rq_out (rq_int[1]), // output
.start_out (start_int[1]) // input
);
endmodule
util_modules/status_router8.v 0 → 100644
View file @ 94f77f4d
/*******************************************************************************
* Module: status_router8
* Date:2015-01-31
* Author: andrey
* Description: Routes status data from 8 sources
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* status_router8.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* status_router8.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module status_router8(
input rst,
input clk,
// 4 input channels
input [7:0] db_in0,
input rq_in0,
output start_in0, // only for the first cycle, combinatorial
input [7:0] db_in1,
input rq_in1,
output start_in1, // only for the first cycle, combinatorial
input [7:0] db_in2,
input rq_in2,
output start_in2, // only for the first cycle, combinatorial
input [7:0] db_in3,
input rq_in3,
output start_in3, // only for the first cycle, combinatorial
input [7:0] db_in4,
input rq_in4,
output start_in4, // only for the first cycle, combinatorial
input [7:0] db_in5,
input rq_in5,
output start_in5, // only for the first cycle, combinatorial
input [7:0] db_in6,
input rq_in6,
output start_in6, // only for the first cycle, combinatorial
input [7:0] db_in7,
input rq_in7,
output start_in7, // only for the first cycle, combinatorial
// output (multiplexed) channel
output [7:0] db_out,
output rq_out,
input start_out // only for the first cycle, combinatorial
);
//TODO: now just uses 3 of status_router2 (tree) - maybe make a dedicated 4-input one?
wire [7:0] db_int [1:0];
wire [1:0] rq_int;
wire [1:0] start_int; // only for the first cycle, combinatorial
status_router2 status_router2_top_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_int[0]), // input[7:0]
.rq_in0 (rq_int[0]), // input
.start_in0 (start_int[0]), // output
.db_in1 (db_int[1]), // input[7:0]
.rq_in1 (rq_int[1]), // input
.start_in1 (start_int[1]), // output
.db_out (db_out), // output[7:0]
.rq_out (rq_out), // output
.start_out (start_out) // input
);
status_router4 status_router4_0123_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_in0), // input[7:0]
.rq_in0 (rq_in0), // input
.start_in0 (start_in0), // output
.db_in1 (db_in1), // input[7:0]
.rq_in1 (rq_in1), // input
.start_in1 (start_in1), // output
.db_in2 (db_in2), // input[7:0]
.rq_in2 (rq_in2), // input
.start_in2 (start_in2), // output
.db_in3 (db_in3), // input[7:0]
.rq_in3 (rq_in3), // input
.start_in3 (start_in3), // output
.db_out (db_int[0]), // output[7:0]
.rq_out (rq_int[0]), // output
.start_out (start_int[0]) // input
);
status_router4 status_router4_4567_i (
.rst (rst), // input
.clk (clk), // input
.db_in0 (db_in4), // input[7:0]
.rq_in0 (rq_in4), // input
.start_in0 (start_in4), // output
.db_in1 (db_in5), // input[7:0]
.rq_in1 (rq_in5), // input
.start_in1 (start_in5), // output
.db_in2 (db_in6), // input[7:0]
.rq_in2 (rq_in6), // input
.start_in2 (start_in6), // output
.db_in3 (db_in7), // input[7:0]
.rq_in3 (rq_in7), // input
.start_in3 (start_in7), // output
.db_out (db_int[1]), // output[7:0]
.rq_out (rq_int[1]), // output
.start_out (start_int[1]) // input
);
endmodule
x393.v
View file @ 94f77f4d
...@@ -531,6 +531,17 @@ end ...@@ -531,6 +531,17 @@ end
wire [6:0] buf_raddr_chn3; wire [6:0] buf_raddr_chn3;
wire [63:0] buf_rdata_chn3; wire [63:0] buf_rdata_chn3;
wire want_rq4;
wire need_rq4;
wire channel_pgm_en4;
wire [31:0] seq_data4;
wire seq_wr4;
wire seq_set4;
wire seq_done4;
wire buf_wr_chn4;
wire [6:0] buf_waddr_chn4;
wire [63:0] buf_wdata_chn4;
// memory controller comamnd encoders interface // memory controller comamnd encoders interface
wire [2:0] encod_linear_rd_bank; wire [2:0] encod_linear_rd_bank;
wire [ADDRESS_NUMBER-1:0] encod_linear_rd_row; wire [ADDRESS_NUMBER-1:0] encod_linear_rd_row;
...@@ -672,6 +683,191 @@ end ...@@ -672,6 +683,191 @@ end
.enc_done (encod_linear_wr_done) // output reg .enc_done (encod_linear_wr_done) // output reg
); );
// TODO: Create module mcntrl393, incuding all of the mcntrl* modules and related buffers (will; need optional cross-clock (or they can be external?
// TODO: program inter-chennel synchronization (a separate module inside mcntrl393
// All cross-clock - external, buffer I/O sync to external clock
// *********************************** Move to mcntrl393 *********************************************
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.NUM_XFER_BITS(6),
.FRAME_WIDTH_BITS(13),
.FRAME_HEIGHT_BITS(16),
.MCNTRL_SCANLINE_ADDR('h120),
.MCNTRL_SCANLINE_MASK('h3f0),
.MCNTRL_SCANLINE_MODE('h0),
.MCNTRL_SCANLINE_STATUS_CNTRL('h1),
.MCNTRL_SCANLINE_STARTADDR('h2),
.MCNTRL_SCANLINE_FRAME_FULL_WIDTH('h3),
.MCNTRL_SCANLINE_WINDOW_WH('h4),
.MCNTRL_SCANLINE_WINDOW_X0Y0('h5),
.MCNTRL_SCANLINE_WINDOW_STARTXY('h6),
.MCNTRL_SCANLINE_STATUS_REG_ADDR('h4),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS(2)
) mcntrl_linear_rw_chn2_i (
.rst(), // input
.mclk(), // input
.cmd_ad(), // input[7:0]
.cmd_stb(), // input
.status_ad(), // output[7:0]
.status_rq(), // output
.status_start(), // input
.frame_start(), // input
.next_page(), // input
.frame_done(), // output
.line_unfinished(), // output[15:0]
.suspend(), // input
.xfer_want(), // output
.xfer_need(), // output
.xfer_grant(), // input
.xfer_start(), // output
.xfer_bank(), // output[2:0]
.xfer_row(), // output[14:0]
.xfer_col(), // output[6:0]
.xfer_num128(), // output[5:0]
.xfer_done(), // input
.xfer_page() // output[1:0]
);
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10),
.NUM_XFER_BITS(6),
.FRAME_WIDTH_BITS(13),
.FRAME_HEIGHT_BITS(16),
.MCNTRL_SCANLINE_ADDR('h120),
.MCNTRL_SCANLINE_MASK('h3f0),
.MCNTRL_SCANLINE_MODE('h0),
.MCNTRL_SCANLINE_STATUS_CNTRL('h1),
.MCNTRL_SCANLINE_STARTADDR('h2),
.MCNTRL_SCANLINE_FRAME_FULL_WIDTH('h3),
.MCNTRL_SCANLINE_WINDOW_WH('h4),
.MCNTRL_SCANLINE_WINDOW_X0Y0('h5),
.MCNTRL_SCANLINE_WINDOW_STARTXY('h6),
.MCNTRL_SCANLINE_STATUS_REG_ADDR('h4),
.MCNTRL_SCANLINE_PENDING_CNTR_BITS(2)
) mcntrl_linear_rw_chn3_i (
.rst(), // input
.mclk(), // input
.cmd_ad(), // input[7:0]
.cmd_stb(), // input
.status_ad(), // output[7:0]
.status_rq(), // output
.status_start(), // input
.frame_start(), // input
.next_page(), // input
.frame_done(), // output
.line_unfinished(), // output[15:0]
.suspend(), // input
.xfer_want(), // output
.xfer_need(), // output
.xfer_grant(), // input
.xfer_start(), // output
.xfer_bank(), // output[2:0]
.xfer_row(), // output[14:0]
.xfer_col(), // output[6:0]
.xfer_num128(), // output[5:0]
.xfer_done(), // input
.xfer_page() // output[1:0]
);
/* Instance template for module mcntrl_ps_pio */
mcntrl_ps_pio #(
.MCNTRL_PS_ADDR('h100),
.MCNTRL_PS_MASK('h3e0),
.MCNTRL_PS_STATUS_REG_ADDR('h2),
.MCNTRL_PS_EN_RST('h0),
.MCNTRL_PS_CMD('h1),
.MCNTRL_PS_STATUS_CNTRL('h2)
) mcntrl_ps_pio_i (
.rst(), // input
.mclk(), // input
.cmd_ad(), // input[7:0]
.cmd_stb(), // input
.status_ad(), // output[7:0]
.status_rq(), // output
.status_start(), // input
.port0_clk(), // input
.port0_re(), // input
.port0_regen(), // input
.port0_addr(), // input[9:0]
.port0_data(), // output[31:0]
.port1_clk(), // input
.port1_we(), // input
.port1_addr(), // input[9:0]
.port1_data(), // input[31:0]
.want_rq0(), // output reg
.need_rq0(), // output reg
.channel_pgm_en0(), // input
.seq_data0(), // output[9:0]
.seq_set0(), // output
.seq_done0(), // input
.buf_wr_chn0(), // input
.buf_waddr_chn0(), // input[6:0]
.buf_wdata_chn0(), // input[63:0]
.want_rq1(), // output reg
.need_rq1(), // output reg
.channel_pgm_en1(), // input
.seq_done1(), // input
.buf_rd_chn1(), // input
.buf_raddr_chn1(), // input[6:0]
.buf_rdata_chn1() // output[63:0]
);
/* Instance template for module cmd_encod_linear_mux */
cmd_encod_linear_mux #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10)
) cmd_encod_linear_mux_i (
.clk(), // input
.bank2(), // input[2:0]
.row2(), // input[14:0]
.start_col2(), // input[6:0]
.num128_2(), // input[5:0]
.start2(), // input
.bank3(), // input[2:0]
.row3(), // input[14:0]
.start_col3(), // input[6:0]
.num128_3(), // input[5:0]
.start3(), // input
.bank(), // output[2:0]
.row(), // output[14:0]
.start_col(), // output[6:0]
.num128(), // output[5:0]
.start_rd(), // output
.start_wr() // output
);
/* Instance template for module cmd_encod_tiled_mux */
cmd_encod_tiled_mux #(
.ADDRESS_NUMBER(15),
.COLADDR_NUMBER(10)
) cmd_encod_tiled_mux_i (
.clk(), // input
.bank4(), // input[2:0]
.row4(), // input[14:0]
.col4(), // input[6:0]
.rowcol_inc4(), // input[21:0]
.num_rows4(), // input[5:0]
.num_cols4(), // input[5:0]
.keep_open4(), // input
.start4(), // input
.bank(), // output[2:0]
.row(), // output[14:0]
.col(), // output[6:0]
.rowcol_inc(), // output[21:0]
.num_rows(), // output[5:0]
.num_cols(), // output[5:0]
.keep_open(), // output
.start_rd(), // output
.start_wr() // output
);
memctrl16 #( memctrl16 #(
.DLY_LD (DLY_LD), .DLY_LD (DLY_LD),
...@@ -802,6 +998,17 @@ end ...@@ -802,6 +998,17 @@ end
.buf_raddr_chn3 (buf_raddr_chn3), // output[6:0] .buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0] .buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
.need_rq4 (need_rq4), // input
.channel_pgm_en4 (channel_pgm_en4), // output reg
.seq_data4 (seq_data4), // input[31:0]
.seq_wr4 (seq_wr4), // input
.seq_set4 (seq_set4), // input
.seq_done4 (seq_done4), // output
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.SDRST (SDRST), // output .SDRST (SDRST), // output
.SDCLK (SDCLK), // output .SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output .SDNCLK (SDNCLK), // output
...@@ -822,6 +1029,7 @@ end ...@@ -822,6 +1029,7 @@ end
.tmp_debug (tmp_debug) // output[11:0] .tmp_debug (tmp_debug) // output[11:0]
); );
// *********************************** End of move to mcntrl393 *********************************************
//MEMCLK //MEMCLK
......
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