Fixed typos

.settings/com.elphel.vdt.VivadoBitstream.prefs

@@ -3,6 +3,5 @@ VivadoBitstream_105_force=true
 VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
 VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
 VivadoBitstream_124_force=true
-VivadoBitstream_125_force=true
-com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->
+com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
 eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

@@ -6,9 +6,10 @@ VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.x
 VivadoSynthesis_122_SkipSnapshotSynth=true
 VivadoSynthesis_123_ResetProject=true
 VivadoSynthesis_123_SkipSnapshotSynth=true
+VivadoSynthesis_124_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->
 VivadoSynthesis_127_verbose=true
 VivadoSynthesis_81_parser_mode=1
 VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
 VivadoSynthesis_95_ShowInfo=true
-com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->
+com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
 eclipse.preferences.version=1

.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->
 eclipse.preferences.version=1
 iverilog_100_TopModulesOther=glbl<-@\#\#@->
 iverilog_101_TopModulesOther=glbl<-@\#\#@->
@@ -6,15 +6,20 @@ iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_102_TopModulesOther=glbl<-@\#\#@->
 iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
+iverilog_103_TopModulesOther=glbl<-@\#\#@->
 iverilog_104_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
+iverilog_105_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->
+iverilog_106_IncludeDir=${verilog_project_loc}_sata/x393/includes<-@\#\#@->${verilog_project_loc}_sata/x393/ddr3<-@\#\#@->
 iverilog_109_ShowNoProblem=true
 iverilog_110_ShowNoProblem=true
 iverilog_110_ShowWarnings=false
+iverilog_111_ShowNoProblem=true
 iverilog_113_SaveLogsPreprocessor=false
 iverilog_113_SaveLogsSimulator=true
 iverilog_114_SaveLogsSimulator=true
+iverilog_115_SaveLogsSimulator=true
 iverilog_121_GrepFindErrWarn=error|warning|sorry
 iverilog_77_Param_Exe=/usr/local/bin/iverilog
 iverilog_78_VVP_Exe=/usr/local/bin/vvp

axi/axibram_write.v

@@ -58,7 +58,7 @@ module  axibram_write #(
    input  [11:0] wid,     // WID[11:0], input
    input         wlast,   // WLAST, input
    input  [ 3:0] wstb,    // WSTRB[3:0], input
-// AXI PS Master GP0: Write Responce
+// AXI PS Master GP0: Write response
    output        bvalid,  // BVALID, output
    input         bready,  // BREADY, input
    output [11:0] bid,     // BID[11:0], output

axi/cmprs_afi_mux.v

@@ -542,7 +542,7 @@ items_left
         .we         (cmd_we)    // output
     );
     
-    wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write responce one
+    wire [53:0] chunk_ptr_rd01; // [0:1]; // combines 2 pointers - write one and write response one
 
     cmprs_afi_mux_ptr cmprs_afi_mux_ptr_i (
         .hclk                (hclk),                // input

util_modules/resync_data.v

@@ -19,6 +19,19 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
  *******************************************************************************/
 `timescale 1ns/1ps
 

wrap/iserdes_mem.v

@@ -51,7 +51,7 @@ module  iserdes_mem #
 );
     wire   [3:0] dout_le;
     assign dout = MSB_FIRST ? {dout_le[0], dout_le[1], dout_le[2], dout_le[3]} : dout_le;
-`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instanciate actual ISERDESE2 (can not be simulated because of encrypted )           
+`ifndef OPEN_SOURCE_ONLY  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           
      ISERDESE2 #(
          .DATA_RATE                  ("DDR"),
          .DATA_WIDTH                 (4),

wrap/ram18p_var_w_var_r.v

@@ -206,8 +206,8 @@ module  ram18p_32w_32r
       input                  [ 3:0] web,      // write byte enable
       input                  [35:0] data_in  // data out
     );
-    localparam  PWIDTH_WR=72;
-    localparam  PWIDTH_RD=72;
+    localparam  PWIDTH_WR=36;
+    localparam  PWIDTH_RD=36;
     
     RAMB18E1
     #(
@@ -459,7 +459,7 @@ module  ram18p_32w_lt32r
       input                         [ 3:0] web,      // write byte enable
       input                         [35:0] data_in   // data out
     );
-    localparam  PWIDTH_WR = 72;
+    localparam  PWIDTH_WR = 36;
     localparam  PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
     localparam  WIDTH_RD  = 1 << LOG2WIDTH_RD;
     localparam  WIDTH_RDP = 1 << (LOG2WIDTH_RD-3);

x393.v

@@ -178,7 +178,7 @@ module  x393 #(
     wire   [11:0]  maxi0_wid;         // WID[11:0], input
     wire           maxi0_wlast;       // WLAST, input
     wire   [ 3:0]  maxi0_wstb;        // WSTRB[3:0], input
-// AXI PS Master GP0: Write Responce
+// AXI PS Master GP0: Write response
     wire           maxi0_bvalid;      // BVALID, output
     wire           maxi0_bready;      // BREADY, input
     wire   [11:0]  maxi0_bid;         // BID[11:0], output
@@ -2737,7 +2737,7 @@ assign axi_grst = axi_rst_pre;
     .MAXIGP0WID     (maxi0_wid[11:0]),       // AXI PS Master GP0 WID[11:0], output
     .MAXIGP0WLAST   (maxi0_wlast),         // AXI PS Master GP0 WLAST, output
     .MAXIGP0WSTRB   (maxi0_wstb[3:0]),    // AXI PS Master GP0 WSTRB[3:0], output
-// AXI PS Master GP0: Write Responce
+// AXI PS Master GP0: Write response
     .MAXIGP0BVALID  (maxi0_bvalid),       // AXI PS Master GP0 BVALID, input
     .MAXIGP0BREADY  (maxi0_bready),       // AXI PS Master GP0 BREADY, output
     .MAXIGP0BID     (maxi0_bid[11:0]),       // AXI PS Master GP0 BID[11:0], input
@@ -2785,7 +2785,7 @@ assign axi_grst = axi_rst_pre;
     .MAXIGP1WID(),               // AXI PS Master GP1 WID[11:0], output
     .MAXIGP1WLAST(),             // AXI PS Master GP1 WLAST, output
     .MAXIGP1WSTRB(),             // AXI PS Master GP1 WSTRB[3:0], output
-// AXI PS Master GP1: Write Responce
+// AXI PS Master GP1: Write response
     .MAXIGP1BVALID(),            // AXI PS Master GP1 BVALID, input
     .MAXIGP1BREADY(),            // AXI PS Master GP1 BREADY, output
     .MAXIGP1BID(),               // AXI PS Master GP1 BID[11:0], input
@@ -2833,7 +2833,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIGP0WID        (saxi0_wid),      // AXI PS Slave GP0 WID[5:0], input
     .SAXIGP0WLAST      (saxi0_wlast),    // AXI PS Slave GP0 WLAST, input
     .SAXIGP0WSTRB      (saxi0_wstrb),    // AXI PS Slave GP0 WSTRB[3:0], input
-// AXI PS Slave GP0: Write Responce
+// AXI PS Slave GP0: Write response
     .SAXIGP0BVALID     (saxi0_bvalid),   // AXI PS Slave GP0 BVALID, output
     .SAXIGP0BREADY     (saxi0_bready),   // AXI PS Slave GP0 BREADY, input
     .SAXIGP0BID        (saxi0_bid),      // AXI PS Slave GP0 BID[5:0], output //TODO:  Update range !!!
@@ -2881,7 +2881,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIGP1WID        (saxi1_wid),      // AXI PS Slave GP1 WID[5:0], input
     .SAXIGP1WLAST      (saxi1_wlast),    // AXI PS Slave GP1 WLAST, input
     .SAXIGP1WSTRB      (saxi1_wstrb),    // AXI PS Slave GP1 WSTRB[3:0], input
-// AXI PS Slave GP1: Write Responce
+// AXI PS Slave GP1: Write response
     .SAXIGP1BVALID     (saxi1_bvalid),   // AXI PS Slave GP1 BVALID, output
     .SAXIGP1BREADY     (saxi1_bready),   // AXI PS Slave GP1 BREADY, input
     .SAXIGP1BID        (saxi1_bid),      // AXI PS Slave GP1 BID[5:0], output //TODO:  Update range !!!
@@ -2935,7 +2935,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIHP0WCOUNT        (afi0_wcount),            // AXI PS Slave HP0 WCOUNT[7:0], output
     .SAXIHP0WACOUNT       (afi0_wacount),           // AXI PS Slave HP0 WACOUNT[5:0], output
     .SAXIHP0WRISSUECAP1EN (afi0_wrissuecap1en),     // AXI PS Slave HP0 WRISSUECAP1EN, input
-// AXI PS Slave HP0: Write Responce
+// AXI PS Slave HP0: Write response
     .SAXIHP0BVALID        (afi0_bvalid),            // AXI PS Slave HP0 BVALID, output
     .SAXIHP0BREADY        (afi0_bready),            // AXI PS Slave HP0 BREADY, input
     .SAXIHP0BID           (afi0_bid),               // AXI PS Slave HP0 BID[5:0], output
@@ -2989,7 +2989,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIHP1WCOUNT        (afi1_wcount),            // AXI PS Slave HP1 WCOUNT[7:0], output
     .SAXIHP1WACOUNT       (afi1_wacount),           // AXI PS Slave HP1 WACOUNT[5:0], output
     .SAXIHP1WRISSUECAP1EN (afi1_wrissuecap1en),     // AXI PS Slave HP1 WRISSUECAP1EN, input
-// AXI PS Slave HP1: Write Responce
+// AXI PS Slave HP1: Write response
     .SAXIHP1BVALID        (afi1_bvalid),            // AXI PS Slave HP1 BVALID, output
     .SAXIHP1BREADY        (afi1_bready),            // AXI PS Slave HP1 BREADY, input
     .SAXIHP1BID           (afi1_bid),               // AXI PS Slave HP1 BID[5:0], output
@@ -3043,7 +3043,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIHP2WCOUNT        (afi2_wcount),            // AXI PS Slave HP2 WCOUNT[7:0], output
     .SAXIHP2WACOUNT       (afi2_wacount),           // AXI PS Slave HP2 WACOUNT[5:0], output
     .SAXIHP2WRISSUECAP1EN (afi2_wrissuecap1en),     // AXI PS Slave HP2 WRISSUECAP1EN, input
-// AXI PS Slave HP2: Write Responce
+// AXI PS Slave HP2: Write response
     .SAXIHP2BVALID        (afi2_bvalid),            // AXI PS Slave HP2 BVALID, output
     .SAXIHP2BREADY        (afi2_bready),            // AXI PS Slave HP2 BREADY, input
     .SAXIHP2BID           (afi2_bid),               // AXI PS Slave HP2 BID[5:0], output
@@ -3097,7 +3097,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIHP3WCOUNT(),            // AXI PS Slave HP3 WCOUNT[7:0], output
     .SAXIHP3WACOUNT(),           // AXI PS Slave HP3 WACOUNT[5:0], output
     .SAXIHP3WRISSUECAP1EN(),     // AXI PS Slave HP3 WRISSUECAP1EN, input
-// AXI PS Slave HP3: Write Responce
+// AXI PS Slave HP3: Write response
     .SAXIHP3BVALID(),            // AXI PS Slave HP3 BVALID, output
     .SAXIHP3BREADY(),            // AXI PS Slave HP3 BREADY, input
     .SAXIHP3BID(),               // AXI PS Slave HP3 BID[5:0], output
@@ -3148,7 +3148,7 @@ assign axi_grst = axi_rst_pre;
     .SAXIACPWID(),               // AXI PS Slave ACP WID[2:0], input
     .SAXIACPWLAST(),             // AXI PS Slave ACP WLAST, input
     .SAXIACPWSTRB(),             // AXI PS Slave ACP WSTRB[7:0], input
-// AXI PS Slave ACP: Write Responce
+// AXI PS Slave ACP: Write response
     .SAXIACPBVALID(),            // AXI PS Slave ACP BVALID, output
     .SAXIACPBREADY(),            // AXI PS Slave ACP BREADY, input
     .SAXIACPBID(),               // AXI PS Slave ACP BID[2:0], output

x393_testbench01.tf

@@ -17,6 +17,19 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
  *******************************************************************************/
 `timescale 1ns/1ps
 `include "system_defines.vh"

x393_testbench02.tf

@@ -17,6 +17,19 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
  *******************************************************************************/
 `timescale 1ns/1ps
 `include "system_defines.vh"

x393_testbench03.tf

@@ -17,6 +17,19 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
  *******************************************************************************/
 `timescale 1ns/1ps
 `include "system_defines.vh"